CoreSight

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[PATCH v3 00/19] perf cs-etm: Queue context packets for frontend

by James Clark

Fix thread tracking when decoding Coresight trace and add a new test for it. The new test is added as a Perf test workload instead of a custom binary with its own build system, but this requires a new feature in Perf test to pass in control pipes which can enable and disable events. This scopes the recording to just the workload and helps to reduce the amount of data recorded in tracing tests. With this new feature we can re-write all of the Coresight tests to make use of it and remove the remaining binaries which fixes the following issues: * They didn't work in out of source builds * A lot of the tests unnecessarily required root and didn't skip without it * They were mainly qualitative tests which didn't look for specific behavior Most importantly, the long build and runtime has been reduced. On a Radxa Orion O6, unroll_loop_thread.c took 37s to compile which is longer than the entire Perf build. Now the build time is negligible and the before and after test runtimes for all the Coresight tests are: | N1SDP | Orion O6 ----------------------------------- Before | 4m 0s | 14m 49s After | 26s | 56s ----------------------------------- Signed-off-by: James Clark <james.clark(a)linaro.org> --- Changes in v3: - Minor sashiko comments - Close some more pipes - Fix warning messages - Error handling improvements - Pass packet into cs_etm__synth_instruction_sample() - Fixup stale comment (Leo) - Link to v2: https://lore.kernel.org/r/20260602-james-cs-context-tracking-fix-v2-0-85b5c… Changes in v2: - Add --workload-ctl option to Perf test - Re-write all the Coresight tests and speed them up - Pass packet to memory access function so frontend can use either the previous or current packet's EL - Link to v1: https://lore.kernel.org/r/20260526-james-cs-context-tracking-fix-v1-0-ebd60… --- James Clark (19): perf cs-etm: Queue context packets for frontend perf test: Add workload-ctl option perf test: Add a workload that forces context switches perf test cs-etm: Test process attribution perf test: Add deterministic workload perf test cs-etm: Replace unroll loop thread with deterministic decode test perf test cs-etm: Remove asm_pure_loop test perf test cs-etm: Replace memcpy test with raw dump stress test perf test: Add named_threads workload perf test cs-etm: Test decoding for concurrent threads test perf test cs-etm: Remove duplicate branch tests perf test cs-etm: Skip if not root perf test cs-etm: Reduce snapshot size perf test cs-etm: Speed up basic test perf test cs-etm: Remove unused Coresight workloads perf test cs-etm: Make disassembly test use kcore perf test cs-etm: Add all branch instructions to test perf test cs-etm: Speed up disassembly test perf test cs-etm: Move existing tests to coresight folder Documentation/trace/coresight/coresight-perf.rst | 78 +------ MAINTAINERS | 2 - tools/perf/Documentation/perf-test.txt | 18 +- tools/perf/Makefile.perf | 14 +- tools/perf/scripts/python/arm-cs-trace-disasm.py | 20 +- tools/perf/tests/builtin-test.c | 187 +++++++++++++++- tools/perf/tests/shell/coresight/Makefile | 29 --- .../perf/tests/shell/coresight/Makefile.miniconfig | 14 -- tools/perf/tests/shell/coresight/asm_pure_loop.sh | 22 -- .../tests/shell/coresight/asm_pure_loop/.gitignore | 1 - .../tests/shell/coresight/asm_pure_loop/Makefile | 34 --- .../shell/coresight/asm_pure_loop/asm_pure_loop.S | 30 --- .../tests/shell/coresight/concurrent_threads.sh | 45 ++++ .../tests/shell/coresight/context_switch_thread.sh | 69 ++++++ tools/perf/tests/shell/coresight/deterministic.sh | 71 +++++++ .../tests/shell/coresight/memcpy_thread/.gitignore | 1 - .../tests/shell/coresight/memcpy_thread/Makefile | 33 --- .../shell/coresight/memcpy_thread/memcpy_thread.c | 80 ------- .../tests/shell/coresight/memcpy_thread_16k_10.sh | 22 -- .../perf/tests/shell/coresight/raw_dump_stress.sh | 48 +++++ .../shell/{ => coresight}/test_arm_coresight.sh | 43 ++-- .../{ => coresight}/test_arm_coresight_disasm.sh | 17 +- .../tests/shell/coresight/thread_loop/.gitignore | 1 - .../tests/shell/coresight/thread_loop/Makefile | 33 --- .../shell/coresight/thread_loop/thread_loop.c | 85 -------- .../shell/coresight/thread_loop_check_tid_10.sh | 23 -- .../shell/coresight/thread_loop_check_tid_2.sh | 23 -- .../shell/coresight/unroll_loop_thread/.gitignore | 1 - .../shell/coresight/unroll_loop_thread/Makefile | 33 --- .../unroll_loop_thread/unroll_loop_thread.c | 75 ------- .../tests/shell/coresight/unroll_loop_thread_10.sh | 22 -- tools/perf/tests/shell/lib/coresight.sh | 134 ------------ tools/perf/tests/tests.h | 3 + tools/perf/tests/workloads/Build | 4 + tools/perf/tests/workloads/context_switch_loop.c | 101 +++++++++ tools/perf/tests/workloads/deterministic.c | 39 ++++ tools/perf/tests/workloads/named_threads.c | 109 ++++++++++ tools/perf/util/cs-etm-decoder/cs-etm-decoder.c | 21 +- tools/perf/util/cs-etm.c | 234 ++++++++++++--------- tools/perf/util/cs-etm.h | 8 +- 40 files changed, 889 insertions(+), 938 deletions(-) --- base-commit: 5f0ca6b80b12bab1ce06839cdffb6148bb650ff4 change-id: 20260515-james-cs-context-tracking-fix-754998bae7ed Best regards, -- James Clark <james.clark(a)linaro.org>

3 months, 3 weeks

Re: [PATCH v7 09/13] coresight: etm4x: missing cscfg_csdev_disable_active_config() in perf enable

by Leo Yan

On Tue, May 19, 2026 at 04:48:08PM +0100, Yeoreum Yun wrote: > In the perf enable path, there are missing cases where > cscfg_csdev_disable_active_config() is not called: > > - Branch broadcast is selected but not supported by the hardware > - etm4_enable_hw() fails > > This can lead to a leak of config_desc->active_cnt. > Fix this by properly calling cscfg_csdev_disable_active_config() > in these error paths. > > Fixes: 810ac401db1f ("coresight: etm4x: Add complex configuration handlers to etmv4") > Signed-off-by: Yeoreum Yun <yeoreum.yun(a)arm.com> > --- > .../hwtracing/coresight/coresight-etm4x-core.c | 18 ++++++++++++------ > 1 file changed, 12 insertions(+), 6 deletions(-) > > diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c > index f0a9f2ef4b27..0889937811cb 100644 > --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c > +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c > @@ -899,6 +899,8 @@ static int etm4_parse_event_config(struct coresight_device *csdev, > * Missing BB support could cause silent decode errors > * so fail to open if it's not supported. > */ > + if (cfg_hash) > + cscfg_csdev_disable_active_config(csdev); > ret = -EINVAL; > goto out; > } else { > @@ -915,6 +917,7 @@ static int etm4_enable_perf(struct coresight_device *csdev, > struct coresight_path *path) > { > struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); > + struct perf_event_attr *attr = &event->attr; > int ret; > > if (WARN_ON_ONCE(drvdata->cpu != smp_processor_id())) > @@ -926,7 +929,7 @@ static int etm4_enable_perf(struct coresight_device *csdev, > /* Configure the tracer based on the session's specifics */ > ret = etm4_parse_event_config(csdev, event); > if (ret) > - goto out; > + goto err; > > drvdata->trcid = path->trace_id; > > @@ -935,16 +938,19 @@ static int etm4_enable_perf(struct coresight_device *csdev, > > /* And enable it */ > ret = etm4_enable_hw(drvdata); > - > -out: > - /* Failed to start tracer; roll back to DISABLED mode */ > if (ret) { > - coresight_set_mode(csdev, CS_MODE_DISABLED); > - return ret; > + if (ATTR_CFG_GET_FLD(attr, configid)) > + cscfg_csdev_disable_active_config(csdev); > + goto err; > } > > csdev->path = path; > return 0; > + > +err: > + /* Failed to start tracer; roll back to DISABLED mode */ > + coresight_set_mode(csdev, CS_MODE_DISABLED); > + return ret; > } Seems to me, it is not readable if spread error handling into both child and parent functions. I would like we can stick to use the same function for resource allocation and rollback for failures. How about below change (I did not verify it yet): diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c index 0889937811cb..8347efb2069b 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c @@ -794,8 +794,7 @@ static int etm4_parse_event_config(struct coresight_device *csdev, .ATTR_CFG_FLD_timestamp_CFG = U64_MAX, }; struct perf_event_attr *attr = &event->attr; - unsigned long cfg_hash; - int preset, cc_threshold; + int cc_threshold; u8 ts_level; /* Clear configuration from previous run */ @@ -882,16 +881,6 @@ static int etm4_parse_event_config(struct coresight_device *csdev, /* bit[12], Return stack enable bit */ config->cfg |= TRCCONFIGR_RS; - /* - * Set any selected configuration and preset. A zero configid means no - * configuration active, preset = 0 means no preset selected. - */ - cfg_hash = ATTR_CFG_GET_FLD(attr, configid); - if (cfg_hash) { - preset = ATTR_CFG_GET_FLD(attr, preset); - ret = cscfg_csdev_enable_active_config(csdev, cfg_hash, preset); - } - /* branch broadcast - enable if selected and supported */ if (ATTR_CFG_GET_FLD(attr, branch_broadcast)) { if (!caps->trcbb) { @@ -899,8 +888,6 @@ static int etm4_parse_event_config(struct coresight_device *csdev, * Missing BB support could cause silent decode errors * so fail to open if it's not supported. */ - if (cfg_hash) - cscfg_csdev_disable_active_config(csdev); ret = -EINVAL; goto out; } else { @@ -918,7 +905,8 @@ static int etm4_enable_perf(struct coresight_device *csdev, { struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); struct perf_event_attr *attr = &event->attr; - int ret; + unsigned long cfg_hash; + int preset, ret; if (WARN_ON_ONCE(drvdata->cpu != smp_processor_id())) return -EINVAL; @@ -931,6 +919,18 @@ static int etm4_enable_perf(struct coresight_device *csdev, if (ret) goto err; + /* + * Set any selected configuration and preset. A zero configid means no + * configuration active, preset = 0 means no preset selected. + */ + cfg_hash = ATTR_CFG_GET_FLD(attr, configid); + if (cfg_hash) { + preset = ATTR_CFG_GET_FLD(attr, preset); + ret = cscfg_csdev_enable_active_config(csdev, cfg_hash, preset); + if (ret) + goto err; + } + drvdata->trcid = path->trace_id; /* Populate pause state */ @@ -938,15 +938,15 @@ static int etm4_enable_perf(struct coresight_device *csdev, /* And enable it */ ret = etm4_enable_hw(drvdata); - if (ret) { - if (ATTR_CFG_GET_FLD(attr, configid)) - cscfg_csdev_disable_active_config(csdev); - goto err; - } + if (ret) + goto err_enable_hw; csdev->path = path; return 0; +err_enable_hw: + if (cfg_hash) + cscfg_csdev_disable_active_config(csdev); err: /* Failed to start tracer; roll back to DISABLED mode */ coresight_set_mode(csdev, CS_MODE_DISABLED);

3 months, 3 weeks

Re: [PATCH v7 08/13] coresight: etm4x: fix inconsistencies with sysfs configuration

by Leo Yan

On Thu, May 28, 2026 at 03:26:57PM +0100, Yeoreum Yun wrote: [...] > > > @@ -47,7 +47,7 @@ static int etm4_cfg_map_reg_offset(struct etmv4_drvdata *drvdata, > > > struct cscfg_regval_csdev *reg_csdev, u32 offset) > > > { > > > int err = -EINVAL, idx; > > > - struct etmv4_config *drvcfg = &drvdata->config; > > > + struct etmv4_config *drvcfg = &drvdata->active_config; > > > > Wouldn't it make more sense to keep using drvdata->config for cfgfs? > > This would avoid cfgfs updating the active configuration while a session > > is enabled. > > > > My understanding is after refactoring cfgfs, we will never expose > > active_config or config anymore so this should not an issue. Before > > that, maybe we just keep to use config so can avoid mess. > > I don't think so. since the cfgfs's config is updated right before > enable and in this patchset, It's applied after "take the mode". > > If we do it into drvdta->config, then contention would be increased > with the access of sysfs and that nullifies almost this patch purpose > and because of we use "one config" this makes a corruption with perf > and sysfs. Here have two different contention: the contention between sysfs and cfgfs, and the contention between cfgfs and a runtime config (active config). My suggestion is to avoid the later contention, which is the main idea in this series that avoid the runtime config is modified in the middle of a session. That said, I have no strong opinion. > > > static void etm4_enable_sysfs_smp_call(void *info) > > > { > > > struct etm4_enable_arg *arg = info; > > > + struct etmv4_drvdata *drvdata; > > > struct coresight_device *csdev; > > > + unsigned long cfg_hash; > > > + int preset; > > > > > > if (WARN_ON(!arg)) > > > return; > > > > > > - csdev = arg->drvdata->csdev; > > > + drvdata = arg->drvdata; > > > + csdev = drvdata->csdev; > > > if (!coresight_take_mode(csdev, CS_MODE_SYSFS)) { > > > /* Someone is already using the tracer */ > > > arg->rc = -EBUSY; > > > return; > > > } > > > > > > - arg->rc = etm4_enable_hw(arg->drvdata); > > > + /* enable any config activated by configfs */ > > > + cscfg_config_sysfs_get_active_cfg(&cfg_hash, &preset); > > > > > > - /* The tracer didn't start */ > > > + drvdata->active_config = arg->config; > > > > Can move this down to just before drvdata->trcid assignment so cscfg > > operations can be put together? > > No. Copy the arg->config must be before cscfg_csdev_enable_active_config(). > If that's after, it overrides the "preset" and this is different from > the former behavior. Please copy config first, then do cscfg stuffs. > > > + arg->rc = etm4_enable_hw(drvdata); > > > if (arg->rc) { > > > - coresight_set_mode(csdev, CS_MODE_DISABLED); > > > - return; > > > + cscfg_csdev_disable_active_config(csdev); > > > + goto err; > > > > Add a new goto tag (like err_enable_hw) for the disable_active_config > > rollback? > > This is only place where cscfg_csdev_disable_active_config(). > Why do we need to goto for cleanup where there is no duplication? It is about to use a central place for handling errors. > > > @@ -1449,7 +1458,7 @@ static void etm4_init_arch_data(void *info) > > > > > > /* EXLEVEL_S, bits[19:16] Secure state instruction tracing */ > > > caps->s_ex_level = FIELD_GET(TRCIDR3_EXLEVEL_S_MASK, etmidr3); > > > - drvdata->config.s_ex_level = caps->s_ex_level; > > > + config->s_ex_level = caps->s_ex_level; > > > > config->s_ex_level is redundant and not really a configuration item. > > We should use caps->s_ex_level instead of config->s_ex_level wherever > > it is used. > > Agree, but this includes it should change the omse function > declations to pass "caps" argument: > - etm4_set_comparator_filter() > - etm4_set_start_stop_filter() > > If that's okay, I'll respin with it. This is fine for me. Thanks, Leo

3 months, 3 weeks

Re: [PATCH v7 03/13] coresight: etm4x: introduce ETM_MAX_SEQ_TRANSITIONS

by Suzuki K Poulose

On 19/05/2026 16:48, Yeoreum Yun wrote: > According to IHI006H Embedded Trace Macrocell Architecture > Specification [0], n could be 0-2 for TCRSEQEVR<n> when > TCRIDR5.NUMSEQSTATE is 0b100. > > Therefore, introduce ETM_MAX_SEQ_TRANSITIONS macro and apply this > in TCRSEQEVR<n> relevant fields. > > Link: https://developer.arm.com/documentation/ihi0064/latest/ [0] > Suggestedby: Leo Yan <leo.yan(a)arm.com> > Signed-off-by: Yeoreum Yun <yeoreum.yun(a)arm.com> > --- > drivers/hwtracing/coresight/coresight-etm4x-cfg.c | 2 +- > drivers/hwtracing/coresight/coresight-etm4x.h | 5 +++-- > 2 files changed, 4 insertions(+), 3 deletions(-) > > diff --git a/drivers/hwtracing/coresight/coresight-etm4x-cfg.c b/drivers/hwtracing/coresight/coresight-etm4x-cfg.c > index c302072b293a..e1a59b434505 100644 > --- a/drivers/hwtracing/coresight/coresight-etm4x-cfg.c > +++ b/drivers/hwtracing/coresight/coresight-etm4x-cfg.c > @@ -76,7 +76,7 @@ static int etm4_cfg_map_reg_offset(struct etmv4_drvdata *drvdata, > } else if ((offset & GENMASK(11, 4)) == TRCSEQEVRn(0)) { > /* sequencer state control registers */ > idx = (offset & GENMASK(3, 0)) / 4; > - if (idx < ETM_MAX_SEQ_STATES) { > + if (idx < ETM_MAX_SEQ_TRANSITIONS) { > reg_csdev->driver_regval = &drvcfg->seq_ctrl[idx]; > err = 0; > } > diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h > index 89d81ce4e04e..60e08ab085c5 100644 > --- a/drivers/hwtracing/coresight/coresight-etm4x.h > +++ b/drivers/hwtracing/coresight/coresight-etm4x.h > @@ -614,6 +614,7 @@ static inline u32 etm4_res_sel_pair(u8 res_sel_idx) > #define ETM_MAX_NR_PE 8 > #define ETMv4_MAX_CNTR 4 > #define ETM_MAX_SEQ_STATES 4 > +#define ETM_MAX_SEQ_TRANSITIONS (ETM_MAX_SEQ_STATES - 1) Similar to the other comment on the patch, please don't tie this to SEQ_STATES. Simpl define. #define ETM_MAX_SEQ_CTRLS 3 Suzuki > #define ETM_MAX_EXT_INP_SEL 4 > #define ETM_MAX_EXT_INP 256 > #define ETM_MAX_EXT_OUT 4 > @@ -877,7 +878,7 @@ struct etmv4_config { > u32 vipcssctlr; > u8 seq_idx; > u8 syncfreq; > - u32 seq_ctrl[ETM_MAX_SEQ_STATES]; > + u32 seq_ctrl[ETM_MAX_SEQ_TRANSITIONS]; > u32 seq_rst; > u32 seq_state; > u8 cntr_idx; > @@ -928,7 +929,7 @@ struct etmv4_save_state { > u32 trcvissctlr; > u32 trcvipcssctlr; > > - u32 trcseqevr[ETM_MAX_SEQ_STATES]; > + u32 trcseqevr[ETM_MAX_SEQ_TRANSITIONS]; > u32 trcseqrstevr; > u32 trcseqstr; > u32 trcextinselr;

3 months, 3 weeks

Re: [PATCH v9 4/4] coresight: cti: expose banked sysfs registers for Qualcomm extended CTI

by Leo Yan

On Mon, Jun 01, 2026 at 10:08:55AM +0800, Yingchao Deng (Consultant) wrote: [...] > I noticed that among the new sysfs knobs in this series, the > integration test registers (ittrigin[1-3], ittrigout[1-3], > ittrigoutack[1-3], ittriginack[1-3]) have no existing documentation > for their base (index-0) counterparts, which were added long before > this series. Ah, thanks for pointing out the missed piece! > Two options for patch 5/5: > > (a) Document only the knobs whose base versions are already > documented (triginstatus[1-3] and trigoutstatus[1-3]). > > (b) Document everything in patch 5/5 — both the new indexed > variants and the previously missing base IT register entries. Please use option (b). Could you fold the code piece below into patch 5? Note, we cannot merge ittrigin and ittrigin[1-3] into a single entry because they were introduced in different kernel versions. @Mike, if any chance you could give a review on this? ---8<--- --- a/Documentation/ABI/testing/sysfs-bus-coresight-devices-cti +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-cti @@ -134,6 +134,60 @@ KernelVersion: 5.7 Contact: Mike Leach or Mathieu Poirier Description: (Read) read current status of output trigger signals. +What: /sys/bus/coresight/devices/<cti-name>/regs/itctrl +Date: March 2020 +KernelVersion 5.7 +Contact: coresight(a)lists.linaro.org +Description: (RW) Control integration mode. + +What: /sys/bus/coresight/devices/<cti-name>/regs/itchin +Date: March 2020 +KernelVersion 5.7 +Contact: coresight(a)lists.linaro.org +Description: (Read) Read the values of the CTCHIN inputs. + +What: /sys/bus/coresight/devices/<cti-name>/regs/itchinack +Date: March 2020 +KernelVersion 5.7 +Contact: coresight(a)lists.linaro.org +Description: (Write) Write the value of the CTCHINACK input. + +What: /sys/bus/coresight/devices/<cti-name>/regs/ittrigin +Date: March 2020 +KernelVersion 5.7 +Contact: coresight(a)lists.linaro.org +Description: (Read) Read the values of the CTTRIGIN inputs. + +What: /sys/bus/coresight/devices/<cti-name>/regs/ittriginack +Date: March 2020 +KernelVersion 5.7 +Contact: coresight(a)lists.linaro.org +Description: (Write) Write the value of the CTTRIGINACK input. + +What: /sys/bus/coresight/devices/<cti-name>/regs/itchout +Date: March 2020 +KernelVersion 5.7 +Contact: coresight(a)lists.linaro.org +Description: (RW) Read or write the value of the CTCHOUT outputs. + +What: /sys/bus/coresight/devices/<cti-name>/regs/itchoutack +Date: March 2020 +KernelVersion 5.7 +Contact: coresight(a)lists.linaro.org +Description: (Read) Read the value of the CTCHOUTACK input. + +What: /sys/bus/coresight/devices/<cti-name>/regs/ittrigout +Date: March 2020 +KernelVersion 5.7 +Contact: coresight(a)lists.linaro.org +Description: (RW) Read or write the value of the CTTRIGOUT outputs. + +What: /sys/bus/coresight/devices/<cti-name>/regs/ittrigoutack +Date: March 2020 +KernelVersion 5.7 +Contact: coresight(a)lists.linaro.org +Description: (Read) Read the value of the CTTRIGOUTACK input. + What: /sys/bus/coresight/devices/<cti-name>/channels/trigin_attach Date: March 2020 KernelVersion: 5.7

3 months, 3 weeks

Re: [PATCH v7 02/13] coresight: etm4x: fix underflow for nrseqstate

by Suzuki K Poulose

On 19/05/2026 16:48, Yeoreum Yun wrote: > TCRSEQEVR<n> is implemented only when TCRIDR5.NUMSEQSTATE is 0b100, > in which case n ranges from 0 to 2; otherwise, TCRIDR5.NUMSEQSTATE is 0b000. > > Therefore, drvdata->nrseqstate should be checked before entering the loop. for (i = 0; i < drvdata->nrseqstate - 1; i++) Wouldn't that check cover the case ? (provided i is signed int ?) Suzuki > > Link: https://developer.arm.com/documentation/ihi0064/latest/ [0] > Fixes: 2e1cdfe184b5 ("coresight-etm4x: Adding CoreSight ETM4x driver") > Reviewed-by: Leo Yan <leo.yan(a)arm.com> > Signed-off-by: Yeoreum Yun <yeoreum.yun(a)arm.com> > --- > .../hwtracing/coresight/coresight-etm4x-core.c | 18 ++++++++++-------- > .../coresight/coresight-etm4x-sysfs.c | 2 ++ > 2 files changed, 12 insertions(+), 8 deletions(-) > > diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c > index 1e3b0344dc00..94b9385e964a 100644 > --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c > +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c > @@ -542,9 +542,11 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata) > etm4x_relaxed_write32(csa, config->vissctlr, TRCVISSCTLR); > if (drvdata->nr_pe_cmp) > etm4x_relaxed_write32(csa, config->vipcssctlr, TRCVIPCSSCTLR); > - for (i = 0; i < drvdata->nrseqstate - 1; i++) > - etm4x_relaxed_write32(csa, config->seq_ctrl[i], TRCSEQEVRn(i)); > + > if (drvdata->nrseqstate) { > + for (i = 0; i < drvdata->nrseqstate - 1; i++) > + etm4x_relaxed_write32(csa, config->seq_ctrl[i], TRCSEQEVRn(i)); > + > etm4x_relaxed_write32(csa, config->seq_rst, TRCSEQRSTEVR); > etm4x_relaxed_write32(csa, config->seq_state, TRCSEQSTR); > } > @@ -1896,10 +1898,10 @@ static int etm4_cpu_save(struct coresight_device *csdev) > if (drvdata->nr_pe_cmp) > state->trcvipcssctlr = etm4x_read32(csa, TRCVIPCSSCTLR); > > - for (i = 0; i < drvdata->nrseqstate - 1; i++) > - state->trcseqevr[i] = etm4x_read32(csa, TRCSEQEVRn(i)); > - > if (drvdata->nrseqstate) { > + for (i = 0; i < drvdata->nrseqstate - 1; i++) > + state->trcseqevr[i] = etm4x_read32(csa, TRCSEQEVRn(i)); > + > state->trcseqrstevr = etm4x_read32(csa, TRCSEQRSTEVR); > state->trcseqstr = etm4x_read32(csa, TRCSEQSTR); > } > @@ -2009,10 +2011,10 @@ static void etm4_cpu_restore(struct coresight_device *csdev) > if (drvdata->nr_pe_cmp) > etm4x_relaxed_write32(csa, state->trcvipcssctlr, TRCVIPCSSCTLR); > > - for (i = 0; i < drvdata->nrseqstate - 1; i++) > - etm4x_relaxed_write32(csa, state->trcseqevr[i], TRCSEQEVRn(i)); > - > if (drvdata->nrseqstate) { > + for (i = 0; i < drvdata->nrseqstate - 1; i++) > + etm4x_relaxed_write32(csa, state->trcseqevr[i], TRCSEQEVRn(i)); > + > etm4x_relaxed_write32(csa, state->trcseqrstevr, TRCSEQRSTEVR); > etm4x_relaxed_write32(csa, state->trcseqstr, TRCSEQSTR); > } > diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c > index e9eeea6240d5..0e1ad175aa1e 100644 > --- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c > +++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c > @@ -1395,6 +1395,8 @@ static ssize_t seq_idx_store(struct device *dev, > struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); > struct etmv4_config *config = &drvdata->config; > > + if (!drvdata->nrseqstate) > + return -ENOTSUPP; > if (kstrtoul(buf, 16, &val)) > return -EINVAL; > if (val >= drvdata->nrseqstate - 1)

3 months, 3 weeks

Re: [PATCH v7 02/13] coresight: etm4x: fix underflow for nrseqstate

by Suzuki K Poulose

On 19/05/2026 16:48, Yeoreum Yun wrote: > TCRSEQEVR<n> is implemented only when TCRIDR5.NUMSEQSTATE is 0b100, > in which case n ranges from 0 to 2; otherwise, TCRIDR5.NUMSEQSTATE is 0b000. > > Therefore, drvdata->nrseqstate should be checked before entering the loop. s/TCR/TRC/g ^^^ and every other patch in the series. Seem like you have been playing with the MMU code ;-) > > Link: https://developer.arm.com/documentation/ihi0064/latest/ [0] > Fixes: 2e1cdfe184b5 ("coresight-etm4x: Adding CoreSight ETM4x driver") > Reviewed-by: Leo Yan <leo.yan(a)arm.com> > Signed-off-by: Yeoreum Yun <yeoreum.yun(a)arm.com> > --- > .../hwtracing/coresight/coresight-etm4x-core.c | 18 ++++++++++-------- > .../coresight/coresight-etm4x-sysfs.c | 2 ++ > 2 files changed, 12 insertions(+), 8 deletions(-) > > diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c > index 1e3b0344dc00..94b9385e964a 100644 > --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c > +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c > @@ -542,9 +542,11 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata) > etm4x_relaxed_write32(csa, config->vissctlr, TRCVISSCTLR); > if (drvdata->nr_pe_cmp) > etm4x_relaxed_write32(csa, config->vipcssctlr, TRCVIPCSSCTLR); > - for (i = 0; i < drvdata->nrseqstate - 1; i++) > - etm4x_relaxed_write32(csa, config->seq_ctrl[i], TRCSEQEVRn(i)); > + > if (drvdata->nrseqstate) { > + for (i = 0; i < drvdata->nrseqstate - 1; i++) > + etm4x_relaxed_write32(csa, config->seq_ctrl[i], TRCSEQEVRn(i)); Looking at this again, I think we are contemplating two different values from a single variable (blame the architecture). Instead, we should: 1. Disconnect number of TRCSEQEVRn from drvdata->nrseqstate, and add nr_seq_ctrls to drvdata and initialise this at probe. for (i = 0; i < drvdata->nr_seq_ctrls; i++) Suzuki > + > etm4x_relaxed_write32(csa, config->seq_rst, TRCSEQRSTEVR); > etm4x_relaxed_write32(csa, config->seq_state, TRCSEQSTR); > } > @@ -1896,10 +1898,10 @@ static int etm4_cpu_save(struct coresight_device *csdev) > if (drvdata->nr_pe_cmp) > state->trcvipcssctlr = etm4x_read32(csa, TRCVIPCSSCTLR); > > - for (i = 0; i < drvdata->nrseqstate - 1; i++) > - state->trcseqevr[i] = etm4x_read32(csa, TRCSEQEVRn(i)); > - > if (drvdata->nrseqstate) { > + for (i = 0; i < drvdata->nrseqstate - 1; i++) > + state->trcseqevr[i] = etm4x_read32(csa, TRCSEQEVRn(i)); > + > state->trcseqrstevr = etm4x_read32(csa, TRCSEQRSTEVR); > state->trcseqstr = etm4x_read32(csa, TRCSEQSTR); > } > @@ -2009,10 +2011,10 @@ static void etm4_cpu_restore(struct coresight_device *csdev) > if (drvdata->nr_pe_cmp) > etm4x_relaxed_write32(csa, state->trcvipcssctlr, TRCVIPCSSCTLR); > > - for (i = 0; i < drvdata->nrseqstate - 1; i++) > - etm4x_relaxed_write32(csa, state->trcseqevr[i], TRCSEQEVRn(i)); > - > if (drvdata->nrseqstate) { > + for (i = 0; i < drvdata->nrseqstate - 1; i++) > + etm4x_relaxed_write32(csa, state->trcseqevr[i], TRCSEQEVRn(i)); > + > etm4x_relaxed_write32(csa, state->trcseqrstevr, TRCSEQRSTEVR); > etm4x_relaxed_write32(csa, state->trcseqstr, TRCSEQSTR); > } > diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c > index e9eeea6240d5..0e1ad175aa1e 100644 > --- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c > +++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c > @@ -1395,6 +1395,8 @@ static ssize_t seq_idx_store(struct device *dev, > struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); > struct etmv4_config *config = &drvdata->config; > > + if (!drvdata->nrseqstate) > + return -ENOTSUPP; > if (kstrtoul(buf, 16, &val)) > return -EINVAL; > if (val >= drvdata->nrseqstate - 1)

3 months, 3 weeks

Re: [PATCH v9 4/4] coresight: cti: expose banked sysfs registers for Qualcomm extended CTI

by Leo Yan

On Thu, May 21, 2026 at 08:16:30PM +0800, Yingchao Deng wrote: [...] > @@ -515,18 +543,36 @@ static struct attribute *coresight_cti_regs_attrs[] = { > &dev_attr_appclear.attr, > &dev_attr_apppulse.attr, > coresight_cti_reg(triginstatus, CTITRIGINSTATUS), > + coresight_cti_reg_index(triginstatus1, CTITRIGINSTATUS, 1), > + coresight_cti_reg_index(triginstatus2, CTITRIGINSTATUS, 2), > + coresight_cti_reg_index(triginstatus3, CTITRIGINSTATUS, 3), For this patch: Reviewed-by: Leo Yan <leo.yan(a)arm.com> AI tool reminds to update Documentation/ABI/testing/sysfs-bus-coresight-devices-cti, you might need to add description with a new patch: What: /sys/bus/coresight/devices/<cti-name>/regs/trigoutstatus[1-3] Date: May 2026 KernelVersion: 7.2 Contact: coresight(a)lists.linaro.org Description: (Read) read current status of QCOM extended output trigger signals. And please add document for other new sysfs knobs. Thanks, Leo

3 months, 4 weeks

[PATCH 0/2] perf cs-etm: Queue context packets for frontend

by James Clark

Fix thread tracking when decoding Coresight trace and add a new test for it. Unfortunately the test has to be added as a separate binary like the other existing Coresight workloads which needs a bit of makefile boilerplate. Ideally it would be a builtin Perf test workload, but Perf has a lot of dependencies and generates a lot of trace when starting up which makes tracing tests very slow because all that has to be decoded. Hopefully I can find a generic way to enable Perf events at the beginning of the workload and then I can migrate everything from tools/perf/tests/shell/coresight to Perf test workloads, but that will have to be done as a separate change. Signed-off-by: James Clark <james.clark(a)linaro.org> --- James Clark (1): perf test cs-etm: Test thread attribution Leo Yan (1): perf cs-etm: Queue context packets for frontend tools/perf/tests/shell/coresight/Makefile | 1 + .../shell/coresight/context_switch_loop/.gitignore | 1 + .../shell/coresight/context_switch_loop/Makefile | 29 ++++ .../context_switch_loop/context_switch_loop.c | 83 ++++++++++ .../tests/shell/coresight/context_switch_thread.sh | 48 ++++++ tools/perf/util/cs-etm-decoder/cs-etm-decoder.c | 18 +- tools/perf/util/cs-etm.c | 181 +++++++++++++-------- tools/perf/util/cs-etm.h | 5 +- 8 files changed, 295 insertions(+), 71 deletions(-) --- base-commit: 09d355618f7ccc27ffc7fc668b2e232872962079 change-id: 20260515-james-cs-context-tracking-fix-754998bae7ed Best regards, -- James Clark <james.clark(a)linaro.org>

3 months, 4 weeks

Re: [PATCH v9 2/4] coresight: cti: use __reg_addr() helper for register access

by Leo Yan

On Thu, May 21, 2026 at 08:16:28PM +0800, Yingchao Deng wrote: [...] > +static void __iomem *__reg_addr(struct cti_drvdata *drvdata, u32 off, > + u32 index) > +{ > + return drvdata->base + off + sizeof(u32) * index; > +} > + > +#define reg_addr(drvdata, off) __reg_addr((drvdata), (off), 0) > +#define reg_index_addr(drvdata, off, i) __reg_addr((drvdata), (off), (i)) > -u32 cti_read_single_reg(struct cti_drvdata *drvdata, int offset) > +u32 cti_read_single_reg(struct cti_drvdata *drvdata, u32 off, u32 index) > { > - int val; > + u32 val; > > CS_UNLOCK(drvdata->base); > - val = readl_relaxed(drvdata->base + offset); > + val = readl_relaxed(reg_index_addr(drvdata, off, index)); > CS_LOCK(drvdata->base); > > return val; > } > > -void cti_write_single_reg(struct cti_drvdata *drvdata, int offset, u32 value) > +void cti_write_single_reg(struct cti_drvdata *drvdata, u32 off, u32 index, > + u32 value) > { > CS_UNLOCK(drvdata->base); > - writel_relaxed(value, drvdata->base + offset); > + writel_relaxed(value, reg_index_addr(drvdata, off, index)); > CS_LOCK(drvdata->base); > } I prefer to move the register helpers into coresight-cti.h and add two additional helpers: cti_read_single_reg_index() and cti_write_single_reg_index(). I also found circular dependency between coresight-cti.h and qcom-cti.h. Since qcom-cti.h only contains register definitions and a small inline function for register conversion, we can simply fold it into coresight-cti.h and dismiss the circular dependency. Based on this idea, I played around with the code a bit (see the snippet below). Would you be okay with applying this approach to patches 02/03? If have any questions, please let me know. ---8<--- --- a/drivers/hwtracing/coresight/coresight-cti.h +++ b/drivers/hwtracing/coresight/coresight-cti.h @@ -60,6 +60,31 @@ struct fwnode_handle; */ #define CTIINOUTEN_MAX 128 +/* QCOM CTI extension */ +#define QCOM_ARCHITECT 0x477 + +#define QCOM_CTIINTACK 0x020 +#define QCOM_CTIAPPSET 0x004 +#define QCOM_CTIAPPCLEAR 0x008 +#define QCOM_CTIAPPPULSE 0x00C +#define QCOM_CTIINEN 0x400 +#define QCOM_CTIOUTEN 0x800 +#define QCOM_CTITRIGINSTATUS 0x040 +#define QCOM_CTITRIGOUTSTATUS 0x060 +#define QCOM_CTICHINSTATUS 0x080 +#define QCOM_CTICHOUTSTATUS 0x084 +#define QCOM_CTIGATE 0x088 +#define QCOM_ASICCTL 0x08C +/* Integration test registers */ +#define QCOM_ITCHINACK 0xE70 +#define QCOM_ITTRIGINACK 0xE80 +#define QCOM_ITCHOUT 0xE74 +#define QCOM_ITTRIGOUT 0xEA0 +#define QCOM_ITCHOUTACK 0xE78 +#define QCOM_ITTRIGOUTACK 0xEC0 +#define QCOM_ITCHIN 0xE7C +#define QCOM_ITTRIGIN 0xEE0 + /** * Group of related trigger signals * @@ -222,9 +247,8 @@ int cti_enable(struct coresight_device *csdev, enum cs_mode mode, int cti_disable(struct coresight_device *csdev, struct coresight_path *path); void cti_write_all_hw_regs(struct cti_drvdata *drvdata); void cti_write_intack(struct device *dev, u32 ackval); -void cti_write_single_reg(struct cti_drvdata *drvdata, u32 off, u32 index, - u32 value); -u32 cti_read_single_reg(struct cti_drvdata *drvdata, u32 off, u32 index); int cti_channel_trig_op(struct device *dev, enum cti_chan_op op, enum cti_trig_dir direction, u32 channel_idx, u32 trigger_idx); @@ -237,6 +261,78 @@ struct coresight_platform_data * coresight_cti_get_platform_data(struct device *dev); const char *cti_plat_get_node_name(struct fwnode_handle *fwnode); +static inline u32 cti_qcom_reg_off(u32 offset) +{ + switch (offset) { + case CTIINTACK: return QCOM_CTIINTACK; + case CTIAPPSET: return QCOM_CTIAPPSET; + case CTIAPPCLEAR: return QCOM_CTIAPPCLEAR; + case CTIAPPPULSE: return QCOM_CTIAPPPULSE; + case CTIINEN: return QCOM_CTIINEN; + case CTIOUTEN: return QCOM_CTIOUTEN; + case CTITRIGINSTATUS: return QCOM_CTITRIGINSTATUS; + case CTITRIGOUTSTATUS: return QCOM_CTITRIGOUTSTATUS; + case CTICHINSTATUS: return QCOM_CTICHINSTATUS; + case CTICHOUTSTATUS: return QCOM_CTICHOUTSTATUS; + case CTIGATE: return QCOM_CTIGATE; + case ASICCTL: return QCOM_ASICCTL; + case ITCHINACK: return QCOM_ITCHINACK; + case ITTRIGINACK: return QCOM_ITTRIGINACK; + case ITCHOUT: return QCOM_ITCHOUT; + case ITTRIGOUT: return QCOM_ITTRIGOUT; + case ITCHOUTACK: return QCOM_ITCHOUTACK; + case ITTRIGOUTACK: return QCOM_ITTRIGOUTACK; + case ITCHIN: return QCOM_ITCHIN; + case ITTRIGIN: return QCOM_ITTRIGIN; + + default: + return offset; + } +} + +static inline void __iomem *__reg_addr(struct cti_drvdata *drvdata, + u32 off, u32 index) +{ + if (unlikely(drvdata->is_qcom_cti)) + off = cti_qcom_reg_off(off); + + return drvdata->base + off + index * sizeof(u32); +} + +#define reg_addr(drvdata, off) __reg_addr((drvdata), (off), 0) +#define reg_index_addr(drvdata, off, i) __reg_addr((drvdata), (off), (i)) + +static inline u32 cti_read_single_reg_index(struct cti_drvdata *drvdata, + u32 off, u32 index) +{ + u32 val; + + CS_UNLOCK(drvdata->base); + val = readl_relaxed(reg_index_addr(drvdata, off, index)); + CS_LOCK(drvdata->base); + + return val; +} + +static inline u32 cti_read_single_reg(struct cti_drvdata *drvdata, u32 off) +{ + return cti_read_single_reg_index(drvdata, off, 0); +} + +static inline void cti_write_single_reg_index(struct cti_drvdata *drvdata, + u32 off, u32 index, u32 value) +{ + CS_UNLOCK(drvdata->base); + writel_relaxed(value, reg_index_addr(drvdata, off, index)); + CS_LOCK(drvdata->base); +} + +static inline void cti_write_single_reg(struct cti_drvdata *drvdata, + u32 off, u32 value) +{ + cti_write_single_reg_index(drvdata, off, 0, value); +} + /* Check if a cti device is enabled */ static inline bool cti_is_active(struct cti_config *cfg) {

3 months, 4 weeks

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