CoreSight October 2026

coresight@lists.linaro.org

6 participants
30 discussions

[PATCH v3 0/4] perf: cs-etm: HW_ID improvements

by James Clark

The driver might not always be able to write HW_IDs, but we don't need them for unformatted mode anyway, so fix that in commit ("perf cs-etm: Synthesize missing HW_ID mappings for raw trace"). Include some other minor improvements encountered on the way to appease Sashiko, like properly freeing queues and ("perf: cs-etm: Respect --no-itrace option") makes debugging broken Coresight perf.data files easier. Signed-off-by: James Clark <james.clark(a)linaro.org> --- Changes in v3: - Remove old b4 prerequisite metadata that's no longer relevant. - Link to v2: https://patch.msgid.link/20261002-james-cs-hw_id-output-failure-v2-0-7a194a… Changes in v2: - Drop driver changes and move to https://lore.kernel.org/linux-perf-users/20261001-james-cs-retry-hw_id-v1-0… - Don't process any HW_IDs for unformatted queues, just create decoders unconditionally with trace ID 1. - Use zfree() instead of etmq->decoder = NULL - Remove dependency on "[PATCH v2 00/14] perf cs-etm: Per-thread mode fixes and snapshot wrap support", it wasn't functionally dependant, just touching some of the same lines. - Link to v1: https://patch.msgid.link/20260821-james-cs-hw_id-output-failure-v1-0-9d532d… --- James Clark (3): perf: cs-etm: Don't add global v0 HW_IDs to unformatted queues perf cs-etm: Free partially created queues perf: cs-etm: Respect --no-itrace option Leo Yan (1): perf cs-etm: Synthesize missing HW_ID mappings for raw trace tools/perf/util/auxtrace.c | 2 +- tools/perf/util/auxtrace.h | 1 + tools/perf/util/cs-etm-decoder/cs-etm-decoder.c | 12 +- tools/perf/util/cs-etm-decoder/cs-etm-decoder.h | 2 +- tools/perf/util/cs-etm.c | 184 +++++++++++++++--------- 5 files changed, 123 insertions(+), 78 deletions(-) --- base-commit: 705da5b15ab89ba97b11eedbe507c2fd83d31cb9 change-id: 20260706-james-cs-hw_id-output-failure-1d06d042ef96 Best regards, -- James Clark <james.clark(a)linaro.org>

18 hours, 12 minutes

[PATCH] coresight: etm4x: Fix event count decoding

by Leo Yan

TRCIDR0.NUMEVENT normally encodes the number of events minus one. From ETMv4.3 onwards, including ETE, a zero TRCIDR4.NUMRSPAIR instead means that no events are implemented and NUMEVENT is zero. The sysfs event controls currently interpret this combination as one event and allow writes to unsupported event fields. Decode NUMEVENT after NUMRSPAIR and store the actual number of events in nr_event. Use the decoded resource count so that older ETM versions, where a zero NUMRSPAIR represents one resource pair, still report at least one event. Update both sysfs event controls to use the actual count and clear their event fields when no events are implemented. Also correct the instruction event enable mask for the single-event case to use INSTEN[0]. The existing mask uses INSTEN[1], preventing event 0 from being enabled. This change depends on the recent driver refactoring. With no reported failures, it is not intended for stable backporting. Signed-off-by: Leo Yan <leo.yan(a)arm.com> --- drivers/hwtracing/coresight/coresight-etm4x-core.c | 15 +++++++++-- .../hwtracing/coresight/coresight-etm4x-sysfs.c | 29 ++++++++++++---------- 2 files changed, 29 insertions(+), 15 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c index e21be6468e9544fe6e22f524de4fef9f89d7484f..b0e286f487017a4155595f14cbb9c9c33b17dc6b 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c @@ -1451,8 +1451,6 @@ static void etm4_init_arch_data(void *info) caps->trccci = !!(etmidr0 & TRCIDR0_TRCCCI); /* RETSTACK, bit[9] Return stack bit */ caps->retstack = !!(etmidr0 & TRCIDR0_RETSTACK); - /* NUMEVENT, bits[11:10] Number of events field */ - caps->nr_event = FIELD_GET(TRCIDR0_NUMEVENT_MASK, etmidr0); /* QSUPP, bits[16:15] Q element support field */ caps->q_support = FIELD_GET(TRCIDR0_QSUPP_MASK, etmidr0); if (caps->q_support) @@ -1519,6 +1517,19 @@ static void etm4_init_arch_data(void *info) caps->nr_resource = FIELD_GET(TRCIDR4_NUMRSPAIR_MASK, etmidr4); if ((drvdata->arch < ETM_ARCH_V4_3) || (caps->nr_resource > 0)) caps->nr_resource += 1; + + /* + * See ARM IHI0064H.b, sections 7.3.32 (TRCIDR0) and 7.3.36 (TRCIDR4). + * + * Before ETMv4.3, one event is always implemented. For ETM v4.3 and + * later, NUMRSPAIR == 0 indicates that no events are implemented. + * Otherwise, NUMEVENT encodes the number of events minus one. + */ + if (caps->nr_resource) + caps->nr_event = FIELD_GET(TRCIDR0_NUMEVENT_MASK, etmidr0) + 1; + else + caps->nr_event = 0; + /* * NUMSSCC, bits[23:20] the number of single-shot * comparator control for tracing. Read any status regs as these diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c index db9e603f97ba82cd608d3d61881fe8153db020ff..fb38f0102290a53a681934c827abf107c141a740 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c @@ -513,19 +513,22 @@ static ssize_t event_store(struct device *dev, raw_spin_lock(&drvdata->spinlock); switch (caps->nr_event) { - case 0x0: + case 0: + sysfs_config->eventctrl0 = 0; + break; + case 1: /* EVENT0, bits[7:0] */ sysfs_config->eventctrl0 = val & 0xFF; break; - case 0x1: - /* EVENT1, bits[15:8] */ + case 2: + /* EVENT1, bits[15:8] */ sysfs_config->eventctrl0 = val & 0xFFFF; break; - case 0x2: + case 3: /* EVENT2, bits[23:16] */ sysfs_config->eventctrl0 = val & 0xFFFFFF; break; - case 0x3: + case 4: /* EVENT3, bits[31:24] */ sysfs_config->eventctrl0 = val; break; @@ -565,22 +568,22 @@ static ssize_t event_instren_store(struct device *dev, /* start by clearing all instruction event enable bits */ sysfs_config->eventctrl1 &= ~TRCEVENTCTL1R_INSTEN_MASK; switch (caps->nr_event) { - case 0x0: - /* generate Event element for event 1 */ - sysfs_config->eventctrl1 |= val & TRCEVENTCTL1R_INSTEN_1; + case 1: + /* generate Event element for event 0 */ + sysfs_config->eventctrl1 |= val & TRCEVENTCTL1R_INSTEN_0; break; - case 0x1: - /* generate Event element for event 1 and 2 */ + case 2: + /* generate Event element for events 0 and 1 */ sysfs_config->eventctrl1 |= val & (TRCEVENTCTL1R_INSTEN_0 | TRCEVENTCTL1R_INSTEN_1); break; - case 0x2: - /* generate Event element for event 1, 2 and 3 */ + case 3: + /* generate Event element for events 0, 1 and 2 */ sysfs_config->eventctrl1 |= val & (TRCEVENTCTL1R_INSTEN_0 | TRCEVENTCTL1R_INSTEN_1 | TRCEVENTCTL1R_INSTEN_2); break; - case 0x3: + case 4: /* generate Event element for all 4 events */ sysfs_config->eventctrl1 |= val & (TRCEVENTCTL1R_INSTEN_0 | TRCEVENTCTL1R_INSTEN_1 | --- base-commit: 343cfcbb3ecfdb80aa576a428cfa3b65ad783842 change-id: 20261022-arm_cs_fix_etm4_event_count-49f384a2f6a7 Best regards, -- Leo Yan <leo.yan(a)arm.com>

18 hours, 29 minutes

Re: [PATCH v2 3/4] coresight: etm4x: Report the external outputs the PMU counts

by Leo Yan

On Mon, Oct 12, 2026 at 04:05:22PM -0700, Amir Ayupov wrote: [...] > --- a/drivers/hwtracing/coresight/coresight-config.h > +++ b/drivers/hwtracing/coresight/coresight-config.h > @@ -35,6 +35,10 @@ > * a device that matches one of its classes and has all of its capabilities. > */ > #define CS_CFG_MATCH_CAP_MASK 0x0000ff00 > +/* trace unit external output n is countable by the PMU as TRCEXTOUTn */ > +#define CS_CFG_MATCH_CAP_PMU_EXTOUT_SHIFT 8 > +#define CS_CFG_MATCH_CAP_PMU_EXTOUT_NR 4 /* TRCEXTOUT0-3 */ > +#define CS_CFG_MATCH_CAP_PMU_EXTOUT(n) BIT(CS_CFG_MATCH_CAP_PMU_EXTOUT_SHIFT + (n)) We can just use a single capacity for all output singals. It would be good to follow the naming convention in the Arm ARM: #define CS_CFG_MATCH_CAP_TRCEXTOUT BIT(8) > int etm4_cscfg_register(struct coresight_device *csdev) > { > + struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); > struct cscfg_csdev_feat_ops ops; > + u32 match_flags = CS_CFG_ETM4_MATCH_FLAGS; > > ops.load_feat = &etm4_cfg_load_feature; > + match_flags |= (u32)drvdata->pmu_extout << CS_CFG_MATCH_CAP_PMU_EXTOUT_SHIFT; > > - return cscfg_register_csdev(csdev, CS_CFG_ETM4_MATCH_FLAGS, &ops); > + return cscfg_register_csdev(csdev, match_flags, &ops); I would suggest to enable the capability bit base on drvdata->caps: if (etm4x_is_ete(drvdata) && drvdata->caps.nr_events) match_flags |= CS_CFG_MATCH_CAP_TRCEXTOUT; For now, we can enable TRCEXTOUT for ETE only, as this should be sufficient to detect the feature safely. I'd like to leave this to James and Mike as I got suggestions from them. Please also rebase onto the latest CoreSight next branch [1], which moves the capability fields into drvdata->caps. I found an issue in the decoding of caps.nr_event; the attached patch fixes it and makes the field hold the actual event count. [1] https://git.kernel.org/pub/scm/linux/kernel/git/coresight/linux.git branch: next ---8<--- From 95307fa0574b1e0b3922ffa23fe98144b2688496 Mon Sep 17 00:00:00 2001 From: Leo Yan <leo.yan(a)arm.com> Date: Wed, 21 Oct 2026 17:05:18 +0100 Subject: [PATCH] coresight: etm4x: Fix event count decoding TRCIDR0.NUMEVENT normally encodes the number of events minus one. From ETMv4.3 onwards, including ETE, a zero TRCIDR4.NUMRSPAIR instead means that no events are implemented and NUMEVENT is zero. The sysfs event controls currently interpret this combination as one event and allow writes to unsupported event fields. Decode NUMEVENT after NUMRSPAIR and store the actual number of events in nr_event. Use the decoded resource count so that older ETM versions, where a zero NUMRSPAIR represents one resource pair, still report at least one event. Update both sysfs event controls to use the actual count and clear their event fields when no events are implemented. Also correct the instruction event enable mask for the single-event case to use INSTEN[0]. The existing mask uses INSTEN[1], preventing event 0 from being enabled. This change depends on the recent driver refactoring. With no reported failures, it is not intended for stable backporting. Signed-off-by: Leo Yan <leo.yan(a)arm.com> --- .../coresight/coresight-etm4x-core.c | 13 +++++++-- .../coresight/coresight-etm4x-sysfs.c | 29 ++++++++++--------- 2 files changed, 27 insertions(+), 15 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c index e21be6468e954..af017bd8a5477 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c @@ -1451,8 +1451,6 @@ static void etm4_init_arch_data(void *info) caps->trccci = !!(etmidr0 & TRCIDR0_TRCCCI); /* RETSTACK, bit[9] Return stack bit */ caps->retstack = !!(etmidr0 & TRCIDR0_RETSTACK); - /* NUMEVENT, bits[11:10] Number of events field */ - caps->nr_event = FIELD_GET(TRCIDR0_NUMEVENT_MASK, etmidr0); /* QSUPP, bits[16:15] Q element support field */ caps->q_support = FIELD_GET(TRCIDR0_QSUPP_MASK, etmidr0); if (caps->q_support) @@ -1519,6 +1517,17 @@ static void etm4_init_arch_data(void *info) caps->nr_resource = FIELD_GET(TRCIDR4_NUMRSPAIR_MASK, etmidr4); if ((drvdata->arch < ETM_ARCH_V4_3) || (caps->nr_resource > 0)) caps->nr_resource += 1; + + /* + * NUMEVENT encodes the number of events minus one. From ETMv4.3, + * including ETE, NUMRSPAIR == 0 means no events are implemented. + * nr_resource already accounts for the pre-ETMv4.3 encoding. + */ + if (caps->nr_resource) + caps->nr_event = FIELD_GET(TRCIDR0_NUMEVENT_MASK, etmidr0) + 1; + else + caps->nr_event = 0; + /* * NUMSSCC, bits[23:20] the number of single-shot * comparator control for tracing. Read any status regs as these diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c index db9e603f97ba8..fb38f0102290a 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c @@ -513,19 +513,22 @@ static ssize_t event_store(struct device *dev, raw_spin_lock(&drvdata->spinlock); switch (caps->nr_event) { - case 0x0: + case 0: + sysfs_config->eventctrl0 = 0; + break; + case 1: /* EVENT0, bits[7:0] */ sysfs_config->eventctrl0 = val & 0xFF; break; - case 0x1: - /* EVENT1, bits[15:8] */ + case 2: + /* EVENT1, bits[15:8] */ sysfs_config->eventctrl0 = val & 0xFFFF; break; - case 0x2: + case 3: /* EVENT2, bits[23:16] */ sysfs_config->eventctrl0 = val & 0xFFFFFF; break; - case 0x3: + case 4: /* EVENT3, bits[31:24] */ sysfs_config->eventctrl0 = val; break; @@ -565,22 +568,22 @@ static ssize_t event_instren_store(struct device *dev, /* start by clearing all instruction event enable bits */ sysfs_config->eventctrl1 &= ~TRCEVENTCTL1R_INSTEN_MASK; switch (caps->nr_event) { - case 0x0: - /* generate Event element for event 1 */ - sysfs_config->eventctrl1 |= val & TRCEVENTCTL1R_INSTEN_1; + case 1: + /* generate Event element for event 0 */ + sysfs_config->eventctrl1 |= val & TRCEVENTCTL1R_INSTEN_0; break; - case 0x1: - /* generate Event element for event 1 and 2 */ + case 2: + /* generate Event element for events 0 and 1 */ sysfs_config->eventctrl1 |= val & (TRCEVENTCTL1R_INSTEN_0 | TRCEVENTCTL1R_INSTEN_1); break; - case 0x2: - /* generate Event element for event 1, 2 and 3 */ + case 3: + /* generate Event element for events 0, 1 and 2 */ sysfs_config->eventctrl1 |= val & (TRCEVENTCTL1R_INSTEN_0 | TRCEVENTCTL1R_INSTEN_1 | TRCEVENTCTL1R_INSTEN_2); break; - case 0x3: + case 4: /* generate Event element for all 4 events */ sysfs_config->eventctrl1 |= val & (TRCEVENTCTL1R_INSTEN_0 | TRCEVENTCTL1R_INSTEN_1 | -- 2.34.1

1 day, 9 hours

Re: [PATCH v2 2/4] coresight: syscfg: Match feature capabilities separately from device class

by Leo Yan

On Mon, Oct 12, 2026 at 04:05:21PM -0700, Amir Ayupov wrote: [...] > --- a/drivers/hwtracing/coresight/coresight-config.h > +++ b/drivers/hwtracing/coresight/coresight-config.h > @@ -30,6 +30,12 @@ > #define CS_CFG_MATCH_CLASS_SRC_ALL 0x0001 /* match any source */ > #define CS_CFG_MATCH_CLASS_SRC_ETM4 0x0002 /* match any ETMv4 device */ It is good to introduce a marco: #define CS_CFG_MATCH_CLASS_MASK GENMASK_U32(7, 0) > +/* > + * flags defining device capabilities a feature can require. A feature loads on > + * a device that matches one of its classes and has all of its capabilities. > + */ > +#define CS_CFG_MATCH_CAP_MASK 0x0000ff00 To make the mask explicitly 32-bit unsigned: #define CS_CFG_MATCH_CAP_MASK GENMASK_U32(15, 8) > + > /* flags defining device instance matching - used in config match desc data. */ > #define CS_CFG_MATCH_INST_ANY 0x80000000 /* any instance of a class */ Not an issue with this patch, but CS_CFG_MATCH_INST_ANY appears to be unused and could be removed in a separate cleanup patch. > diff --git a/drivers/hwtracing/coresight/coresight-syscfg.c b/drivers/hwtracing/coresight/coresight-syscfg.c > index a816c22c87bc8..1545d64afec01 100644 > --- a/drivers/hwtracing/coresight/coresight-syscfg.c > +++ b/drivers/hwtracing/coresight/coresight-syscfg.c > @@ -172,7 +172,21 @@ cscfg_alloc_csdev_feat(struct coresight_device *csdev, struct cscfg_feature_desc > } > > /* load one feature into one coresight device */ > +/* > + * A feature matches a device that shares one of its class flags and has all of > + * the capability flags it requires. > + */ > +static bool cscfg_match_feat_csdev(u32 feat_flags, u32 csdev_flags) > +{ > + u32 caps = feat_flags & CS_CFG_MATCH_CAP_MASK; > + > + return (feat_flags & csdev_flags & ~CS_CFG_MATCH_CAP_MASK) && > + (csdev_flags & caps) == caps; For clearer comparison conditions: /* Class type must be matches */ if ((feat_flags & CS_CFG_MATCH_CLASS_MASK) != (csdev_flags & CS_CFG_MATCH_CLASS_MASK) return false; /* No required capabilities miss from the device */ if (feat_flags & ~csdev_flags & CS_CFG_MATCH_CAP_MASK) return false; return true; Thanks, Leo

1 day, 12 hours

Re: [PATCH v2 1/4] coresight: syscfg: Fail to enable a configuration not loaded on the device

by Leo Yan

On Mon, Oct 12, 2026 at 04:05:20PM -0700, Amir Ayupov wrote: > cscfg_csdev_enable_active_config() looks up the selected configuration in > the device's loaded configurations, and returns success when it is not > there. A configuration is only loaded on devices that match at least one > of its features, so a perf session or sysfs enable that selects it on any > other device runs without the configuration, with no error. > > Return -EINVAL instead, so enabling the source fails on that device. The > function is only called with a non-zero configuration hash, so sources > enabled without a configuration are unaffected. > > Fixes: f8cce2ff3c04 ("coresight: syscfg: Add API to activate and enable configurations") > Assisted-by: Devmate:Opus-5.5 > Signed-off-by: Amir Ayupov <aaupov(a)fb.com> Reviewed-by: Leo Yan <leo.yan(a)arm.com>

1 day, 12 hours

[PATCH v2 00/14] perf cs-etm: Per-thread mode fixes and snapshot wrap support

by James Clark

Fix a few issues with per-thread mode: - With TRBE, thread migrations hit a queue without a decoder assert - On nVHE, everything looks like guest trace instead of host - Tracing multiple threads didn't really work After adding a tests for those, it turns out there were some snapshot bugs not picked up by the other snapshot tests. That showed that the different snapshot searches for Intel BTS and Arm SPE were inconsistent and I think all tracers can benefit from using the same pointer fixup logic, so that gets refactored into the common auxtrace.c. Then SPE can just share the Intel BTS search as it was obviously copied from it originally. IntelPT keeps the more advanced duplicate data search, but in the future that could probably be made the common one and all tracers would benefit from using it (except maybe BTS if it always has a very small buffer, but I doubt the overhead of the duplicate search would be an issue). For now this is more of a refactor rather than behavioral change so don't do that yet. Signed-off-by: James Clark <james.clark(a)linaro.org> --- Changes in v2: - Remove stale "may be reset to -1 in per-thread mode" comment - Set CPU when queueing auxtrace fragments otherwise auxtrace_queues__add_event() overwrites the queue's CPU - Link to v1: https://patch.msgid.link/20260811-james-cs-unformatted-per-thread-fix-v1-0-… --- James Clark (14): perf cs-etm: Fix nVHE per-thread decoding perf cs-etm: Warn for invalid timestamp option perf cs-etm: Turn on context packet timestamps in per-thread mode perf cs-etm: Use per-CPU queues for per-thread mode perf cs-etm: Increase default timestamp generation period perf auxtrace: Turn Intel BTS snapshot search into a generic one perf arm-spe: Use generic snapshot search perf auxtrace: intel-pt: Use new snapshot_has_wrapped callback perf cs-etm: Queue partial AUX records perf cs-etm: Don't print missing buffers in snapshot mode perf auxtrace: cs-etm: Capture wrapped snapshots perf test: Allow infinite named_thread loops perf test: Add test for per-thread mode perf cs-etm: Test multiple per-thread threads Documentation/userspace-api/perf_ring_buffer.rst | 6 +- tools/perf/Documentation/perf-test.txt | 2 +- tools/perf/arch/arm/util/cs-etm.c | 30 ++++- tools/perf/arch/arm64/util/arm-spe.c | 147 +-------------------- tools/perf/arch/x86/util/intel-bts.c | 115 +--------------- tools/perf/arch/x86/util/intel-pt.c | 58 +++----- .../perf/tests/shell/coresight/per-thread-multi.sh | 78 +++++++++++ tools/perf/tests/shell/coresight/per-thread.sh | 48 +++++++ .../perf/tests/shell/coresight/raw_dump_stress.sh | 5 - tools/perf/tests/workloads/named_threads.c | 7 +- tools/perf/util/auxtrace.c | 136 +++++++++++++++++-- tools/perf/util/auxtrace.h | 20 ++- tools/perf/util/cs-etm.c | 101 ++++++++++---- 13 files changed, 384 insertions(+), 369 deletions(-) --- base-commit: 9453bc6a69ef43755f1c28d5688cacdd69fa16bd change-id: 20260605-james-cs-unformatted-per-thread-fix-50e723aa7f0e Best regards, -- James Clark <james.clark(a)linaro.org>

1 day, 17 hours

Re: [PATCH 2/2] perf: arm_spe: Prefer large AUX mappings

by Leo Yan

On Thu, Oct 08, 2026 at 04:13:27PM +0530, Dev Jain wrote: > > >>> Commit 18049c8cff9c ("perf/aux: Allocate non-contiguous AUX pages by > >>> default") made the AUX allocator use order-0 pages by default unless a > >>> PMU explicitly asks for contiguous allocations. > >> > >> But that commit specifically calls out SPE as benefitting from > >> non-contiguous pages: > >> > >> "For instance, ARM SPE and TRBE operate with virtual pages, and > >> Coresight ETR allocates a separate buffer. For these PMUs, > >> allocating contiguous AUX pages unnecessarily exacerbates memory > >> fragmentation. This fragmentation can prevent their use on > >> long-running devices." > >> > >> so why doesn't passing PERF_PMU_CAP_AUX_PREFER_LARGE reintroduce the > >> problems that 18049c8cff9c was trying to solve? > I don't have the full context here (can look in detail later) so drive-by comment: > > In general, doing large order allocations should *reduce* fragmentation. If you allocate > 16 order-0 pages as opposed to an order-4 compound page, you may end up spreading your > allocations across different blocks, thus preventing them from merging later. > > A recent example can be found in vmalloc [1]. > > [1] https://lore.kernel.org/all/aPjrRkjiIt6HmXmT@casper.infradead.org/ Thanks, Dev. Roughly read the shared link, larger allocations can keep pages with the same lifetime together, so order-0 allocation is not necessarily better for fragmentation. As mentioned in my other reply, the AUX buffer allocator already used __GFP_NORETRY before the commit 18049c8cff9c, so those allocations do not directly invoke the kernel OOM killer. This calls for revisiting that rationale in 18049c8cff9c. The original issue does not appear to have been investigated sufficiently, and we still haven't received further details since this series. I propose reverting 18049c8cff9c to restore the previous allocation policy. If no objections, I will send a revert for review. Thanks, Leo

2 days, 10 hours

[PATCH 00/25] CoreSight / perf: Support AUX sampling

by Leo Yan

This series adds AUX sampling support to Arm CoreSight. A PMU sample can carry a window of recent AUX trace, which perf generates callchain and branch stack for the sampled thread. This provides execution history for context-based profiling. The series can be divided into four parts: 1. Patches 01 ~ 03 for event core: The perf event core changes warn on non-positive AUX snapshot returns before checking alignment padding. Space for a non-zero AUX payload has already been reserved, so a zero return leaves that payload unwritten. CoreSight fills unavailable trace with zeros and returns the requested size. It also prevents AUX sampling and pause/resume from nesting through an NMI. A driver guard alone can leave perf's pause state (aux_paused) inconsistent with the hardware state. The event core ensures only one AUX callback is exclusively invoked. Export the output copy helpers so CoreSight can fill sample payloads when the driver is built as a module. 2. Patches 04 ~ 09 for ETM perf: The ETM perf changes separate the lifetime of the published CoreSight context from that of the AUX output handle. Centralize buffer updates, and end AUX output when throttling stops an event without PERF_EF_UPDATE so a later restart can acquire a fresh handle. Make hardware-state transitions reflect completed operations. 3. Patches 10 ~ 13 for TRBE driver: TRBE snapshot buffers need padding to meet the CPU's alignment and wrap constraints. Use circular buffer mode for overwrite snapshots, retaining Fill mode on CPUs that require the write out-of-range workaround. TRBE faults can still raise interrupts in circular mode. Track when the sink is handling an interrupt so an AUX sampling NMI can skip a snapshot while the interrupted handler is updating the buffer. Make repeated sink disable safe for deferred cleanup after a snapshot failure. 4. Patches 14 ~ 25 for AUX sampling and decoding: Shared atomic STOP and AUX action bits prevent an NMI stop from tearing down the context while pause, resume or snapshot accesses it. The AUX operation finishes and then completes the deferred stop, publishing the stopped state only after hardware teardown. Add snapshot_aux() to the CoreSight driver to pause the source, update the sink buffer, disable the path, copy the recent trace into the PMU sample, and then re-enable the path and resume the source. Patch 17 fixes history collection for zero-IP PMU samples. Perf clears the IP when a user-only sampling interrupt skids into the kernel, but the timestamp and TID remain valid for matching the trace history. In perf, decode each embedded payload as an independent trace window, selecting the decoder with the sampled CPU and using the sample's PID/TID and traced context IDs to attribute history to the sampled thread. Refactor common timeless decoding and history collection, and drain pending OpenCSD output so buffered history is not lost. Attach reconstructed callchains and branch stacks to the original PMU samples, preserving histories already present in the samples. Add a test, and document the recording and decoding workflow and its limitations. The initial support targets unformatted trace from per-CPU sinks such as TRBE. Shared formatted sinks such as ETR can mix trace from multiple CPUs, consuming the limited sample window with execution unrelated to the sampled thread. This series is based on Amir's series "perf: Add CoreSight branch history to existing samples" [1] for perf tool's branch / callchain generating. [1] https://lore.kernel.org/linux-perf-users/cover.1787005265.git.aaupov@fb.com/ Signed-off-by: Leo Yan <leo.yan(a)arm.com> --- Leo Yan (25): perf/core: Reject non-positive AUX snapshot sizes perf/core: Prevent AUX sampling from racing with pause/resume perf/core: Export output copy helpers for CoreSight coresight: perf: End AUX output when an event is throttled coresight: perf: Extract AUX buffer update helper coresight: perf: Simplify flow for CPUs without a path coresight: perf: Validate the live context through its path coresight: perf: Validate context before resuming trace coresight: perf: Improve hardware state transitions coresight: trbe: Pad snapshot buffers coresight: trbe: Use circular buffer mode for snapshots coresight: trbe: Track per-CPU sink interrupt handling coresight: trbe: Handle an already disabled sink coresight: perf: Look up the trace path in etm_event_pause() coresight: perf: Serialize AUX pause and resume with event stops coresight: perf: Support AUX sampling with per-CPU sinks perf cs-etm: Allow history collection for samples with zero IP perf cs-etm: Unify timeless buffer decoding perf cs-etm: Propagate errors from trace queue flushing perf cs-etm: Drain pending packets before finishing trace blocks perf cs-etm: Complete packet draining with end of trace perf cs-etm: Centralize sample history collection perf cs-etm: Decode AUX samples into callchains and branch stacks perf test: Add CoreSight AUX sample decoding test Documentation: coresight: Document AUX sample decoding Documentation/trace/coresight/coresight-perf.rst | 39 ++ drivers/hwtracing/coresight/coresight-etm-perf.c | 396 +++++++++++++----- drivers/hwtracing/coresight/coresight-etm-perf.h | 2 + drivers/hwtracing/coresight/coresight-trbe.c | 122 ++++-- include/linux/coresight.h | 2 + kernel/events/core.c | 26 +- kernel/events/ring_buffer.c | 2 + tools/perf/arch/arm/util/cs-etm.c | 6 + tools/perf/tests/shell/coresight/aux_sample.sh | 189 +++++++++ tools/perf/util/cs-etm-decoder/cs-etm-decoder.c | 39 ++ tools/perf/util/cs-etm-decoder/cs-etm-decoder.h | 7 + tools/perf/util/cs-etm.c | 491 ++++++++++++++++------- 12 files changed, 1040 insertions(+), 281 deletions(-) --- base-commit: 134e1295eedfc9a3c6e4e63d8ef45dc63749449b change-id: 20260826-arm_cs_support_aux_sample-275664545588 Best regards, -- Leo Yan <leo.yan(a)arm.com>

2 days, 12 hours

[PATCH v2 00/11] coresight: trbe: Refactor buffer handling and add trigger support

by Leo Yan

TRBE currently stops trace collection at each buffer limit, so interrupt latency can cause trace loss. This series adds trigger-based maintenance and WRAP mode to reduce these gaps, while protecting unconsumed data and retaining limit-based handling where required by errata. The perf changes preserve decoder state across contiguous indexed AUX fragments, with resets when continuity cannot be established. Thread stacks still flush at each data block boundary. For normal recording, a quarter-buffer watermark wakes userspace earlier. The 11 patches cover: Patches 01-02: Next-buffer computation cleanup and refactoring. Patches 03-07: Trigger support, headroom, save/restore, and KUnit tests. Patches 08-11: Decoder continuity and earlier userspace wakeups. This series is based on coresight-next and requires "coresight: trbe: Refactor buffer and IRQ handling" [1] to be applied first. This series has been tested on the Orion6 board with TRBE and the Juno-r2 board with ETR using the following commands: perf record -e cs_etm// -a -- bash -c 'for i in {1..5}; do timeout 0.1 yes > /dev/null; sleep 0.1; done' perf script --itrace=i1000iTZ [1] https://lore.kernel.org/linux-arm-kernel/20261016-trbe_enable_disable_irq_h… Signed-off-by: Leo Yan <leo.yan(a)arm.com> --- Changes in v2: - Split the enable/disable, perf-handle lifecycle, and IRQ handling fixes into the separate prerequisite series, leaving 11 patches here. - Restrict KUnit buffer and padding stubs to the synthetic test handle, preserving normal buffer lookup and AUX accounting for real perf IRQs. - Centralize decoder-reset decisions in cs_etm__get_trace(), while retaining thread-stack flushing at every data block boundary. - Reset per-thread decoders for unknown or changed CPUs, preserve CPU metadata on all split pieces, and retain resets through empty fragments. - Reset the decoder on logical AUX offset discontinuities, including clipped snapshots and missing AUX records, while preserving continuity across internal buffer splits. - Link to v1: https://lore.kernel.org/r/20251201-trbe_buffer_refactor_v1-1-v1-0-7da32b076… --- Leo Yan (11): coresight: trbe: Remove misleading comment coresight: trbe: Refactor next buffer computation coresight: trbe: Track trigger count support per CPU coresight: trbe: Use trigger mode for buffer maintenance coresight: trbe: Leave headroom for stop-on-trigger mode coresight: trbe: Save and restore trigger counter coresight: trbe: Add KUnit tests for compute normal buffer perf cs-etm: Reset decoder on COLLISION flag perf cs-etm: Reset per-thread decoder on CPU migration perf cs-etm: Reset decoder on AUX offset discontinuity perf cs-etm: Set watermark for AUX trace drivers/hwtracing/coresight/Kconfig | 15 + .../coresight/coresight-trbe-kunit-tests.c | 644 +++++++++++++++++++++ drivers/hwtracing/coresight/coresight-trbe.c | 342 ++++++++--- drivers/hwtracing/coresight/coresight-trbe.h | 18 + tools/perf/arch/arm/util/cs-etm.c | 15 + tools/perf/util/auxtrace.h | 2 + tools/perf/util/cs-etm.c | 92 ++- 7 files changed, 1029 insertions(+), 99 deletions(-) --- base-commit: 343cfcbb3ecfdb80aa576a428cfa3b65ad783842 change-id: 20260617-trbe_buffer_refactor_v2-8813e33fde8b prerequisite-message-id: <20261016-trbe_enable_disable_irq_handle_refactor-v2-0-3f57cf3199b1(a)arm.com> prerequisite-patch-id: 295f75af9986fc6193b0f3ec0f144096c1194efd prerequisite-patch-id: 60541bcf6bd25acf076fca2dd2e62ea382541fd5 prerequisite-patch-id: 0a6dbd3a69611c9bdca8ad61ea943d6577251fb8 prerequisite-patch-id: 0f4dc971d1375cd5672a63cd148b6e7f6dfdd9b3 prerequisite-patch-id: b42114d2185bbd15c9095191417aad34137cc5e9 prerequisite-patch-id: fdcdce0d19c611de475c6e9737ef544a9fb19153 prerequisite-patch-id: 948b6aa1254adfc9f89a5aba3ef45e41d891debe prerequisite-patch-id: ba1cc65a72bcfef9e22fea14f52eeaeeb2c551d3 prerequisite-patch-id: d0efcfbe7d1f7886aaa5c34655c14a979bf55863 prerequisite-patch-id: af045abf5718e35f16a5b98ec7c04213cf24d426 prerequisite-patch-id: d0af1d9f5551622858815d148de5dc3c94cdf564 prerequisite-patch-id: 9d02a95ecafda17debf728ef1098b98030019a10 prerequisite-patch-id: c6251f03223c3bd4bcf43abc292907dd93cad527 prerequisite-patch-id: 690af6c1769b93d8712aa73b322bb4e5f0acdc66 prerequisite-patch-id: 21c3d8dacd550b977ae549a1865e43523ed64f98 prerequisite-patch-id: 0b5666068c0fed73e6906473b38861556881e5b0 prerequisite-patch-id: f5c97c9acc3e691b3612999eae97c3366acf3d97 prerequisite-patch-id: 55846a3b80ca3196062d06522af768ac83751d97 prerequisite-patch-id: 5f5be1d1c925a9c0d945eba516a9075153045292 prerequisite-patch-id: 8e39271308702e557abc4e4e79fc96d0157844a7 prerequisite-patch-id: b99199a58c4a87408c4c2b0b39ee4861f5cd9d80 prerequisite-patch-id: 1bdbfe0417a4a98984b2fbe8d664738657de3032 prerequisite-patch-id: aeab33675e29539d239c8ffdf4bbd4cf861972c6 Best regards, -- Leo Yan <leo.yan(a)arm.com>

6 days, 5 hours

[PATCH v2 00/23] coresight: trbe: Refactor buffer and IRQ handling

by Leo Yan

This series follows the earlier TRBE buffer refactoring posting [1]. The work is now split into two parts. This first part contains fixes and refactoring in preparation for wrap and trigger mode support. Support for those modes will be sent separately. The patches are grouped as follows for easier review: Patches 1-5: Minor fixes Add register definitions, fix the watermark range check, and improve erratum checks and perf handle validation. Patches 6-11: Enable/disable lifecycle fixes Clean up session setup, status clearing and IRQ handle ownership. Patches 12-17: Refine status classification Decode stop reasons, report truncation on errors and improve trace-size accounting. Patches 18-23: Improve IRQ and overflow handling Keep the handle in per-CPU data, stabilize status reads, and improve AUX restarts and trace-gap reporting. A race also remains between TRBE interrupt handling and AUX pause/resume from a sampling NMI. This should be resolved as part of the state machine refactoring in the CoreSight AUX sampling series [2]. [1] https://lore.kernel.org/linux-arm-kernel/20251201-trbe_buffer_refactor_v1-1… [2] https://lore.kernel.org/linux-arm-kernel/20260915-arm_cs_support_aux_sample… Signed-off-by: Leo Yan <leo.yan(a)arm.com> --- Leo Yan (23): arm64/sysreg: Define TRBSR_EL1.EC event classes coresight: trbe: Make watermark range check overflow safe in __trbe_normal_offset() coresight: trbe: Use helpers for checking errata coresight: trbe: Check the buffer association before IRQ validation coresight: trbe: Validate perf handle before using sink data coresight: trbe: Drop redundant disable from enable path coresight: trbe: Publish the session after successful enable coresight: trbe: Clear stale external abort status coresight: trbe: Clear TRBSR status at stop sites coresight: trbe: Drop redundant disables coresight: trbe: Assign the perf handle in enable and disable coresight: trbe: Decode TRBSR status codes coresight: trbe: Simplify wrap status handling coresight: trbe: Treat access not allowed stops as fatal coresight: trbe: Report truncated trace on buffer update errors coresight: trbe: Always classify TRBSR when updating buffer coresight: trbe: Calculate trace size across buffer wrap coresight: trbe: Keep the perf handle in per-CPU data coresight: trbe: Reload the AUX buffer on overflow restart coresight: trbe: Add fault action argument to trbe_handle_overflow() coresight: trbe: Read TRBSR after prohibiting and flushing trace coresight: trbe: Restart trace source for stopped buffers coresight: trbe: Report trace gaps with PARTIAL instead of COLLISION arch/arm64/include/asm/sysreg.h | 6 + arch/arm64/tools/sysreg | 8 +- drivers/hwtracing/coresight/coresight-trbe.c | 481 ++++++++++++++++++--------- drivers/hwtracing/coresight/coresight-trbe.h | 8 - 4 files changed, 345 insertions(+), 158 deletions(-) --- base-commit: 343cfcbb3ecfdb80aa576a428cfa3b65ad783842 change-id: 20261016-trbe_enable_disable_irq_handle_refactor-0a3450f03473 Best regards, -- Leo Yan <leo.yan(a)arm.com>

6 days, 9 hours

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CoreSight October 2026