CoreSight December 2025

coresight@lists.linaro.org

7 participants
49 discussions

by Leo Yan

Kconfig symbols must not include the CONFIG_ prefix. Remove the CONFIG_ prefix for default values to work. Fixes: a02509f301c6 ("stm class: Factor out default framing protocol") Fixes: d69d5e83110f ("stm class: Add MIPI SyS-T protocol support") Signed-off-by: Leo Yan <leo.yan(a)arm.com> --- drivers/hwtracing/stm/Kconfig | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/hwtracing/stm/Kconfig b/drivers/hwtracing/stm/Kconfig index eda6b11d40a1f9ab49a1ec1e6faae8ee178c5ed3..cd7f0b0f3fbebc74775d8835187e49e5bd21d646 100644 --- a/drivers/hwtracing/stm/Kconfig +++ b/drivers/hwtracing/stm/Kconfig @@ -13,7 +13,7 @@ if STM config STM_PROTO_BASIC tristate "Basic STM framing protocol driver" - default CONFIG_STM + default STM help This is a simple framing protocol for sending data over STM devices. This was the protocol that the STM framework used @@ -28,7 +28,7 @@ config STM_PROTO_BASIC config STM_PROTO_SYS_T tristate "MIPI SyS-T STM framing protocol driver" - default CONFIG_STM + default STM help This is an implementation of MIPI SyS-T protocol to be used over the STP transport. In addition to the data payload, it --- base-commit: 40fbbd64bba6c6e7a72885d2f59b6a3be9991eeb change-id: 20251216-fix_stm_kconfig-a72f40c7612c Best regards, -- Leo Yan <leo.yan(a)arm.com>

8 months, 1 week

[PATCH RESEND v5 0/3] coresight-tnoc: Add support for Interconnect TNOC

by Yuanfang Zhang

This patch series adds support for the Qualcomm CoreSight Interconnect TNOC (Trace Network On Chip) block, which acts as a CoreSight graph link forwarding trace data from subsystems to the Aggregator TNOC. Unlike the Aggregator TNOC, this block does not support aggregation or ATID assignment. Signed-off-by: Yuanfang Zhang <yuanfang.zhang(a)oss.qualcomm.com> --- Changes in v5: - Add the missing review-by tag for patch 3. - Link to v4: https://lore.kernel.org/r/20250831-itnoc-v4-0-f0fb0ef822a5@oss.qualcomm.com Changes in v4: - Fix unintended blank line removals in trace_noc_enable_hw. - Link to v3: https://lore.kernel.org/r/20250828-itnoc-v3-0-f1b55dea7a27@oss.qualcomm.com Changes in v3: - Add detail for changes in V2. - Remove '#address-cells' and '#size-cells' properties from in-ports field. - Fix comment indentation for packet description. - Link to v2: https://lore.kernel.org/r/20250819-itnoc-v2-0-2d0e6be44e2f@oss.qualcomm.com Changes in v2: - Removed the trailing '|' after the description in qcom,coresight-itnoc.yaml. - Dropped the 'select' section from the YAML file. - Updated node name to use a more generic naming convention. - Removed the 'items' property from the compatible field. - Deleted the description for the reg property. - Dropped clock-names and adjusted the order of clock-names and clocks. - Moved additionalProperties to follow the $ref of out-ports. - Change "atid" type from u32 to int, set it as "-EOPNOTSUPP" for non-AMBA device. - Link to v1: https://lore.kernel.org/r/20250815-itnoc-v1-0-62c8e4f7ad32@oss.qualcomm.com --- Yuanfang Zhang (3): dt-bindings: arm: qcom: Add Coresight Interconnect TNOC coresight-tnoc: add platform driver to support Interconnect TNOC coresight-tnoc: Add runtime PM support for Interconnect TNOC .../bindings/arm/qcom,coresight-itnoc.yaml | 90 ++++++++++++++ drivers/hwtracing/coresight/coresight-tnoc.c | 136 +++++++++++++++++++-- 2 files changed, 215 insertions(+), 11 deletions(-) --- base-commit: 2b52cf338d39d684a1c6af298e8204902c026aca change-id: 20250815-itnoc-460273d1b80c Best regards, -- Yuanfang Zhang <yuanfang.zhang(a)oss.qualcomm.com>

8 months, 1 week

[PATCH v4 00/14] perf cs-etm/arm-spe: Remove hard coded config fields

by James Clark

The specific config field that an event format attribute is in is consistently hard coded, even though the API is supposed to be that the driver publishes the config field name. To stop this pattern from being copy pasted and causing problems in the future, replace them all with calls to a new helper that returns the value that a user set. This reveals some issues in evsel__set_config_if_unset(). It doesn't work with sparse bitfields, which are an unused but documented feature. And it also only writes to the attr.config field. To fix it we need to start tracking user changes for all config fields and then use existing helper functions that support sparse bitfields. Some other refactoring was also required and a test was added. --- Changes in v4: - Constify some function args (Ian) - Move some evsel__* functions to evsel.c and make some pmu.c functions public to support this (Ian) - Drop pmu arg where it can be fetched from evsel->pmu (Ian) - Link to v3: https://lore.kernel.org/r/20251212-james-perf-config-bits-v3-0-aa36a4846776… Changes in v3: - Fix uninitialized variable warning on GCC - Fix leak of evlist in test - Confirm no type punning issues with ubsan (Ian) - Link to v2: https://lore.kernel.org/r/20251208-james-perf-config-bits-v2-0-4ac0281993b0… Changes in v2: - Remove macros in get_config_chgs() and some other refactoring. - Support sparse bitfields in evsel__set_config_if_unset(). - Always track user changes instead of only when 'pmu->perf_event_attr_init_default' is set. - Add a test. - Don't bail out in cs-etm.c if any format fields are missing (Leo). - Rename 'guess' to 'synth' (Mike). - Link to v1: https://lore.kernel.org/r/20251201-james-perf-config-bits-v1-0-22ecbbf8007c… --- James Clark (14): perf parse-events: Refactor get_config_terms() to remove macros perf evsel: Refactor evsel__set_config_if_unset() arguments perf evsel: Move evsel__* functions to evsel.c perf evsel: Support sparse fields in evsel__set_config_if_unset() perf parse-events: Track all user changed config bits perf evsel: apply evsel__set_config_if_unset() to all config fields perf evsel: Add a helper to get the value of a config field perf parse-events: Always track user config changes perf tests: Test evsel__set_config_if_unset() and config change tracking perf cs-etm: Make a helper to find the Coresight evsel perf cs-etm: Don't use hard coded config bits when setting up ETMCR perf cs-etm: Don't use hard coded config bits when setting up TRCCONFIGR perf cs-etm: Don't hard code config attribute when configuring the event perf arm-spe: Don't hard code config attribute tools/perf/arch/arm/util/cs-etm.c | 201 +++++++++++++++------------- tools/perf/arch/arm64/util/arm-spe.c | 17 +-- tools/perf/arch/x86/util/intel-pt.c | 3 +- tools/perf/tests/pmu.c | 91 +++++++++++++ tools/perf/util/evsel.c | 112 +++++++++++++++- tools/perf/util/evsel.h | 6 +- tools/perf/util/evsel_config.h | 7 +- tools/perf/util/parse-events.c | 248 ++++++++++++++++++++--------------- tools/perf/util/pmu.c | 95 ++++---------- tools/perf/util/pmu.h | 34 ++++- 10 files changed, 529 insertions(+), 285 deletions(-) --- base-commit: cbd41c6d4c26c161a2b0e70ad411d3885ff13507 change-id: 20251112-james-perf-config-bits-bee7106f0f00 Best regards, -- James Clark <james.clark(a)linaro.org>

8 months, 2 weeks

[PATCH v8 00/13] coresight: Update timestamp attribute to be an interval instead of bool

by James Clark

Do some cleanups then expand the timestamp format attribute from 1 bit to 4 bits for ETMv4 in Perf mode. The current interval is too high for most use cases, and particularly on the FVP the number of timestamps generated is excessive. This change not only still allows disabling or enabling timestamps, but also allows the interval to be configured. The old bit is kept deprecated and undocumented for now. There are known broken versions of Perf that don't read the format attribute positions from sysfs and instead hard code the timestamp bit. We can leave the old bit in the driver until we need the bit for another feature or enough time has passed that these old Perfs are unlikely to be used. The interval option is added as an event format attribute, rather than a Coresight config because it's something that the driver is already configuring automatically in Perf mode using any unused counter, so it's not possible to modify this with a config. Applies to coresight/next Signed-off-by: James Clark <james.clark(a)linaro.org> --- Changes in v8: - Handle ts_level attribute outside etm4_config_timestamp_event() (Mike) - Flip commits 11 and 12 so that the new attribute works as soon as it's published to sysfs for bisecting (Suzuki) - Remove some spurious header includes - Link to v7: https://lore.kernel.org/r/20251126-james-cs-syncfreq-v7-0-7fae5e0e5e16@lina… Changes in v7: - Change TRCCNTCTLRn and TRCTSCTLR register definitions to use a combined field for TYPE and SEL (EVENT) so that they can be used with the new utilities. - Add utility functions for creating resource selectors that do compile and runtime checking of the resource selector ID. - Link to v6: https://lore.kernel.org/r/20251119-james-cs-syncfreq-v6-0-740d24a29e51@lina… Changes in v6: - #ifdef out format attributes for ETMv3 instead of using is_visible(). Then the same block can be used to define format_attr_contextid_show() which avoids an awkward WARN_ONCE() and comments in arm32 for a function that's never called. - Link to v5: https://lore.kernel.org/r/20251118-james-cs-syncfreq-v5-0-82efd7b1a751@lina… Changes in v5: - Add parens to interval calculation in docs (Randy) - Swap "minimum interval" and "maximum interval" in docs. (Leo) - Add TRCSYNCPR.PERIOD to docs (Leo) - Use CONFIG_ARM64 to avoid is_kernel_in_hyp_mode() (Leo) - Add a comment for hidden ETMv3 format attributes (Leo) - Hide configid for ETMv3 (Leo) - Link to v4: https://lore.kernel.org/r/20251112-james-cs-syncfreq-v4-0-165ba21401dc@lina… Changes in v4: - Add #defines for true and false resources ETM_RES_SEL_TRUE/FALSE - Reword comment about finding a counter to say if there are no resources there are no counters. - Extend existing timestamp format attribute instead of adding a new one - Refactor all the config definitions and parsing to use GEN_PMU_FORMAT_ATTR()/ATTR_CFG_GET_FLD() so we can see where the unused bits are. - Link to v3: https://lore.kernel.org/r/20251002-james-cs-syncfreq-v3-0-fe5df2bf91d1@lina… Changes in v3: - Move the format attr definitions to coresight-etm-perf.h we can compile on arm32 without #ifdefs - (Leo) - Convert the new #ifdefs to a single one in an is_visible() function so that the code is cleaner - (Leo) - Drop the change to remove the holes in struct etmv4_config as they were grouped by function - (Mike) - Link to v2: https://lore.kernel.org/r/20250814-james-cs-syncfreq-v2-0-c76fcb87696d@lina… Changes in v2: - Only show the attribute for ETMv4 to improve usability and fix the arm32 build error. Wrapping everything in IS_ENABLED(CONFIG_CORESIGHT_SOURCE_ETM4X) isn't ideal, but the -perf.c file is shared between ETMv3 and ETMv4, and there is already precedent for doing it this way. - Link to v1: https://lore.kernel.org/r/20250811-james-cs-syncfreq-v1-0-b001cd6e3404@lina… --- James Clark (13): coresight: Change syncfreq to be a u8 coresight: Repack struct etmv4_drvdata coresight: Refactor etm4_config_timestamp_event() coresight: Hide unused ETMv3 format attributes coresight: Define format attributes with GEN_PMU_FORMAT_ATTR() coresight: Interpret ETMv3 config with ATTR_CFG_GET_FLD() coresight: Don't reject unrecognized ETMv3 format attributes coresight: Interpret perf config with ATTR_CFG_GET_FLD() coresight: Interpret ETMv4 config with ATTR_CFG_GET_FLD() coresight: Remove misleading definitions coresight: Prepare to allow setting the timestamp interval coresight: Extend width of timestamp format attribute coresight: docs: Document etm4x timestamp interval option Documentation/trace/coresight/coresight.rst | 16 +- drivers/hwtracing/coresight/coresight-etm-perf.c | 68 ++++---- drivers/hwtracing/coresight/coresight-etm-perf.h | 38 +++++ drivers/hwtracing/coresight/coresight-etm3x-core.c | 39 +++-- drivers/hwtracing/coresight/coresight-etm4x-core.c | 175 ++++++++++++--------- drivers/hwtracing/coresight/coresight-etm4x.h | 92 ++++++++--- include/linux/coresight-pmu.h | 24 --- 7 files changed, 279 insertions(+), 173 deletions(-) --- base-commit: 9e9182cab5ebc3ee7544e60ef08ba19fdf216920 change-id: 20250724-james-cs-syncfreq-7c2257a38ed3 Best regards, -- James Clark <james.clark(a)linaro.org>

8 months, 3 weeks

[PATCH] MAINTAINERS: Change of email address

by Mike Leach

My e-mail address for linux work is changing to mike.leach(a)arm.com from 1st Jan 2026. Update MAINTAINERS file accordingly Signed-off-by: Mike Leach <mike.leach(a)linaro.org> --- MAINTAINERS | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index 5b11839cba9d..e3974f9f300a 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2657,7 +2657,7 @@ N: digicolor ARM/CORESIGHT FRAMEWORK AND DRIVERS M: Suzuki K Poulose <suzuki.poulose(a)arm.com> -R: Mike Leach <mike.leach(a)linaro.org> +R: Mike Leach <mike.leach(a)arm.com> R: James Clark <james.clark(a)linaro.org> L: coresight(a)lists.linaro.org (moderated for non-subscribers) L: linux-arm-kernel(a)lists.infradead.org (moderated for non-subscribers) @@ -20476,7 +20476,7 @@ PERFORMANCE EVENTS TOOLING ARM64 R: John Garry <john.g.garry(a)oracle.com> R: Will Deacon <will(a)kernel.org> R: James Clark <james.clark(a)linaro.org> -R: Mike Leach <mike.leach(a)linaro.org> +R: Mike Leach <mike.leach(a)arm.com> R: Leo Yan <leo.yan(a)linux.dev> L: linux-arm-kernel(a)lists.infradead.org (moderated for non-subscribers) S: Supported -- 2.32.0

8 months, 3 weeks

[PATCH v4 0/3] Coresight TMC-ETR: refactor the tmc-etr mode and some cleanups

by Junhao He

This patchset builds upon Yicong's previous patches [1]. Patch 2 introducing fix race issues found by using TMC-ETR. Patch 1 & 3 introducing two cleanups found when debugging the issues. [1] https://lore.kernel.org/linux-arm-kernel/20241202092419.11777-1-yangyicong@… --- Changes in v4: - a) Add comment at the context of set etr to sysfs mode. - b) Move the check on drvdata->read to the start of enable etr. - c) Add checks to prevent multiple sysfs processes from simultaneously competing to enable ETR. - d) Fix the issue with the guard used. Link: https://lore.kernel.org/linux-arm-kernel/20250818080600.418425-1-hejunhao3@… --- Changes in v3: - Patches 1: Additional comment for tmc_drvdata::etr_mode. Update comment for tmc_drvdata::reading with Jonathan's Tag. - Patches 2: Replace scoped_guard with guard with Jonathan's Tag. - Patches 2: Fix spinlock to raw_spinlock, and refactor this code based on Leo's suggested solution. - Patches 3: change the size's type to ssize_t and use max_t to simplify the code with Leo's Tag. Link: https://lore.kernel.org/linux-arm-kernel/20250620075412.952934-1-hejunhao3@… Changes in v2: - Updated the commit of patch2. - Rebase to v6.16-rc1 Junhao He (1): coresight: tmc: refactor the tmc-etr mode setting to avoid race conditions Yicong Yang (2): coresight: tmc: Add missing doc including reading and etr_mode of struct tmc_drvdata coresight: tmc: Decouple the perf buffer allocation from sysfs mode .../hwtracing/coresight/coresight-tmc-etr.c | 136 +++++++++--------- drivers/hwtracing/coresight/coresight-tmc.h | 2 + 2 files changed, 66 insertions(+), 72 deletions(-) -- 2.33.0

9 months

Re: [PATCH v7 3/4] coresight: tpda: add logic to configure TPDA_SYNCR register

by Suzuki K Poulose

On 23/12/2025 08:41, Jie Gan wrote: > From: Tao Zhang <tao.zhang(a)oss.qualcomm.com> > > The TPDA_SYNC counter tracks the number of bytes transferred from the > aggregator. When this count reaches the value programmed in the > TPDA_SYNCR register, an ASYNC request is triggered, allowing userspace > tools to accurately parse each valid packet. > > Signed-off-by: Tao Zhang <tao.zhang(a)oss.qualcomm.com> > Reviewed-by: James Clark <james.clark(a)linaro.org> > Co-developed-by: Jie Gan <jie.gan(a)oss.qualcomm.com> > Signed-off-by: Jie Gan <jie.gan(a)oss.qualcomm.com> > --- > .../ABI/testing/sysfs-bus-coresight-devices-tpda | 18 +++++ > drivers/hwtracing/coresight/coresight-tpda.c | 90 ++++++++++++++++++++++ > drivers/hwtracing/coresight/coresight-tpda.h | 10 +++ > 3 files changed, 118 insertions(+) > > diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpda b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpda > index c8bc7b19ab25..c989eea1ef59 100644 > --- a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpda > +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpda > @@ -41,3 +41,21 @@ Contact: Jinlong Mao <jinlong.mao(a)oss.qualcomm.com>, Tao Zhang <tao.zhang(a)oss.qu > Description: > (RW) Set global (all ports) flush request bit. The bit remains set until a > global flush request sequence completes. > + > +What: /sys/bus/coresight/devices/<tpda-name>/syncr_mode > +Date: December 2025 > +KernelVersion: 6.19 > +Contact: Jinlong Mao <jinlong.mao(a)oss.qualcomm.com>, Tao Zhang <tao.zhang(a)oss.qualcomm.com>, Jie Gan <jie.gan(a)oss.qualcomm.com> > +Description: > + (RW) Set mode the of the syncr counter. > + mode 0 - COUNT[11:0] value represents the approximate number of bytes moved between two ASYNC packet requests > + mode 1 - the bits COUNT[11:7] are used as a power of 2. for example, we could insert an async packet every 8K > + data by writing a value 13 to the COUNT[11:7] field. > + > +What: /sys/bus/coresight/devices/<tpda-name>/syncr_count > +Date: December 2025 > +KernelVersion: 6.19 > +Contact: Jinlong Mao <jinlong.mao(a)oss.qualcomm.com>, Tao Zhang <tao.zhang(a)oss.qualcomm.com>, Jie Gan <jie.gan(a)oss.qualcomm.com> > +Description: > + (RW) Set value the of the syncr counter. > + Range: 0-4095 > diff --git a/drivers/hwtracing/coresight/coresight-tpda.c b/drivers/hwtracing/coresight/coresight-tpda.c > index d24a9098f1b1..8283e16ec400 100644 > --- a/drivers/hwtracing/coresight/coresight-tpda.c > +++ b/drivers/hwtracing/coresight/coresight-tpda.c > @@ -163,6 +163,20 @@ static void tpda_enable_pre_port(struct tpda_drvdata *drvdata) > */ > if (drvdata->trig_flag_ts) > writel_relaxed(0x0, drvdata->base + TPDA_FPID_CR); > + > + /* Initialize with a value of 0 */ > + val = 0; > + if (drvdata->syncr_mode) > + val |= TPDA_SYNCR_MODE_CTRL_MASK; > + > + if (drvdata->syncr_count > 0 && > + drvdata->syncr_count < TPDA_SYNCR_COUNT_MASK) > + val |= drvdata->syncr_count; > + else > + /* Program the count to its MAX value by default */ > + val |= TPDA_SYNCR_COUNT_MASK; > + > + writel_relaxed(val, drvdata->base + TPDA_SYNCR); > } > > static int tpda_enable_port(struct tpda_drvdata *drvdata, int port) > @@ -385,8 +399,84 @@ static ssize_t global_flush_req_store(struct device *dev, > } > static DEVICE_ATTR_RW(global_flush_req); > > +static ssize_t syncr_mode_show(struct device *dev, > + struct device_attribute *attr, > + char *buf) > +{ > + struct tpda_drvdata *drvdata = dev_get_drvdata(dev->parent); > + unsigned long val, syncr_val; > + > + if (!drvdata->csdev->refcnt) > + return -EINVAL; > + > + guard(spinlock)(&drvdata->spinlock); > + syncr_val = readl_relaxed(drvdata->base + TPDA_SYNCR); > + val = FIELD_GET(TPDA_SYNCR_MODE_CTRL_MASK, syncr_val); > + > + return sysfs_emit(buf, "%lu\n", val); > +} > + > +static ssize_t syncr_mode_store(struct device *dev, > + struct device_attribute *attr, > + const char *buf, > + size_t size) > +{ > + struct tpda_drvdata *drvdata = dev_get_drvdata(dev->parent); > + unsigned long val; > + > + if (kstrtoul(buf, 0, &val)) > + return -EINVAL; > + > + guard(spinlock)(&drvdata->spinlock); > + /* set the mode when first enabling the device */ > + drvdata->syncr_mode = !!val; > + > + return size; > +} > +static DEVICE_ATTR_RW(syncr_mode); > + > +static ssize_t syncr_count_show(struct device *dev, > + struct device_attribute *attr, > + char *buf) > +{ > + struct tpda_drvdata *drvdata = dev_get_drvdata(dev->parent); > + unsigned long val; > + > + if (!drvdata->csdev->refcnt) > + return -EINVAL; > + > + guard(spinlock)(&drvdata->spinlock); > + val = readl_relaxed(drvdata->base + TPDA_SYNCR); > + val &= TPDA_SYNCR_COUNT_MASK; > + > + return sysfs_emit(buf, "%lu\n", val); > +} > + > +static ssize_t syncr_count_store(struct device *dev, > + struct device_attribute *attr, > + const char *buf, > + size_t size) > +{ > + struct tpda_drvdata *drvdata = dev_get_drvdata(dev->parent); > + unsigned long val; > + > + if (kstrtoul(buf, 0, &val)) > + return -EINVAL; > + > + if (val < 0 || val > TPDA_SYNCR_COUNT_MASK) Checking "val < 0" for an unsigned type is invalid. Simply keep the second part. Suzuki > + return -EINVAL; > + > + guard(spinlock)(&drvdata->spinlock); > + drvdata->syncr_count = val; > + > + return size; > +} > +static DEVICE_ATTR_RW(syncr_count); > + > static struct attribute *tpda_attrs[] = { > &dev_attr_global_flush_req.attr, > + &dev_attr_syncr_mode.attr, > + &dev_attr_syncr_count.attr, > tpda_trig_sysfs_rw(freq_ts_enable, FREQTS), > tpda_trig_sysfs_rw(trig_freq_enable, FRIE), > tpda_trig_sysfs_rw(trig_flag_ts_enable, FLRIE), > diff --git a/drivers/hwtracing/coresight/coresight-tpda.h b/drivers/hwtracing/coresight/coresight-tpda.h > index 1cc9253293ec..56d35697303a 100644 > --- a/drivers/hwtracing/coresight/coresight-tpda.h > +++ b/drivers/hwtracing/coresight/coresight-tpda.h > @@ -9,6 +9,7 @@ > #define TPDA_CR (0x000) > #define TPDA_Pn_CR(n) (0x004 + (n * 4)) > #define TPDA_FPID_CR (0x084) > +#define TPDA_SYNCR (0x08C) > > /* Cross trigger global (all ports) flush request bit */ > #define TPDA_CR_FLREQ BIT(0) > @@ -36,6 +37,11 @@ > /* Aggregator port DSB data set element size bit */ > #define TPDA_Pn_CR_DSBSIZE BIT(8) > > +/* TPDA_SYNCR count mask */ > +#define TPDA_SYNCR_COUNT_MASK GENMASK(11, 0) > +/* TPDA_SYNCR mode control bit */ > +#define TPDA_SYNCR_MODE_CTRL_MASK GENMASK(12, 12) > + > #define TPDA_MAX_INPORTS 32 > > /** > @@ -52,6 +58,8 @@ > * @trig_freq: Enable/disable cross trigger FREQ packet request interface. > * @freq_ts: Enable/disable the timestamp for all FREQ packets. > * @cmbchan_mode: Configure the CMB/MCMB channel mode. > + * @syncr_mode: Setting the mode for counting packets. > + * @syncr_count: Setting the value of the count. > */ > struct tpda_drvdata { > void __iomem *base; > @@ -66,6 +74,8 @@ struct tpda_drvdata { > bool trig_freq; > bool freq_ts; > bool cmbchan_mode; > + bool syncr_mode; > + u32 syncr_count; > }; > > /* Enumerate members of global control register(cr) */ >

9 months, 1 week

Re: [PATCH v6 4/4] coresight: tpda: add sysfs node to flush specific port

by Suzuki K Poulose

On 23/12/2025 02:16, Jie Gan wrote: > > > On 12/22/2025 9:12 PM, Suzuki K Poulose wrote: >> On 22/12/2025 06:02, Jie Gan wrote: >>> From: Tao Zhang <tao.zhang(a)oss.qualcomm.com> >>> >>> Setting bit i in the TPDA_FLUSH_CR register initiates a flush request >>> for port i, forcing the data to synchronize and be transmitted to the >>> sink device. >>> >>> Signed-off-by: Tao Zhang <tao.zhang(a)oss.qualcomm.com> >>> Reviewed-by: James Clark <james.clark(a)linaro.org> >>> Co-developed-by: Jie Gan <jie.gan(a)oss.qualcomm.com> >>> Signed-off-by: Jie Gan <jie.gan(a)oss.qualcomm.com> >>> --- >>> .../ABI/testing/sysfs-bus-coresight-devices-tpda | 7 ++++ >>> drivers/hwtracing/coresight/coresight-tpda.c | 40 +++++++++++ >>> + ++++++++++ >>> drivers/hwtracing/coresight/coresight-tpda.h | 1 + >>> 3 files changed, 48 insertions(+) >>> >>> diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices- >>> tpda b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpda >>> index d359d90dca72..df8f03d4b573 100644 >>> --- a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpda >>> +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpda >>> @@ -51,3 +51,10 @@ Description: >>> mode 0 - COUNT[11:0] value represents the approximate >>> number of bytes moved between two ASYNC packet requests >>> mode 1 - the bits COUNT[11:7] are used as a power of 2. for >>> example, we could insert an async packet every 8K >>> data by writing a value 13 to the COUNT[11:7] field. >>> + >>> +What: /sys/bus/coresight/devices/<tpda-name>/port_flush_req >>> +Date: December 2025 >>> +KernelVersion: 6.19 >>> +Contact: Jinlong Mao <jinlong.mao(a)oss.qualcomm.com>, Tao Zhang >>> <tao.zhang(a)oss.qualcomm.com>, Jie Gan <jie.gan(a)oss.qualcomm.com> >>> +Description: >>> + (RW) Configure the bit i to requests a flush operation of >>> port i on the TPDA. >> >> Does this have similar semantics as the "global_flush_req" for "Read" ? > > Yes, global_flush_req triggers all ports at once, whereas this node > initiates a flush request for specific port(s). > > For reading, we can check whether the flush request has completed. Please document it as such. Suzuki > > Thanks, > Jie > >> i.e., the bit stays set until the request completes ? Otherwise, why >> isn't this Write only ? >> >> I don't see the point of "Reading" this value back. >> >> Suzuki >> >>> diff --git a/drivers/hwtracing/coresight/coresight-tpda.c b/drivers/ >>> hwtracing/coresight/coresight-tpda.c >>> index 7baa8a0965d3..f79fea4fbb2c 100644 >>> --- a/drivers/hwtracing/coresight/coresight-tpda.c >>> +++ b/drivers/hwtracing/coresight/coresight-tpda.c >>> @@ -430,9 +430,49 @@ static ssize_t syncr_mode_store(struct device *dev, >>> } >>> static DEVICE_ATTR_RW(syncr_mode); >>> +static ssize_t port_flush_req_show(struct device *dev, >>> + struct device_attribute *attr, >>> + char *buf) >>> +{ >>> + struct tpda_drvdata *drvdata = dev_get_drvdata(dev->parent); >>> + unsigned long val; >>> + >>> + if (!drvdata->csdev->refcnt) >>> + return -EINVAL; >>> + >>> + guard(spinlock)(&drvdata->spinlock); >>> + val = readl_relaxed(drvdata->base + TPDA_FLUSH_CR); >>> + >>> + return sysfs_emit(buf, "0x%lx\n", val); >>> +} >>> + >>> +static ssize_t port_flush_req_store(struct device *dev, >>> + struct device_attribute *attr, >>> + const char *buf, >>> + size_t size) >>> +{ >>> + struct tpda_drvdata *drvdata = dev_get_drvdata(dev->parent); >>> + u32 val; >>> + >>> + if (kstrtou32(buf, 0, &val)) >>> + return -EINVAL; >>> + >>> + if (!drvdata->csdev->refcnt || !val) >>> + return -EINVAL; >>> + >>> + guard(spinlock)(&drvdata->spinlock); >>> + CS_UNLOCK(drvdata->base); >>> + writel_relaxed(val, drvdata->base + TPDA_FLUSH_CR); >>> + CS_LOCK(drvdata->base); >>> + >>> + return size; >>> +} >>> +static DEVICE_ATTR_RW(port_flush_req); >>> + >>> static struct attribute *tpda_attrs[] = { >>> &dev_attr_global_flush_req.attr, >>> &dev_attr_syncr_mode.attr, >>> + &dev_attr_port_flush_req.attr, >>> tpda_trig_sysfs_rw(freq_ts_enable, FREQTS), >>> tpda_trig_sysfs_rw(trig_freq_enable, FRIE), >>> tpda_trig_sysfs_rw(trig_flag_ts_enable, FLRIE), >>> diff --git a/drivers/hwtracing/coresight/coresight-tpda.h b/drivers/ >>> hwtracing/coresight/coresight-tpda.h >>> index 1d2de50bb9f9..ef1ce2ce36a9 100644 >>> --- a/drivers/hwtracing/coresight/coresight-tpda.h >>> +++ b/drivers/hwtracing/coresight/coresight-tpda.h >>> @@ -10,6 +10,7 @@ >>> #define TPDA_Pn_CR(n) (0x004 + (n * 4)) >>> #define TPDA_FPID_CR (0x084) >>> #define TPDA_SYNCR (0x08C) >>> +#define TPDA_FLUSH_CR (0x090) >>> /* Cross trigger global (all ports) flush request bit */ >>> #define TPDA_CR_FLREQ BIT(0) >>> >> >

9 months, 1 week

Re: [PATCH v6 4/4] coresight: tpda: add sysfs node to flush specific port

by Suzuki K Poulose

On 22/12/2025 06:02, Jie Gan wrote: > From: Tao Zhang <tao.zhang(a)oss.qualcomm.com> > > Setting bit i in the TPDA_FLUSH_CR register initiates a flush request > for port i, forcing the data to synchronize and be transmitted to the > sink device. > > Signed-off-by: Tao Zhang <tao.zhang(a)oss.qualcomm.com> > Reviewed-by: James Clark <james.clark(a)linaro.org> > Co-developed-by: Jie Gan <jie.gan(a)oss.qualcomm.com> > Signed-off-by: Jie Gan <jie.gan(a)oss.qualcomm.com> > --- > .../ABI/testing/sysfs-bus-coresight-devices-tpda | 7 ++++ > drivers/hwtracing/coresight/coresight-tpda.c | 40 ++++++++++++++++++++++ > drivers/hwtracing/coresight/coresight-tpda.h | 1 + > 3 files changed, 48 insertions(+) > > diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpda b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpda > index d359d90dca72..df8f03d4b573 100644 > --- a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpda > +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpda > @@ -51,3 +51,10 @@ Description: > mode 0 - COUNT[11:0] value represents the approximate number of bytes moved between two ASYNC packet requests > mode 1 - the bits COUNT[11:7] are used as a power of 2. for example, we could insert an async packet every 8K > data by writing a value 13 to the COUNT[11:7] field. > + > +What: /sys/bus/coresight/devices/<tpda-name>/port_flush_req > +Date: December 2025 > +KernelVersion: 6.19 > +Contact: Jinlong Mao <jinlong.mao(a)oss.qualcomm.com>, Tao Zhang <tao.zhang(a)oss.qualcomm.com>, Jie Gan <jie.gan(a)oss.qualcomm.com> > +Description: > + (RW) Configure the bit i to requests a flush operation of port i on the TPDA. Does this have similar semantics as the "global_flush_req" for "Read" ? i.e., the bit stays set until the request completes ? Otherwise, why isn't this Write only ? I don't see the point of "Reading" this value back. Suzuki > diff --git a/drivers/hwtracing/coresight/coresight-tpda.c b/drivers/hwtracing/coresight/coresight-tpda.c > index 7baa8a0965d3..f79fea4fbb2c 100644 > --- a/drivers/hwtracing/coresight/coresight-tpda.c > +++ b/drivers/hwtracing/coresight/coresight-tpda.c > @@ -430,9 +430,49 @@ static ssize_t syncr_mode_store(struct device *dev, > } > static DEVICE_ATTR_RW(syncr_mode); > > +static ssize_t port_flush_req_show(struct device *dev, > + struct device_attribute *attr, > + char *buf) > +{ > + struct tpda_drvdata *drvdata = dev_get_drvdata(dev->parent); > + unsigned long val; > + > + if (!drvdata->csdev->refcnt) > + return -EINVAL; > + > + guard(spinlock)(&drvdata->spinlock); > + val = readl_relaxed(drvdata->base + TPDA_FLUSH_CR); > + > + return sysfs_emit(buf, "0x%lx\n", val); > +} > + > +static ssize_t port_flush_req_store(struct device *dev, > + struct device_attribute *attr, > + const char *buf, > + size_t size) > +{ > + struct tpda_drvdata *drvdata = dev_get_drvdata(dev->parent); > + u32 val; > + > + if (kstrtou32(buf, 0, &val)) > + return -EINVAL; > + > + if (!drvdata->csdev->refcnt || !val) > + return -EINVAL; > + > + guard(spinlock)(&drvdata->spinlock); > + CS_UNLOCK(drvdata->base); > + writel_relaxed(val, drvdata->base + TPDA_FLUSH_CR); > + CS_LOCK(drvdata->base); > + > + return size; > +} > +static DEVICE_ATTR_RW(port_flush_req); > + > static struct attribute *tpda_attrs[] = { > &dev_attr_global_flush_req.attr, > &dev_attr_syncr_mode.attr, > + &dev_attr_port_flush_req.attr, > tpda_trig_sysfs_rw(freq_ts_enable, FREQTS), > tpda_trig_sysfs_rw(trig_freq_enable, FRIE), > tpda_trig_sysfs_rw(trig_flag_ts_enable, FLRIE), > diff --git a/drivers/hwtracing/coresight/coresight-tpda.h b/drivers/hwtracing/coresight/coresight-tpda.h > index 1d2de50bb9f9..ef1ce2ce36a9 100644 > --- a/drivers/hwtracing/coresight/coresight-tpda.h > +++ b/drivers/hwtracing/coresight/coresight-tpda.h > @@ -10,6 +10,7 @@ > #define TPDA_Pn_CR(n) (0x004 + (n * 4)) > #define TPDA_FPID_CR (0x084) > #define TPDA_SYNCR (0x08C) > +#define TPDA_FLUSH_CR (0x090) > > /* Cross trigger global (all ports) flush request bit */ > #define TPDA_CR_FLREQ BIT(0) >

9 months, 1 week

Re: [PATCH v6 3/4] coresight: tpda: add logic to configure TPDA_SYNCR register

by Suzuki K Poulose

On 22/12/2025 06:02, Jie Gan wrote: > From: Tao Zhang <tao.zhang(a)oss.qualcomm.com> > > The TPDA_SYNC counter tracks the number of bytes transferred from the > aggregator. When this count reaches the value programmed in the > TPDA_SYNCR register, an ASYNC request is triggered, allowing userspace > tools to accurately parse each valid packet. > > Signed-off-by: Tao Zhang <tao.zhang(a)oss.qualcomm.com> > Reviewed-by: James Clark <james.clark(a)linaro.org> > Co-developed-by: Jie Gan <jie.gan(a)oss.qualcomm.com> > Signed-off-by: Jie Gan <jie.gan(a)oss.qualcomm.com> > --- > .../ABI/testing/sysfs-bus-coresight-devices-tpda | 10 +++++ > drivers/hwtracing/coresight/coresight-tpda.c | 46 ++++++++++++++++++++++ > drivers/hwtracing/coresight/coresight-tpda.h | 8 ++++ > 3 files changed, 64 insertions(+) > > diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpda b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpda > index c8bc7b19ab25..d359d90dca72 100644 > --- a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpda > +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpda > @@ -41,3 +41,13 @@ Contact: Jinlong Mao <jinlong.mao(a)oss.qualcomm.com>, Tao Zhang <tao.zhang(a)oss.qu > Description: > (RW) Set global (all ports) flush request bit. The bit remains set until a > global flush request sequence completes. > + > +What: /sys/bus/coresight/devices/<tpda-name>/syncr_mode > +Date: December 2025 > +KernelVersion: 6.19 > +Contact: Jinlong Mao <jinlong.mao(a)oss.qualcomm.com>, Tao Zhang <tao.zhang(a)oss.qualcomm.com>, Jie Gan <jie.gan(a)oss.qualcomm.com> > +Description: > + (RW) Set mode the of the syncr counter. > + mode 0 - COUNT[11:0] value represents the approximate number of bytes moved between two ASYNC packet requests > + mode 1 - the bits COUNT[11:7] are used as a power of 2. for example, we could insert an async packet every 8K > + data by writing a value 13 to the COUNT[11:7] field. What is COUNT here ? and more importantly how is this usefule without the support for setting the COUNT ? Do we plan to expose setting this ? If yes, why not now ? I don't see the point of merging "this" patch without the support for setting the counter. Suzuki > diff --git a/drivers/hwtracing/coresight/coresight-tpda.c b/drivers/hwtracing/coresight/coresight-tpda.c > index d24a9098f1b1..7baa8a0965d3 100644 > --- a/drivers/hwtracing/coresight/coresight-tpda.c > +++ b/drivers/hwtracing/coresight/coresight-tpda.c > @@ -163,6 +163,15 @@ static void tpda_enable_pre_port(struct tpda_drvdata *drvdata) > */ > if (drvdata->trig_flag_ts) > writel_relaxed(0x0, drvdata->base + TPDA_FPID_CR); > + > + /* Initialize with a value of 0 */ > + val = 0; > + if (drvdata->syncr_mode) > + val |= TPDA_SYNCR_MODE_CTRL_MASK; > + > + /* Program the counter to its MAX value by default */ > + val |= TPDA_SYNCR_COUNTER_MASK; > + writel_relaxed(val, drvdata->base + TPDA_SYNCR); > } > > static int tpda_enable_port(struct tpda_drvdata *drvdata, int port) > @@ -385,8 +394,45 @@ static ssize_t global_flush_req_store(struct device *dev, > } > static DEVICE_ATTR_RW(global_flush_req); > > +static ssize_t syncr_mode_show(struct device *dev, > + struct device_attribute *attr, > + char *buf) > +{ > + struct tpda_drvdata *drvdata = dev_get_drvdata(dev->parent); > + unsigned long val, syncr_val; > + > + if (!drvdata->csdev->refcnt) > + return -EINVAL; > + > + guard(spinlock)(&drvdata->spinlock); > + syncr_val = readl_relaxed(drvdata->base + TPDA_SYNCR); > + val = FIELD_GET(TPDA_SYNCR_MODE_CTRL_MASK, syncr_val); > + > + return sysfs_emit(buf, "%lu\n", val); > +} > + > +static ssize_t syncr_mode_store(struct device *dev, > + struct device_attribute *attr, > + const char *buf, > + size_t size) > +{ > + struct tpda_drvdata *drvdata = dev_get_drvdata(dev->parent); > + unsigned long val; > + > + if (kstrtoul(buf, 0, &val)) > + return -EINVAL; > + > + guard(spinlock)(&drvdata->spinlock); > + /* set the mode when first enabling the device */ > + drvdata->syncr_mode = !!val; > + > + return size; > +} > +static DEVICE_ATTR_RW(syncr_mode); > + > static struct attribute *tpda_attrs[] = { > &dev_attr_global_flush_req.attr, > + &dev_attr_syncr_mode.attr, > tpda_trig_sysfs_rw(freq_ts_enable, FREQTS), > tpda_trig_sysfs_rw(trig_freq_enable, FRIE), > tpda_trig_sysfs_rw(trig_flag_ts_enable, FLRIE), > diff --git a/drivers/hwtracing/coresight/coresight-tpda.h b/drivers/hwtracing/coresight/coresight-tpda.h > index 1cc9253293ec..1d2de50bb9f9 100644 > --- a/drivers/hwtracing/coresight/coresight-tpda.h > +++ b/drivers/hwtracing/coresight/coresight-tpda.h > @@ -9,6 +9,7 @@ > #define TPDA_CR (0x000) > #define TPDA_Pn_CR(n) (0x004 + (n * 4)) > #define TPDA_FPID_CR (0x084) > +#define TPDA_SYNCR (0x08C) > > /* Cross trigger global (all ports) flush request bit */ > #define TPDA_CR_FLREQ BIT(0) > @@ -36,6 +37,11 @@ > /* Aggregator port DSB data set element size bit */ > #define TPDA_Pn_CR_DSBSIZE BIT(8) > > +/* TPDA_SYNCR counter mask */ > +#define TPDA_SYNCR_COUNTER_MASK GENMASK(11, 0) > +/* TPDA_SYNCR mode control bit */ > +#define TPDA_SYNCR_MODE_CTRL_MASK GENMASK(12, 12) > + > #define TPDA_MAX_INPORTS 32 > > /** > @@ -52,6 +58,7 @@ > * @trig_freq: Enable/disable cross trigger FREQ packet request interface. > * @freq_ts: Enable/disable the timestamp for all FREQ packets. > * @cmbchan_mode: Configure the CMB/MCMB channel mode. > + * @syncr_mode: Configure the mode for counting packets. > */ > struct tpda_drvdata { > void __iomem *base; > @@ -66,6 +73,7 @@ struct tpda_drvdata { > bool trig_freq; > bool freq_ts; > bool cmbchan_mode; > + bool syncr_mode; > }; > > /* Enumerate members of global control register(cr) */ >

9 months, 1 week

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