CoreSight

coresight@lists.linaro.org

7 participants
2474 discussions

[PATCH v3 0/9] coresight: Fix and improve clock usage

by Leo Yan

This series fixes and improves clock usage in the Arm CoreSight drivers. Based on the DT binding documents, the trace clock (atclk) is defined in some CoreSight modules, but support is absent. In most cases, the issue is hidden because the atclk clock is shared by multiple CoreSight modules and the clock is enabled anyway by other drivers. The first three patches address this issue. The programming clock (pclk) management in CoreSight drivers does not use the devm_XXX() variant APIs, the drivers needs to manually disable and release clocks for errors and for normal module exit. However, the drivers miss to disable clocks during module exit. The atclk may also not be disabled in CoreSight drivers during module exit. By using devm APIs, patches 04 and 05 fix clock disabling issues. Another issue is pclk might be enabled twice in init phase - once by AMBA bus driver, and again by CoreSight drivers. This is fixed in patch 06. Patches 07 to 09 refactor the clock related code. Patch 07 consolidats the clock initialization into a central place. Patch 08 makes the clock enabling sequence consistent. Patch 09 removes redundant condition checks and adds error handling in runtime PM. This series has been verified on Arm64 Hikey960 and Juno platforms. Changes from v2: - Updated subjects for patches 04 and 05 (Anshuman). - Refined condition checking "if (dev_is_amba(dev))" in patch 07 (Anshuman). Changes from v1: - Moved the coresight_get_enable_clocks() function into CoreSight core layer (James). - Added comments for clock naming "apb_pclk" and "apb" (James). - Re-ordered patches for easier understanding (Anshuman). - Minor improvement for commit log in patch 01 (Anshuman). Signed-off-by: Leo Yan <leo.yan(a)arm.com> --- Leo Yan (9): coresight: tmc: Support atclk coresight: catu: Support atclk coresight: etm4x: Support atclk coresight: Appropriately disable programming clocks coresight: Appropriately disable trace bus clocks coresight: Avoid enable programming clock duplicately coresight: Consolidate clock enabling coresight: Make clock sequence consistent coresight: Refactor runtime PM drivers/hwtracing/coresight/coresight-catu.c | 53 ++++++++--------- drivers/hwtracing/coresight/coresight-catu.h | 1 + drivers/hwtracing/coresight/coresight-core.c | 45 +++++++++++++++ drivers/hwtracing/coresight/coresight-cpu-debug.c | 41 +++++--------- drivers/hwtracing/coresight/coresight-ctcu-core.c | 24 +++----- drivers/hwtracing/coresight/coresight-etb10.c | 18 ++---- drivers/hwtracing/coresight/coresight-etm3x-core.c | 17 ++---- drivers/hwtracing/coresight/coresight-etm4x-core.c | 32 ++++++----- drivers/hwtracing/coresight/coresight-etm4x.h | 4 +- drivers/hwtracing/coresight/coresight-funnel.c | 66 ++++++++-------------- drivers/hwtracing/coresight/coresight-replicator.c | 63 ++++++++------------- drivers/hwtracing/coresight/coresight-stm.c | 34 +++++------ drivers/hwtracing/coresight/coresight-tmc-core.c | 48 ++++++++-------- drivers/hwtracing/coresight/coresight-tmc.h | 2 + drivers/hwtracing/coresight/coresight-tpiu.c | 36 +++++------- include/linux/coresight.h | 30 +--------- 16 files changed, 225 insertions(+), 289 deletions(-) --- base-commit: 408c97c4a5e0b634dcd15bf8b8808b382e888164 change-id: 20250609-arm_cs_fix_clock_v3_public-d546e8bfc852 Best regards, -- Leo Yan <leo.yan(a)arm.com>

2 months, 3 weeks

Re: [BUG] CoreSight: WARN_ON in coresight_disclaim_device_unlocked due to register reset on CPU power-cycle

by Suzuki K Poulose

Cc: coresight lists, Leo, James, Mike L Hello ! Thanks for the report ! In the future, please use scripts/get_maintainer.pl for the clear list of people/list for reporting issues. Response inline, below. On 20/06/2025 08:21, Keita Morisaki wrote: > Hello folks, > > I am writing to report a WARN_ON message I'm encountering in the > CoreSight driver on a multi-core ARM system running a 6.12-based kernel. > The warning appears consistently when disabling an Embedded Trace > Extension (ETE) source after it has been active. The issue is not > reproducible when CPUidle is disabled. > > The problem occurs because the driver assumes the CoreSight claim > register is persistent, but it could be reset by the CPUidle power > management flow. The section B2.3.2 of Arm CoreSight Architecture > Specification v3.0[1] indicates that the claim register must reset at > “reset”. A CPU power-up from an idle state can trigger a Cold reset, > which might explain this behavior. > > My ftrace analysis confirms this. I traced the only two functions that > modify the claim state: coresight_set_claim_tags (which sets the claim) > and coresight_clear_claim_tags (which is the only part of the kernel > that writes to CLAIMCLR). The trace shows the claim being set, followed > by a CPUidle transition, but no subsequent call to > coresight_clear_claim_tags. > > Here are the steps to reproduce the issue: > > modprobecoresight_etm4x > > # Enable any relevant sink > > echo1>/sys/bus/coresight/devices/ete0/enable_source > > echo0>/sys/bus/coresight/devices/ete0/enable_source > > > Here is a relevant snippet from the ftrace log that illustrates the > sequence: > > #tracer:function_graph > > # > > #CPUDURATIONFUNCTIONCALLS > > #||||||| > > 0)|coresight_claim_device_unlocked[coresight](){ > > 0)3.750us|coresight_set_claim_tags[coresight]();//Claimissethere > > 0)+20.260us|} > > 0)|/*psci_domain_idle_enter:cpu_id=0state={Our PSCI parameter value}*/// > CPUgoesidle > > 0)|/*psci_domain_idle_exit:cpu_id=0state={Our PSCI parameter value}*/// > CPUwakesup,causingColdreset > > ... > > 0)(a)309346.3us|coresight_disclaim_device_unlocked[coresight]();// > TriggersWARN_ON > > > The following WARN_ON [2] is printed because the CLAIMCLR register has > already been reset at the time coresight_disclaim_device_unlocked is > called, contrary to the driver's expectation. > We have the ETM driver performing the save/restore of ETM context during a CPUidle. This is only done when the ETM/ETE is described to be loosing context over PM operation. If this is not done (via DT), the driver doesn't do anything. This could be problematic. Could you try adding: "arm,coresight-loses-context-with-cpu" property to the ETE nodes and see if it makes a difference ? Kind regards Suzuki [0] https://elixir.bootlin.com/linux/v6.12/source/Documentation/devicetree/bind… > [416.354181][C0]WARNING:CPU:0PID:0atdrivers/hwtracing/coresight/ > coresight-core.c:187coresight_disclaim_device_unlocked+0x84/0x9c[coresight] > > [416.535454][C0]Calltrace: > > [416.538606][C0]coresight_disclaim_device_unlocked+0x84/0x9c[coresight] > > [416.549359][C0]etm4_disable_hw+0x2d8/0x374[coresight_etm4x] > > [416.623310][C0]do_idle+0x1d4/0x264 > > (Note on tracing: To get this detailed trace, I made two modifications > to the kernel. First, since the trace_psci_domain_idle_enter/exit events > are not available in kernel 6.12, I cherry-picked the upstream patch > 7b7644831e72 [3] to add them. Second, to specifically trace the claim > functions, I temporarily replaced their inline compiler hints with > noinline.) > > Given the evidence, it appears the driver's assumption that the claim > register is persistent across CPU power states is incorrect and may need > to be addressed. > > Could you please provide your guidance on this? > > Thank you for your time and assistance. > > [1] https://developer.arm.com/documentation/ihi0029/latest/ <https:// > developer.arm.com/documentation/ihi0029/latest/>_ > _[2] https://elixir.bootlin.com/linux/v6.12/source/drivers/hwtracing/ > coresight/coresight-core.c#L187 <https://elixir.bootlin.com/linux/v6.12/ > source/drivers/hwtracing/coresight/coresight-core.c#L187>_ > _[3] https://web.git.kernel.org/pub/scm/linux/kernel/git/torvalds/ > linux.git/commit/?id=7b7644831e7276f52a233ec685d13c965fff09d9 <https:// > web.git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/? > id=7b7644831e7276f52a233ec685d13c965fff09d9> > > Best regards, > Keita

2 months, 4 weeks

Re: [PATCH] coresight: Replace scnprintf() with sysfs_emit() in sysfs show functions

by James Clark

On 19/06/2025 4:07 pm, Chelsy Ratnawat wrote: > Replace calls to scnprintf() with sysfs_emit() in sysfs show functions. > These helpers are preferred in sysfs callbacks because they automatically > handle buffer sizing (PAGE_SIZE) and improve safety and readability. > > Signed-off-by: Chelsy Ratnawat <chelsyratnawat2001(a)gmail.com> > --- > .../hwtracing/coresight/coresight-etm-perf.c | 4 +- > .../coresight/coresight-etm3x-sysfs.c | 2 +- > .../coresight/coresight-etm4x-sysfs.c | 108 +++++++++--------- > drivers/hwtracing/coresight/coresight-stm.c | 8 +- There's two missing from coresight-sysfs.c. Might as well change those too while were here. With those changed: Reviewed-by: James Clark <james.clark(a)linaro.org>

3 months

OpenCSD v1.6.1-rc1 release

by Mike Leach

A branch ocsd-main-v1.6.1-rc1 has been released on the OpenCSD github site This contains a number of bugfixes for issues relating to ETMv4 ETE speculative trace. See readme for further information. This has been released to allow for testing and feedback. Known issues outstanding: a) TINFO logging has minor issue on periodic TINFO elements. b) ETMv3 / PTM regression testss failing on return stack tests. Under investigation as this code is not part of the update. -- Mike Leach Principal Engineer, ARM Ltd. Manchester Design Centre. UK

3 months

Re: [PATCH v2] coresight: fix indentation error in cscfg_remove_owned_csdev_configs()

by Leo Yan

On Wed, Jun 11, 2025 at 11:30:25AM +0100, Yeoreum Yun wrote: > Fix wrong indentation in cscfg_remove_owned_csdev_configs() > > Reported-by: kernel test robot <lkp(a)intel.com> > Closes: https://lore.kernel.org/oe-kbuild-all/202506102238.XQfScl5x-lkp@intel.com/ > Fixes: 53b9e2659719 ("coresight: holding cscfg_csdev_lock while removing cscfg from csdev") > Signed-off-by: Yeoreum Yun <yeoreum.yun(a)arm.com> Reviewed-by: Leo Yan <leo.yan(a)arm.com> > --- > > Sorry for my bad forgetting to run checkpatch.pl... > > --- > drivers/hwtracing/coresight/coresight-syscfg.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/hwtracing/coresight/coresight-syscfg.c b/drivers/hwtracing/coresight/coresight-syscfg.c > index 83dad24e0116..6836b05986e8 100644 > --- a/drivers/hwtracing/coresight/coresight-syscfg.c > +++ b/drivers/hwtracing/coresight/coresight-syscfg.c > @@ -395,7 +395,7 @@ static void cscfg_remove_owned_csdev_configs(struct coresight_device *csdev, voi > if (list_empty(&csdev->config_csdev_list)) > return; > > - guard(raw_spinlock_irqsave)(&csdev->cscfg_csdev_lock); > + guard(raw_spinlock_irqsave)(&csdev->cscfg_csdev_lock); > > list_for_each_entry_safe(config_csdev, tmp, &csdev->config_csdev_list, node) { > if (config_csdev->config_desc->load_owner == load_owner) > -- > LEVI:{C3F47F37-75D8-414A-A8BA-3980EC8A46D7} >

3 months, 1 week

[PATCH v9 0/2] coresight: Add Coresight Trace Network On Chip driver

by Yuanfang Zhang

The Trace Network On Chip (TNOC) is an integration hierarchy which is a hardware component that integrates the functionalities of TPDA and funnels. It collects trace from subsystems and transfers it to coresight sink. In addition to the generic TNOC mentioned above, there is also a special type of TNOC called Interconnect TNOC. Unlike the generic TNOC, the Interconnect TNOC doesn't need ATID. Its primary function is to connect the source of subsystems to the Aggregator TNOC. Its driver is different from this patch and will describe it and upstream its driver separately. Signed-off-by: Yuanfang Zhang <quic_yuanfang(a)quicinc.com> --- Changes in v9: - Mention the binding is only for Aggregator TNOC. - Link to v8: https://lore.kernel.org/r/20250606-trace-noc-v8-0-833f94712c57@quicinc.com Changes in v8: - Add sysfs node to expose atid. - Link to v7: https://lore.kernel.org/r/20250523-trace-noc-v7-0-d65edbab2997@quicinc.com Changes in v7: - Move the content in header file into coresight-tnoc.c. - Use scoped_guard() to replace spin_lock(). - Invoke coresight_trace_id_put_system_id() for registration failure. - Link to v6: https://lore.kernel.org/r/20250522-trace-noc-v6-0-f5a9bcae90ee@quicinc.com Changes in v6: - Add a newline after return statements. - Use 'x &= foo' to replace 'x = x & foo'. - Use 'x |= foo' to replace 'x = x | foo'. - Link to v5: https://lore.kernel.org/r/20250512-trace-noc-v5-0-f2ef070baee5@quicinc.com Changes in v5: - update cover-letter to describe the Interconnect TNOC. - Link to v4: https://lore.kernel.org/r/20250415-trace-noc-v4-0-979938fedfd8@quicinc.com Changes in v4: - Fix dt_binding warning. - update mask of trace_noc amba_id. - Modify driver comments. - rename TRACE_NOC_SYN_VAL to TRACE_NOC_SYNC_INTERVAL. - Link to v3: https://lore.kernel.org/r/20250411-trace-noc-v3-0-1f19ddf7699b@quicinc.com Changes in v3: - Remove unnecessary sysfs nodes. - update commit messages. - Use 'writel' instead of 'write_relaxed' when writing to the register for the last time. - Add trace_id ops. - Link to v2: https://lore.kernel.org/r/20250226-trace-noc-driver-v2-0-8afc6584afc5@quici… Changes in v2: - Modified the format of DT binging file. - Fix compile warnings. - Link to v1: https://lore.kernel.org/r/46643089-b88d-49dc-be05-7bf0bb21f847@quicinc.com --- Yuanfang Zhang (2): dt-bindings: arm: Add device Trace Network On Chip definition coresight: add coresight Trace Network On Chip driver .../bindings/arm/qcom,coresight-tnoc.yaml | 113 ++++++++++ drivers/hwtracing/coresight/Kconfig | 13 ++ drivers/hwtracing/coresight/Makefile | 1 + drivers/hwtracing/coresight/coresight-tnoc.c | 242 +++++++++++++++++++++ 4 files changed, 369 insertions(+) --- base-commit: a2cc6ff5ec8f91bc463fd3b0c26b61166a07eb11 change-id: 20250403-trace-noc-f8286b30408e Best regards, -- Yuanfang Zhang <quic_yuanfang(a)quicinc.com>

3 months, 1 week

[PATCH v8 0/2] coresight: Add Coresight Trace Network On Chip driver

by Yuanfang Zhang

The Trace Network On Chip (TNOC) is an integration hierarchy which is a hardware component that integrates the functionalities of TPDA and funnels. It collects trace from subsystems and transfers it to coresight sink. In addition to the generic TNOC mentioned above, there is also a special type of TNOC called Interconnect TNOC. Unlike the generic TNOC, the Interconnect TNOC doesn't need ATID. Its primary function is to connect the source of subsystems to the Aggregator TNOC. Its driver is different from this patch and will describe it and upstream its driver separately. Signed-off-by: Yuanfang Zhang <quic_yuanfang(a)quicinc.com> --- Changes in v8: - Add sysfs node to expose atid. - Link to v7: https://lore.kernel.org/r/20250523-trace-noc-v7-0-d65edbab2997@quicinc.com Changes in v7: - Move the content in header file into coresight-tnoc.c. - Use scoped_guard() to replace spin_lock(). - Invoke coresight_trace_id_put_system_id() for registration failure. - Link to v6: https://lore.kernel.org/r/20250522-trace-noc-v6-0-f5a9bcae90ee@quicinc.com Changes in v6: - Add a newline after return statements. - Use 'x &= foo' to replace 'x = x & foo'. - Use 'x |= foo' to replace 'x = x | foo'. - Link to v5: https://lore.kernel.org/r/20250512-trace-noc-v5-0-f2ef070baee5@quicinc.com Changes in v5: - update cover-letter to describe the Interconnect TNOC. - Link to v4: https://lore.kernel.org/r/20250415-trace-noc-v4-0-979938fedfd8@quicinc.com Changes in v4: - Fix dt_binding warning. - update mask of trace_noc amba_id. - Modify driver comments. - rename TRACE_NOC_SYN_VAL to TRACE_NOC_SYNC_INTERVAL. - Link to v3: https://lore.kernel.org/r/20250411-trace-noc-v3-0-1f19ddf7699b@quicinc.com Changes in v3: - Remove unnecessary sysfs nodes. - update commit messages. - Use 'writel' instead of 'write_relaxed' when writing to the register for the last time. - Add trace_id ops. - Link to v2: https://lore.kernel.org/r/20250226-trace-noc-driver-v2-0-8afc6584afc5@quici… Changes in v2: - Modified the format of DT binging file. - Fix compile warnings. - Link to v1: https://lore.kernel.org/r/46643089-b88d-49dc-be05-7bf0bb21f847@quicinc.com --- Yuanfang Zhang (2): dt-bindings: arm: Add device Trace Network On Chip definition coresight: add coresight Trace Network On Chip driver .../bindings/arm/qcom,coresight-tnoc.yaml | 111 ++++++++++ drivers/hwtracing/coresight/Kconfig | 13 ++ drivers/hwtracing/coresight/Makefile | 1 + drivers/hwtracing/coresight/coresight-tnoc.c | 242 +++++++++++++++++++++ 4 files changed, 367 insertions(+) --- base-commit: a2cc6ff5ec8f91bc463fd3b0c26b61166a07eb11 change-id: 20250403-trace-noc-f8286b30408e Best regards, -- Yuanfang Zhang <quic_yuanfang(a)quicinc.com>

3 months, 1 week

[PATCH v6 0/2] coresight: Add Coresight Trace Network On Chip driver

by Yuanfang Zhang

The Trace Network On Chip (TNOC) is an integration hierarchy which is a hardware component that integrates the functionalities of TPDA and funnels. It collects trace from subsystems and transfers it to coresight sink. In addition to the generic TNOC mentioned above, there is also a special type of TNOC called Interconnect TNOC. Unlike the generic TNOC, the Interconnect TNOC doesn't need ATID. Its primary function is to connect the source of subsystems to the Aggregator TNOC. Its driver is different from this patch and will describe it and upstream its driver separately. Signed-off-by: Yuanfang Zhang <quic_yuanfang(a)quicinc.com> --- Changes in v6: - Add a newline after return statements. - Use 'x &= foo' to replace 'x = x & foo'. - Use 'x |= foo' to replace 'x = x | foo'. - Link to v5: https://lore.kernel.org/r/20250512-trace-noc-v5-0-f2ef070baee5@quicinc.com Changes in v5: - update cover-letter to describe the Interconnect TNOC. - Link to v4: https://lore.kernel.org/r/20250415-trace-noc-v4-0-979938fedfd8@quicinc.com Changes in v4: - Fix dt_binding warning. - update mask of trace_noc amba_id. - Modify driver comments. - rename TRACE_NOC_SYN_VAL to TRACE_NOC_SYNC_INTERVAL. - Link to v3: https://lore.kernel.org/r/20250411-trace-noc-v3-0-1f19ddf7699b@quicinc.com Changes in v3: - Remove unnecessary sysfs nodes. - update commit messages. - Use 'writel' instead of 'write_relaxed' when writing to the register for the last time. - Add trace_id ops. - Link to v2: https://lore.kernel.org/r/20250226-trace-noc-driver-v2-0-8afc6584afc5@quici… Changes in v2: - Modified the format of DT binging file. - Fix compile warnings. - Link to v1: https://lore.kernel.org/r/46643089-b88d-49dc-be05-7bf0bb21f847@quicinc.com --- Yuanfang Zhang (2): dt-bindings: arm: Add device Trace Network On Chip definition coresight: add coresight Trace Network On Chip driver .../bindings/arm/qcom,coresight-tnoc.yaml | 111 ++++++++++++ drivers/hwtracing/coresight/Kconfig | 13 ++ drivers/hwtracing/coresight/Makefile | 1 + drivers/hwtracing/coresight/coresight-tnoc.c | 192 +++++++++++++++++++++ drivers/hwtracing/coresight/coresight-tnoc.h | 34 ++++ 5 files changed, 351 insertions(+) --- base-commit: a2cc6ff5ec8f91bc463fd3b0c26b61166a07eb11 change-id: 20250403-trace-noc-f8286b30408e Best regards, -- Yuanfang Zhang <quic_yuanfang(a)quicinc.com>

3 months, 1 week

[PATCH] coresight-tpdm: add trace_id sysfs node

by Yuanfang Zhang

The trace ID of TPMD is the trace ID of the TPDA or TNOC which it is connected to, this change adds trace_id sysfs node to expose this trace id to userspace. Signed-off-by: Yuanfang Zhang <quic_yuanfang(a)quicinc.com> --- drivers/hwtracing/coresight/coresight-tpdm.c | 16 ++++++++++++++++ drivers/hwtracing/coresight/coresight-tpdm.h | 2 ++ 2 files changed, 18 insertions(+) diff --git a/drivers/hwtracing/coresight/coresight-tpdm.c b/drivers/hwtracing/coresight/coresight-tpdm.c index 7214e65097ec9ac69f6c7c9278bcd28d25945c9e..8a5d115157924f39b09f8e3005827d7d64aa376c 100644 --- a/drivers/hwtracing/coresight/coresight-tpdm.c +++ b/drivers/hwtracing/coresight/coresight-tpdm.c @@ -497,6 +497,9 @@ static int tpdm_enable(struct coresight_device *csdev, struct perf_event *event, __tpdm_enable(drvdata); drvdata->enable = true; + + if (path) + drvdata->traceid = path->trace_id; spin_unlock(&drvdata->spinlock); dev_dbg(drvdata->dev, "TPDM tracing enabled\n"); @@ -554,6 +557,7 @@ static void tpdm_disable(struct coresight_device *csdev, __tpdm_disable(drvdata); coresight_set_mode(csdev, CS_MODE_DISABLED); drvdata->enable = false; + drvdata->traceid = 0; spin_unlock(&drvdata->spinlock); dev_dbg(drvdata->dev, "TPDM tracing disabled\n"); @@ -655,9 +659,21 @@ static ssize_t integration_test_store(struct device *dev, } static DEVICE_ATTR_WO(integration_test); +static ssize_t traceid_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + unsigned long val; + struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent); + + val = drvdata->traceid; + return sprintf(buf, "%#lx\n", val); +} +static DEVICE_ATTR_RO(traceid); + static struct attribute *tpdm_attrs[] = { &dev_attr_reset_dataset.attr, &dev_attr_integration_test.attr, + &dev_attr_traceid.attr, NULL, }; diff --git a/drivers/hwtracing/coresight/coresight-tpdm.h b/drivers/hwtracing/coresight/coresight-tpdm.h index b117543897344b689f666f6890cabb59c8ee4869..e12a64f265daa86f1b82fa3640e271e8386f99af 100644 --- a/drivers/hwtracing/coresight/coresight-tpdm.h +++ b/drivers/hwtracing/coresight/coresight-tpdm.h @@ -300,6 +300,7 @@ struct cmb_dataset { * @cmb Specifics associated to TPDM CMB. * @dsb_msr_num Number of MSR supported by DSB TPDM * @cmb_msr_num Number of MSR supported by CMB TPDM + * @traceid: Value of the current ID for this component. */ struct tpdm_drvdata { @@ -313,6 +314,7 @@ struct tpdm_drvdata { struct cmb_dataset *cmb; u32 dsb_msr_num; u32 cmb_msr_num; + u8 traceid; }; /* Enumerate members of various datasets */ --- base-commit: 94305e83eccb3120c921cd3a015cd74731140bac change-id: 20250523-showtraceid-2df91c89be8f Best regards, -- Yuanfang Zhang <quic_yuanfang(a)quicinc.com>

3 months, 2 weeks

Possibility of using Coresight STM - ETR as console for System Control Processor

by Linu Cherian

Hi, We are looking for console options( output only) for the SCP(system control processor)cores in our SOC other than UART and was considering STM as an option. Something like this, SCP ----> STM ---> ETR ---> DDR <--- Linux On the Linux system, some user space scripts can retrieve the ETR trace buffers and move it to a file on a periodic basis. Do you see any basic issue with this approach or have better alternatives to suggest ? Few issues we could think of, 1. SCP wont be able to route the messages to the STM -> ETR path until those are initialized by the Linux user space. Hence any messages until Linux comes up need to be buffered in the SCP local memory and should get flushed once the STM - ETR path is ready. 2. Possible message loss due to buffer overwrite We might have to reserve the ETR trace buffers only to the SCP and keep sufficiently large buffers to reduce the message loss. Assume that reserving a STM port for use by an external core can be achieved from the Linux STM sysfs interface. Thanks, Linu Cherian.

3 months, 3 weeks

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