CoreSight

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Re: [PATCH 2/2] perf: arm_spe: Prefer large AUX mappings

by Leo Yan

On Mon, Aug 10, 2026 at 04:10:48PM +0100, Will Deacon wrote: > On Mon, Aug 10, 2026 at 03:44:42PM +0100, Leo Yan wrote: > > Commit 18049c8cff9c ("perf/aux: Allocate non-contiguous AUX pages by > > default") made the AUX allocator use order-0 pages by default unless a > > PMU explicitly asks for contiguous allocations. > > But that commit specifically calls out SPE as benefitting from > non-contiguous pages: > > "For instance, ARM SPE and TRBE operate with virtual pages, and > Coresight ETR allocates a separate buffer. For these PMUs, > allocating contiguous AUX pages unnecessarily exacerbates memory > fragmentation. This fragmentation can prevent their use on > long-running devices." > > so why doesn't passing PERF_PMU_CAP_AUX_PREFER_LARGE reintroduce the > problems that 18049c8cff9c was trying to solve? The question is how "allocating contiguous AUX pages unnecessarily exacerbates memory fragmentation." The relevant information I could find is [1]: "On Android, we collect ETM data periodically on internal user devices for AutoFDO optimization (for both userspace libraries and the kernel). Allocating a large chunk of contiguous AUX pages (4M for each CPU) periodically is almost unbearable. The kernel may need to kill many processes to fulfill the request. It affects user experience even after using PMU." We might have missed chance to clarify how the fragmentation issue occurs in the first place. Let's say, a phone with 8 CPUs, allocating 4MB per CPU requires 32MB in total, which is a relatively small portion of 4GiB or 8GiB of RAM commonly found in phones. Moreover, once contiguous pages are freed, the buddy allocator can coalesce them again into buddy list. It is not obvious to me that PREFER_LARGE directly causes fragmentation. One case where AUX allocation could exacerbate fragmentation is when the system is already fragmented. If a high-order allocation fails and the allocator falls back to smaller-order blocks, those allocations may consume free blocks scattered across different buddy regions and make subsequent high-order allocations more difficult. If this is the main concern, I'd suggest using a smaller AUX buffer (e.g. 1MB or even 512KB) for TRBE/SPE to reduce memory pressure. Snapshot mode '-S' could also be considered, as it allows the buffer to be allocated once and reused for subsequent recordings by signals. OTOH, using only order-0 pages can significantly increase TTW overhead on the trace path and lead to overflows, we observe this causes huge trace discontinuity. In the end, we need to trace-off the fragmentation concern against the trace discontinuity. Thanks, Leo [1] https://lore.kernel.org/lkml/CALJ9ZPNLgEBxOmDim-vztUknEETwdL-Z2gJ8K9s44TiPg…

10 hours, 49 minutes

[PATCH 0/2] perf/arm: Prefer large AUX mappings for CoreSight and SPE

by Leo Yan

Since the commit: 18049c8cff9 ("perf/aux: Allocate non-contiguous AUX pages by default") it changed the AUX buffer allocator to allocate AUX pages page-by-page (order=0) unless a PMU explicitly asks for contiguous allocations via the capability flag PERF_PMU_CAP_AUX_PREFER_LARGE. The goal was to make AUX allocation more memory-friendly by default, because not all PMUs require physically contiguous AUX pages and large contiguous allocations can contribute to fragmentation on long-running systems. However, Arm SPE and CoreSight/TRBE rely on page-table translation when writing trace data to memory. With page-by-page AUX allocation, a large AUX buffer is mapped with many small mappings. This increases TLB pressure, in practice this can increase trace-buffer latency due to table translation walks (TTW) and contribute to trace discontinuities. This series restores large AUX allocation for Arm CoreSight and SPE by setting PERF_PMU_CAP_AUX_PREFER_LARGE. This is intended to work together with the mm large-mapping series [1]. That series allows vmap() to map physically contiguous pages with larger granules. With this series, perf first tries larger-order AUX allocations, and the vmap() code can then create larger mappings for the contiguous chunks. The fragmentation concern from commit 18049c8cff9c should not block this opt-in. PERF_PMU_CAP_AUX_PREFER_LARGE is a preference, not a hard requirement. The AUX allocator already falls back to smaller orders when a high-order allocation fails. So this series gives Arm trace PMUs the performance benefit when large chunks are available. The comparison below uses a baseline that already includes the mm large-mapping series [1]. "Baseline" means that the mm series is applied but this Arm PMU series is not. "Large AUX" means the same kernel plus this series. Some configurations to mitigate noise during test: 1) The tests were run with CPU10 isolated with the kernel parameter "isolcpus=10". 2) CPU10 was used as the traced CPU, the PMU counter CPU, and the workload CPU. The perf control tasks were pinned to CPU2 so that they did not add extra work on CPU10. 3) Each test was run for 10 iterations, and the tables report the average counter values across those runs. The results show that using larger AUX mappings reduces the TLB pressure. This is mainly visible in the refill events: CoreSight/TRBE shows a large drop in l2d_tlb_refill and a smaller reduction in l1d_tlb_refill, while SPE also reduces l2d_tlb_refill. The dtlb_walk event also drops in both tests, which shows fewer data TLB walks after the AUX buffer can be mapped with larger granules. ETM sparse branch delay (cs_etm, AUX 1GB) taskset -c 2 perf stat -C 10 -e cycles:u,instructions:u,dtlb_walk:u,l1d_tlb:u,l1d_tlb_refill:u,l2d_tlb_refill:u \ -- taskset -c 2 perf record -C 10 -m ,1G -e cs_etm// \ -- taskset -c 10 ./sparse_branch_delay.elf | | Baseline | Large map | | | | Metric | Avg. | Avg. | Delta | Change | |----------------+-----------+-----------+------------+---------| | dtlb_walk | 72.8 | 63.9 | -8.9 | -12.23% | | l1d_tlb | 7,434.4 | 1,982.2 | -5,452.2 | -73.34% | | l1d_tlb_refill | 163.7 | 148.2 | -15.5 | -9.47% | | l2d_tlb_refill | 161,884.9 | 513.1 | -161,371.8 | -99.68% | SPE dd memory copy (arm_spe, AUX 512MB) taskset -c 2 perf stat -C 10 -e cycles:u,instructions:u,dtlb_walk:u,l1d_tlb:u,l1d_tlb_refill:u,l2d_tlb_refill:u \ -- taskset -c 2 perf record -C 10 -m ,512M -e arm_spe_0/ts_enable=1,pa_enable=1,period=64,min_latency=0/ \ -- taskset -c 10 dd if=/dev/zero of=/dev/shm/dd_mem_test bs=1M count=1024 status=progress | | Baseline | Large map | | | | Metric | Avg. | Avg. | Delta | Change | |----------------+-----------+-----------+------------+---------| | dtlb_walk | 1,760.2 | 1,387.9 | -372.3 | -21.15% | | l1d_tlb | 257,312.4 | 251,460.9 | -5,851.5 | -2.27% | | l1d_tlb_refill | 15,921.9 | 15,933.6 | 11.7 | +0.07% | | l2d_tlb_refill | 4,285.0 | 2,796.5 | -1,488.5 | -34.74% | Note that after setting PREFER_LARGE for CoreSight and SPE, the existing AUX trace drivers either prefer large pages or, in the case of Intel BTS/PT, use the stronger AUX_NO_SG constraint. We can refactor this later by either dropping PREFER_LARGE entirely or reversing the flag if a driver needs discrete pages. For now, keep PREFER_LARGE to preserve flexibility in the allocation policy. [1] https://lore.kernel.org/linux-mm/20260715120813.3609949-1-jiangwen6@xiaomi.… Signed-off-by: Leo Yan <leo.yan(a)arm.com> --- Dev Jain (1): coresight: perf: Prefer large AUX mappings Leo Yan (1): perf: arm_spe: Prefer large AUX mappings drivers/hwtracing/coresight/coresight-etm-perf.c | 3 ++- drivers/perf/arm_spe_pmu.c | 3 ++- 2 files changed, 4 insertions(+), 2 deletions(-) --- base-commit: db2ddb87143519e20a95aa36c60b36107b736a58 change-id: 20260717-perf_aux_trace_large_granule-d9b30cc14b5a Best regards, -- Leo Yan <leo.yan(a)arm.com>

13 hours, 46 minutes

[GIT PULL] coresight: Updates for Linux v7.3

by Suzuki K Poulose

Hi Greg Please find this pull request for CoreSight subsystem targeting v7.3. Almost all of them are fixes to the existing code, along with a MAINTAINERS update for HiSilicon PTT driver. Kindly pull Suzuki The following changes since commit 8cdeaa50eae8dad34885515f62559ee83e7e8dda: Linux 7.2-rc2 (2026-07-05 14:44:06 -1000) are available in the Git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/coresight/linux.git tags/coresight-next-v7.3 for you to fetch changes up to 9e3604d7369cfc0110100eb1a0acab1865ee2d18: coresight: etm4x: remove redundant fields in etmv4_save_state (2026-08-07 10:45:11 +0100) ---------------------------------------------------------------- coresight: Updates for Linux v7.3 This is relatively smaller update for CoreSight/hwtracing subsystem updates. - MAINTAINERS update for HiSilicon PCI Trace & Tune drivers - Minor fixes to hisi_ptt driver - Various fixes to the coresight etm4x dirvers Signed-off-by: Suzuki K Poulose <suzuki.poulose(a)arm.com> ---------------------------------------------------------------- Jonathan Cameron (1): MAINTAINERS: Update HiSilicon PCI Trace and Tune maintainer Kuan-Wei Chiu (1): coresight: etm3x: Fix cntr_val_show() to match cntr_val_store() behavior Sanman Pradhan (2): hwtracing: hisi_ptt: Propagate DMA reset timeout in trace_start() hwtracing: hisi_ptt: Remove unnecessary trace buffer zeroing in trace_start() Yeoreum Yun (5): coresight: etm4x: fix wrong check of etm4x_sspcicrn_present() coresight: etm4x: fix underflow for usage of (nrseqstate - 1) coresight: etm4x: fix leaked trace id coresight: etm4x: missing cscfg_csdev_disable_active_config() in perf enable coresight: etm4x: remove redundant fields in etmv4_save_state MAINTAINERS | 3 +- .../hwtracing/coresight/coresight-etm3x-sysfs.c | 15 ++---- drivers/hwtracing/coresight/coresight-etm4x-cfg.c | 2 +- drivers/hwtracing/coresight/coresight-etm4x-core.c | 59 +++++++++++++--------- .../hwtracing/coresight/coresight-etm4x-sysfs.c | 6 ++- drivers/hwtracing/coresight/coresight-etm4x.h | 12 ++--- drivers/hwtracing/ptt/hisi_ptt.c | 25 ++++----- 7 files changed, 63 insertions(+), 59 deletions(-)

3 days, 5 hours

[PATCH v2] coresight: trbe: Hide enable_sink sysfs file

by James Clark

TRBE doesn't support sysfs mode, but the enable_sink file can still be successfully written to enable the device, and only attempting to enable the source would later fail. Avoid misleading users by adding a flag that devices can use to hide either the enable_sink or enable_source files, and set it for TRBE. Don't set it for ETE as it's possible that ETE could appear on the legacy bus and work with sysfs, and writing to enable_source already reports EINVAL if the device doesn't support sysfs mode. Signed-off-by: James Clark <james.clark(a)linaro.org> --- Changes in v2: - Re-use CORESIGHT_DESC flags in csdev instead of converting to bool. - Hide all remaining attrs after label instead of only source and sink attrs as there aren't any others anyway (Leo). - Link to v1: https://lore.kernel.org/r/20260507-james-cs-hide-trbe-enable-v1-1-b4e40439f… --- drivers/hwtracing/coresight/coresight-core.c | 1 + drivers/hwtracing/coresight/coresight-sysfs.c | 15 +++++++++------ drivers/hwtracing/coresight/coresight-trbe.c | 7 +++++++ include/linux/coresight.h | 4 ++++ 4 files changed, 21 insertions(+), 6 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-core.c b/drivers/hwtracing/coresight/coresight-core.c index f7b1308a759c..a0c098980096 100644 --- a/drivers/hwtracing/coresight/coresight-core.c +++ b/drivers/hwtracing/coresight/coresight-core.c @@ -1543,6 +1543,7 @@ coresight_init_device(struct coresight_desc *desc) csdev->ops = desc->ops; csdev->access = desc->access; csdev->orphan = true; + csdev->flags = desc->flags; if (desc->flags & CORESIGHT_DESC_CPU_BOUND) { csdev->cpu = desc->cpu; diff --git a/drivers/hwtracing/coresight/coresight-sysfs.c b/drivers/hwtracing/coresight/coresight-sysfs.c index 4b010f8bc4c0..75000fe64fda 100644 --- a/drivers/hwtracing/coresight/coresight-sysfs.c +++ b/drivers/hwtracing/coresight/coresight-sysfs.c @@ -346,16 +346,19 @@ static ssize_t label_show(struct device *dev, } static DEVICE_ATTR_RO(label); -static umode_t label_is_visible(struct kobject *kobj, - struct attribute *attr, int n) +static umode_t coresight_attr_is_visible(struct kobject *kobj, + struct attribute *attr, int n) { struct device *dev = kobj_to_dev(kobj); + struct coresight_device *csdev = to_coresight_device(dev); if (attr == &dev_attr_label.attr) { if (fwnode_property_present(dev_fwnode(dev), "label")) return attr->mode; else return 0; + } else if (csdev->flags & CORESIGHT_DESC_NO_SYSFS_MODE) { + return 0; } return attr->mode; @@ -369,7 +372,7 @@ static struct attribute *coresight_sink_attrs[] = { static struct attribute_group coresight_sink_group = { .attrs = coresight_sink_attrs, - .is_visible = label_is_visible, + .is_visible = coresight_attr_is_visible, }; __ATTRIBUTE_GROUPS(coresight_sink); @@ -381,7 +384,7 @@ static struct attribute *coresight_source_attrs[] = { static struct attribute_group coresight_source_group = { .attrs = coresight_source_attrs, - .is_visible = label_is_visible, + .is_visible = coresight_attr_is_visible, }; __ATTRIBUTE_GROUPS(coresight_source); @@ -392,7 +395,7 @@ static struct attribute *coresight_link_attrs[] = { static struct attribute_group coresight_link_group = { .attrs = coresight_link_attrs, - .is_visible = label_is_visible, + .is_visible = coresight_attr_is_visible, }; __ATTRIBUTE_GROUPS(coresight_link); @@ -403,7 +406,7 @@ static struct attribute *coresight_helper_attrs[] = { static struct attribute_group coresight_helper_group = { .attrs = coresight_helper_attrs, - .is_visible = label_is_visible, + .is_visible = coresight_attr_is_visible, }; __ATTRIBUTE_GROUPS(coresight_helper); diff --git a/drivers/hwtracing/coresight/coresight-trbe.c b/drivers/hwtracing/coresight/coresight-trbe.c index c7cbca45f2de..eca8e13a9744 100644 --- a/drivers/hwtracing/coresight/coresight-trbe.c +++ b/drivers/hwtracing/coresight/coresight-trbe.c @@ -1348,6 +1348,13 @@ static void arm_trbe_register_coresight_cpu(struct trbe_drvdata *drvdata, int cp desc.dev = dev; desc.cpu = cpu; desc.flags = CORESIGHT_DESC_CPU_BOUND; + /* + * ETE isn't connected to TRBE with a link like other Coresight devices + * and the TRBE driver has been written to always assume Perf mode, so + * Prevent sysfs from being used. + */ + desc.flags |= CORESIGHT_DESC_NO_SYSFS_MODE; + trbe_csdev = coresight_register(&desc); if (IS_ERR(trbe_csdev)) goto cpu_clear; diff --git a/include/linux/coresight.h b/include/linux/coresight.h index add0579cad88..6cd1d01b843b 100644 --- a/include/linux/coresight.h +++ b/include/linux/coresight.h @@ -142,6 +142,8 @@ struct csdev_access { }) #define CORESIGHT_DESC_CPU_BOUND BIT(0) +/* Device can't be activated from sysfs, only via Perf. */ +#define CORESIGHT_DESC_NO_SYSFS_MODE BIT(1) /** * struct coresight_desc - description of a component required from drivers @@ -310,6 +312,8 @@ struct coresight_device { struct list_head config_csdev_list; raw_spinlock_t cscfg_csdev_lock; void *active_cscfg_ctxt; + /* CORESIGHT_DESC_[x] flags */ + u32 flags; }; /* --- base-commit: c8eb4a8dd259fb2b215da32764fa8c6c76519896 change-id: 20260506-james-cs-hide-trbe-enable-3c8d784e72d8 Best regards, -- James Clark <james.clark(a)linaro.org>

3 days, 18 hours

[PATCH v9 00/13] fix several inconsistencies with sysfs configuration in etmX

by Yeoreum Yun

The current ETMx configuration via sysfs can lead to the following inconsistencies: - If a configuration is modified via sysfs while a perf session is active, the running configuration may differ between before a sched-out and after a subsequent sched-in. - If a perf session and sysfs session tries to enable concurrently, configuration from configfs could be corrupted (etm4). - There is chance to corrupt drvdata->config if perf session tries to enabled among handling cscfg_csdev_disable_active_config() in etm4_disable_sysfs() (etm4). To resolve these inconsistencies, the configuration should be separated into: - active_config, which is applied configuration for the current session - config, which stores the settings configured via sysfs. and apply configuration from configfs after taking a mode. Also, This patch set includes some small fixes: - missing trace id release in etm4x. - underflow issue for nrseqstate. - wrong check in etm4x_sspcicrn_present(). - missing call of cscfg_csdev_disable_active_config() This patch based on coresight tree's next Patch History ============= from v8 to v9: - add feat_csdev_lock guard interface. - set feat_csdev->drv_spinlock as NULL for etmv4_drvdata. - https://lore.kernel.org/all/20260629090007.1718746-1-yeoreum.yun@arm.com/ from v7 to v8: - accept @Leo Yan' suggestion to handle error. - small minor fixes following @Suzuki' suggestion. - https://lore.kernel.org/all/20260519154812.254884-1-yeoreum.yun@arm.com/ from v6 to v7: - rebase on coresight/next - add ETM_MAX_SEQ_TRANSITIONS define - remove redundant patch relavent cpu-hotplug as coresight-pm patch merged. - https://lore.kernel.org/all/20260422132203.977549-1-yeoreum.yun@arm.com/ from v5 to v6: - fix missing of calling cscfg_csdev_disable_active_config() - add rb & fixes tags. - add ss_status field in etm4x_drvdata to expose STATUS and PENDING bits. - https://lore.kernel.org/all/20260415165528.3369607-1-yeoreum.yun@arm.com/ from v4 to v5: - add rb-tag. - fix underflow issue for nrseqstate. - fix wrong check in etm4_sspcicrn_present(). - remove redundant fields on etmv4_save_state. - rename caps->ss_status to ss_cmp. - fix wrong location of etm4_release_trace_id. - https://lore.kernel.org/all/20260413142003.3549310-1-yeoreum.yun@arm.com/ from v3 to v4: - change etm_drvdata->spinlock type to raw_spin_lock_t - remove redundant call etmX_enable_hw() with starting_cpu() callsback. - fix missing trace id release. - add missing docs. - https://lore.kernel.org/all/20260412175506.412301-1-yeoreum.yun@arm.com/ from v2 to v3: - fix build error for etm3x. - fix checkpatch warning. - https://lore.kernel.org/all/20260410074310.2693385-1-yeoreum.yun@arm.com/ from v1 to v2 - rebased to v7.0-rc7. - introduce etmX_caps structure to save etmX's capabilities. - remove ss_status from etmv4_config. - modify active_config after taking a mode (perf/sysfs). - https://lore.kernel.org/all/20260317181705.2456271-1-yeoreum.yun@arm.com/ Yeoreum Yun (13): coresight: etm4x: fix wrong check of etm4x_sspcicrn_present() coresight: etm4x: fix underflow for usage of (nrseqstate - 1) coresight: etm4x: fix leaked trace id coresight: etm4x: fix inconsistencies with sysfs configuration coresight: etm4x: missing cscfg_csdev_disable_active_config() in perf enable coresight: etm3x: fix inconsistencies with sysfs configuration coresight: etm3x: change drvdata->spinlock type to raw_spin_lock_t coresight: etm3x: remove redundant cpu online check on etm_enable_sysfs() coresight: etm4x: introduce struct etm4_caps coresight: etm4x: exclude ss_status from drvdata->config coresight: etm4x: remove s_ex_level from config coresight: etm4x: remove redundant fields in etmv4_save_state coresight: etm3x: introduce struct etm_caps .../hwtracing/coresight/coresight-config.c | 18 +- .../hwtracing/coresight/coresight-config.h | 26 + drivers/hwtracing/coresight/coresight-etm.h | 48 +- .../coresight/coresight-etm3x-core.c | 96 ++-- .../coresight/coresight-etm3x-sysfs.c | 159 +++--- .../hwtracing/coresight/coresight-etm4x-cfg.c | 16 +- .../coresight/coresight-etm4x-core.c | 454 ++++++++++-------- .../coresight/coresight-etm4x-sysfs.c | 204 ++++---- drivers/hwtracing/coresight/coresight-etm4x.h | 204 ++++---- 9 files changed, 682 insertions(+), 543 deletions(-) base-commit: 98495b5a4d77dd22e106f462b76e1093a55b29a7 -- LEVI:{C3F47F37-75D8-414A-A8BA-3980EC8A46D7}

4 days, 14 hours

Re: [PATCH v1] coresight: Check runtime PM resume result

by Anshuman Khandual

On 03/08/26 4:55 AM, Yuho Choi wrote: > coresight_get_ref() ignores the return value of pm_runtime_get_sync() > and reports success even when runtime resume fails. A path is then built > and the CoreSight device may be accessed while it remains powered off. > > Use pm_runtime_resume_and_get() so a failed resume is reported and its > runtime PM usage reference is rolled back. Drop the module and device > references acquired before the resume attempt when it fails. > > Fixes: 5da5325fa856 ("coresight: moving PM runtime operations to core framework") > Signed-off-by: Yuho Choi <dbgh9129(a)gmail.com> > --- Should 'Fixes:' be tagging the following commit - which had introduced coresight_get_ref() unconditionally calling pm_runtime_get_sync() ? 32b0707a4182 ("coresight: Add try_get_module() in coresight_grab_device()") > drivers/hwtracing/coresight/coresight-core.c | 6 +++++- > 1 file changed, 5 insertions(+), 1 deletion(-) > > diff --git a/drivers/hwtracing/coresight/coresight-core.c b/drivers/hwtracing/coresight/coresight-core.c > index 6d65c43d574f..77d05b360484 100644 > --- a/drivers/hwtracing/coresight/coresight-core.c > +++ b/drivers/hwtracing/coresight/coresight-core.c > @@ -843,7 +843,11 @@ static bool coresight_get_ref(struct coresight_device *csdev) > goto err_module; > > /* Make sure the device is powered on */ > - pm_runtime_get_sync(parent); > + if (pm_runtime_resume_and_get(parent) < 0) { > + module_put(drv->owner); > + goto err_module; > + } > + > return true; > > err_module:

1 week

[PATCH v3 0/8] coresight: Prevent per-thread events from sharing a sink

by James Clark

Concurrent per-thread events results in a WARN on N1SDP which leads to the realization that per-thread events shouldn't have been sharing sinks in the first place. This slips through because different per-thread events will have the same PID if owned by the same process, and we only check the PID and nothing else. That results in unexpected WARNs because it looks like we assumed it couldn't happen (although exclusive PMU rules allow it). But even if it was supported it would result in trace from the wrong thread in another event's per-thread buffer, so we should disallow it. Fix it everywhere the same PID checking logic was copy pasted. Then the PIDs can be dropped from a few structs as they are now unused. Signed-off-by: James Clark <james.clark(a)linaro.org> --- Changes in v3: - Storing and accessing event owners at runtime causes problems due to various scenarios of: events (and sibling events) exiting, children inheriting event FDs, PID reuse, CPU affine events that also have a target process set but different inherit settings. Fix it by creating a session ID in etm_setup_aux() and holding the references in it for the duration of the whole session. (Leo) - Make the ETR buffer allocator consistent with sink sharing rules by not doing numeric PID comparisons there either. - Fix up some Sashiko reports that it sees after interacting with cscfg and taking extra references to tasks and PIDs. - Link to v2: https://lore.kernel.org/r/20260709-james-cs-multiple-per-threads-v2-0-10ac7… Changes in v2: - Fix inherited events by following event->parent - Link to v1: https://lore.kernel.org/r/20260709-james-cs-multiple-per-threads-v1-0-d384e… --- James Clark (8): coresight: tmc-etr: Don't stop Perf cleanup for active sysfs reads coresight: configfs: Don't assume active until cscfg_mgr is set coresight: etm-perf: Flush workqueue before unloading module coresight: tmc-etr: Prevent per-thread events from sharing a sink coresight: tmc-etr: Use session ID for buffer ownership coresight: tmc-etf: Prevent per-thread events from sharing a sink coresight: etb10: Prevent per-thread events from sharing a sink coresight: ultrasoc-smb: Prevent per-thread events from sharing a sink drivers/hwtracing/coresight/coresight-core.c | 28 +-- drivers/hwtracing/coresight/coresight-etb10.c | 33 ++-- drivers/hwtracing/coresight/coresight-etm-perf.c | 79 ++++++++- drivers/hwtracing/coresight/coresight-etm-perf.h | 15 ++ drivers/hwtracing/coresight/coresight-priv.h | 2 - drivers/hwtracing/coresight/coresight-syscfg.c | 6 +- drivers/hwtracing/coresight/coresight-tmc-core.c | 6 +- drivers/hwtracing/coresight/coresight-tmc-etf.c | 44 ++--- drivers/hwtracing/coresight/coresight-tmc-etr.c | 207 +++++++++++++---------- drivers/hwtracing/coresight/coresight-tmc.h | 30 ++-- drivers/hwtracing/coresight/coresight-trbe.c | 3 +- drivers/hwtracing/coresight/ultrasoc-smb.c | 25 +-- drivers/hwtracing/coresight/ultrasoc-smb.h | 6 +- include/linux/coresight.h | 5 +- 14 files changed, 294 insertions(+), 195 deletions(-) --- base-commit: 98495b5a4d77dd22e106f462b76e1093a55b29a7 change-id: 20260708-james-cs-multiple-per-threads-ed1d25ed1734 Best regards, -- James Clark <james.clark(a)linaro.org>

1 week, 6 days

Re: [PATCH v3] coresight: coresight.h: add '*' to kernel-doc lines

by Anshuman Khandual

On 20/07/26 3:54 AM, Randy Dunlap wrote: > kernel-doc reports 2 (kernel-doc) lines in coresight.h that don't have > a beginning '*' in them, so fix these lines. > > Also convert struct coresight_trace_id_map to kernel-doc format to > remove another warning. > > Warning: include/linux/coresight.h:173 bad line: > connected to @src_port. NULL until the device is created > Warning: include/linux/coresight.h:177 bad line: > needs to be filtered. > Warning: include/linux/coresight.h:236 This comment starts with '/**', > but isn't a kernel-doc comment. > > Fixes: ec9903d6cc34 ("coresight: Add support for trace filtering by source") > Fixes: d49c9cf15f89 ("coresight: Rename connection members to make the direction explicit") > Signed-off-by: Randy Dunlap <rdunlap(a)infradead.org> > --- > v2: rebase & resend > v3: rebase & resend > > Cc: James Clark <james.clark(a)arm.com> > Cc: Tao Zhang <quic_taozha(a)quicinc.com> > Cc: Suzuki K Poulose <suzuki.poulose(a)arm.com> > Cc: coresight(a)lists.linaro.org > Cc: Danilo Krummrich <dakr(a)kernel.org> > Cc: Mike Leach <mike.leach(a)arm.com> > Cc: Leo Yan <leo.yan(a)arm.com> > Cc: linux-arm-kernel(a)lists.infradead.org > --- > include/linux/coresight.h | 6 +++--- > 1 file changed, 3 insertions(+), 3 deletions(-) > > --- linux-next-20260717.orig/include/linux/coresight.h > +++ linux-next-20260717/include/linux/coresight.h > @@ -177,11 +177,11 @@ struct coresight_desc { > * @dest_port: destination's input port number @src_port is connected to. > * @dest_fwnode: destination component's fwnode handle. > * @dest_dev: a @coresight_device representation of the component > - connected to @src_port. NULL until the device is created > + * connected to @src_port. NULL until the device is created > * @link: Representation of the connection as a sysfs link. > * @filter_src_fwnode: filter source component's fwnode handle. > * @filter_src_dev: a @coresight_device representation of the component that > - needs to be filtered. > + * needs to be filtered. > * > * The full connection structure looks like this, where in_conns store > * references to same connection as the source device's out_conns. > @@ -234,7 +234,7 @@ struct coresight_sysfs_link { > #define CORESIGHT_TRACE_IDS_MAX 128 > > /** > - * Trace ID map. > + * struct coresight_trace_id_map - Trace ID map. > * > * @used_ids: Bitmap to register available (bit = 0) and in use (bit = 1) IDs. > * Initialised so that the reserved IDs are permanently marked as > But still there are more warnings left in the documentation file even after the patch applied. Should they be fixed as well ? ./scripts/kernel-doc -none include/linux/coresight.h Warning: include/linux/coresight.h:216 struct member 'src_dev' not described in 'coresight_connection' Warning: include/linux/coresight.h:216 struct member 'src_refcnt' not described in 'coresight_connection' Warning: include/linux/coresight.h:216 struct member 'dest_refcnt' not described in 'coresight_connection' Warning: include/linux/coresight.h:248 struct member 'cpu_map' not described in 'coresight_trace_id_map' Warning: include/linux/coresight.h:248 struct member 'lock' not described in 'coresight_trace_id_map' Warning: include/linux/coresight.h:312 struct member 'perf_sink_id_map' not described in 'coresight_device' Warning: include/linux/coresight.h:216 struct member 'src_dev' not described in 'coresight_connection' Warning: include/linux/coresight.h:216 struct member 'src_refcnt' not described in 'coresight_connection' Warning: include/linux/coresight.h:216 struct member 'dest_refcnt' not described in 'coresight_connection' Warning: include/linux/coresight.h:248 struct member 'cpu_map' not described in 'coresight_trace_id_map' Warning: include/linux/coresight.h:248 struct member 'lock' not described in 'coresight_trace_id_map' Warning: include/linux/coresight.h:312 struct member 'perf_sink_id_map' not described in 'coresight_device'

1 week, 6 days

[PATCH v8 00/13] fix several inconsistencies with sysfs configuration in etmX

by Yeoreum Yun

The current ETMx configuration via sysfs can lead to the following inconsistencies: - If a configuration is modified via sysfs while a perf session is active, the running configuration may differ between before a sched-out and after a subsequent sched-in. - If a perf session and sysfs session tries to enable concurrently, configuration from configfs could be corrupted (etm4). - There is chance to corrupt drvdata->config if perf session tries to enabled among handling cscfg_csdev_disable_active_config() in etm4_disable_sysfs() (etm4). To resolve these inconsistencies, the configuration should be separated into: - active_config, which is applied configuration for the current session - config, which stores the settings configured via sysfs. and apply configuration from configfs after taking a mode. Also, This patch set includes some small fixes: - missing trace id release in etm4x. - underflow issue for nrseqstate. - wrong check in etm4x_sspcicrn_present(). - missing call of cscfg_csdev_disable_active_config() This patch based on coresight tree's next Patch History ============= from v7 to v8: - accept @Leo Yan' suggestion to handle error. - small minor fixes following @Suzuki' suggestion. - https://lore.kernel.org/all/20260519154812.254884-1-yeoreum.yun@arm.com/ from v6 to v7: - rebase on coresight/next - add ETM_MAX_SEQ_TRANSITIONS define - remove redundant patch relavent cpu-hotplug as coresight-pm patch merged. - https://lore.kernel.org/all/20260422132203.977549-1-yeoreum.yun@arm.com/ from v5 to v6: - fix missing of calling cscfg_csdev_disable_active_config() - add rb & fixes tags. - add ss_status field in etm4x_drvdata to expose STATUS and PENDING bits. - https://lore.kernel.org/all/20260415165528.3369607-1-yeoreum.yun@arm.com/ from v4 to v5: - add rb-tag. - fix underflow issue for nrseqstate. - fix wrong check in etm4_sspcicrn_present(). - remove redundant fields on etmv4_save_state. - rename caps->ss_status to ss_cmp. - fix wrong location of etm4_release_trace_id. - https://lore.kernel.org/all/20260413142003.3549310-1-yeoreum.yun@arm.com/ from v3 to v4: - change etm_drvdata->spinlock type to raw_spin_lock_t - remove redundant call etmX_enable_hw() with starting_cpu() callsback. - fix missing trace id release. - add missing docs. - https://lore.kernel.org/all/20260412175506.412301-1-yeoreum.yun@arm.com/ from v2 to v3: - fix build error for etm3x. - fix checkpatch warning. - https://lore.kernel.org/all/20260410074310.2693385-1-yeoreum.yun@arm.com/ from v1 to v2 - rebased to v7.0-rc7. - introduce etmX_caps structure to save etmX's capabilities. - remove ss_status from etmv4_config. - modify active_config after taking a mode (perf/sysfs). - https://lore.kernel.org/all/20260317181705.2456271-1-yeoreum.yun@arm.com/ Yeoreum Yun (13): coresight: etm4x: fix wrong check of etm4x_sspcicrn_present() coresight: etm4x: fix underflow for usage of (nrseqstate - 1) coresight: etm4x: introduce struct etm4_caps coresight: etm4x: exclude ss_status from drvdata->config coresight: etm4x: remove s_ex_level from config coresight: etm4x: remove redundant fields in etmv4_save_state coresight: etm4x: fix leaked trace id coresight: etm4x: fix inconsistencies with sysfs configuration coresight: etm4x: missing cscfg_csdev_disable_active_config() in perf enable coresight: etm3x: change drvdata->spinlock type to raw_spin_lock_t coresight: etm3x: introduce struct etm_caps coresight: etm3x: fix inconsistencies with sysfs configuration coresight: etm3x: remove redundant cpu online check on etm_enable_sysfs() drivers/hwtracing/coresight/coresight-etm.h | 46 +- .../coresight/coresight-etm3x-core.c | 96 ++-- .../coresight/coresight-etm3x-sysfs.c | 159 +++--- .../hwtracing/coresight/coresight-etm4x-cfg.c | 5 +- .../coresight/coresight-etm4x-core.c | 454 ++++++++++-------- .../coresight/coresight-etm4x-sysfs.c | 204 ++++---- drivers/hwtracing/coresight/coresight-etm4x.h | 202 ++++---- 7 files changed, 639 insertions(+), 527 deletions(-) -- LEVI:{C3F47F37-75D8-414A-A8BA-3980EC8A46D7}

2 weeks, 5 days

Re: [PATCH v3] coresight: Fix scheduling while atomic in coresight_cpu_pm_notify()

by Leo Yan

On Fri, Jul 17, 2026 at 12:41:54AM +0300, Mohamed Ayman wrote: [...] > static struct coresight_path *coresight_cpu_get_active_path(enum cs_mode mode) > { > struct coresight_device *source; > - bool is_active = false; > + struct coresight_path *path = NULL; > > - source = coresight_get_percpu_source_ref(smp_processor_id()); > - if (!source) > - return NULL; > - > - if (coresight_get_mode(source) & mode) > - is_active = true; > + guard(raw_spinlock_irqsave)(&coresight_dev_lock); > > - coresight_put_percpu_source_ref(source); > + source = per_cpu(csdev_source, smp_processor_id()); > + if (source && (coresight_get_mode(source) & mode)) > + path = source->path; > > - /* > - * It is expected to run in atomic context or with the CPU lock held for > - * sysfs mode, so it cannot be preempted to disable the path. Here > - * returns the active path pointer without concern that its state may > - * change. Since the build path has taken a reference on the component, > - * the path can be safely used by the caller. > - */ Please keep the comment, as it helps explain why the path pointer can be returned and safely used by the caller. > - return is_active ? source->path : NULL; > + return path; With above update: Reviewed-by: Leo Yan <leo.yan(a)arm.com> Just a thought: we could view this in two stages. 1) The first stage is building the CoreSight path, where we need to ensure the involved modules remain bound while the path is being established. 2) Once the path has been built and the device mode is enabled, we enter the runtime stage. From that point on, observing the device mode as enabled guarantees that the associated data structures can be accessed safely. I would leave this to maintainers for a call in case any concerns on lifetime management.

2 weeks, 6 days

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