CoreSight

coresight@lists.linaro.org

9 participants
2378 discussions

[PATCH] coresight-tpdm: add trace_id sysfs node

by Yuanfang Zhang

The trace ID of TPMD is the trace ID of the TPDA or TNOC which it is connected to, this change adds trace_id sysfs node to expose this trace id to userspace. Signed-off-by: Yuanfang Zhang <quic_yuanfang(a)quicinc.com> --- drivers/hwtracing/coresight/coresight-tpdm.c | 16 ++++++++++++++++ drivers/hwtracing/coresight/coresight-tpdm.h | 2 ++ 2 files changed, 18 insertions(+) diff --git a/drivers/hwtracing/coresight/coresight-tpdm.c b/drivers/hwtracing/coresight/coresight-tpdm.c index 7214e65097ec9ac69f6c7c9278bcd28d25945c9e..8a5d115157924f39b09f8e3005827d7d64aa376c 100644 --- a/drivers/hwtracing/coresight/coresight-tpdm.c +++ b/drivers/hwtracing/coresight/coresight-tpdm.c @@ -497,6 +497,9 @@ static int tpdm_enable(struct coresight_device *csdev, struct perf_event *event, __tpdm_enable(drvdata); drvdata->enable = true; + + if (path) + drvdata->traceid = path->trace_id; spin_unlock(&drvdata->spinlock); dev_dbg(drvdata->dev, "TPDM tracing enabled\n"); @@ -554,6 +557,7 @@ static void tpdm_disable(struct coresight_device *csdev, __tpdm_disable(drvdata); coresight_set_mode(csdev, CS_MODE_DISABLED); drvdata->enable = false; + drvdata->traceid = 0; spin_unlock(&drvdata->spinlock); dev_dbg(drvdata->dev, "TPDM tracing disabled\n"); @@ -655,9 +659,21 @@ static ssize_t integration_test_store(struct device *dev, } static DEVICE_ATTR_WO(integration_test); +static ssize_t traceid_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + unsigned long val; + struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent); + + val = drvdata->traceid; + return sprintf(buf, "%#lx\n", val); +} +static DEVICE_ATTR_RO(traceid); + static struct attribute *tpdm_attrs[] = { &dev_attr_reset_dataset.attr, &dev_attr_integration_test.attr, + &dev_attr_traceid.attr, NULL, }; diff --git a/drivers/hwtracing/coresight/coresight-tpdm.h b/drivers/hwtracing/coresight/coresight-tpdm.h index b117543897344b689f666f6890cabb59c8ee4869..e12a64f265daa86f1b82fa3640e271e8386f99af 100644 --- a/drivers/hwtracing/coresight/coresight-tpdm.h +++ b/drivers/hwtracing/coresight/coresight-tpdm.h @@ -300,6 +300,7 @@ struct cmb_dataset { * @cmb Specifics associated to TPDM CMB. * @dsb_msr_num Number of MSR supported by DSB TPDM * @cmb_msr_num Number of MSR supported by CMB TPDM + * @traceid: Value of the current ID for this component. */ struct tpdm_drvdata { @@ -313,6 +314,7 @@ struct tpdm_drvdata { struct cmb_dataset *cmb; u32 dsb_msr_num; u32 cmb_msr_num; + u8 traceid; }; /* Enumerate members of various datasets */ --- base-commit: 94305e83eccb3120c921cd3a015cd74731140bac change-id: 20250523-showtraceid-2df91c89be8f Best regards, -- Yuanfang Zhang <quic_yuanfang(a)quicinc.com>

4 weeks, 1 day

Possibility of using Coresight STM - ETR as console for System Control Processor

by Linu Cherian

Hi, We are looking for console options( output only) for the SCP(system control processor)cores in our SOC other than UART and was considering STM as an option. Something like this, SCP ----> STM ---> ETR ---> DDR <--- Linux On the Linux system, some user space scripts can retrieve the ETR trace buffers and move it to a file on a periodic basis. Do you see any basic issue with this approach or have better alternatives to suggest ? Few issues we could think of, 1. SCP wont be able to route the messages to the STM -> ETR path until those are initialized by the Linux user space. Hence any messages until Linux comes up need to be buffered in the SCP local memory and should get flushed once the STM - ETR path is ready. 2. Possible message loss due to buffer overwrite We might have to reserve the ETR trace buffers only to the SCP and keep sufficiently large buffers to reduce the message loss. Assume that reserving a STM port for use by an external core can be achieved from the Linux STM sysfs interface. Thanks, Linu Cherian.

1 month

[PATCH v7 0/2] coresight: Add Coresight Trace Network On Chip driver

by Yuanfang Zhang

The Trace Network On Chip (TNOC) is an integration hierarchy which is a hardware component that integrates the functionalities of TPDA and funnels. It collects trace from subsystems and transfers it to coresight sink. In addition to the generic TNOC mentioned above, there is also a special type of TNOC called Interconnect TNOC. Unlike the generic TNOC, the Interconnect TNOC doesn't need ATID. Its primary function is to connect the source of subsystems to the Aggregator TNOC. Its driver is different from this patch and will describe it and upstream its driver separately. Signed-off-by: Yuanfang Zhang <quic_yuanfang(a)quicinc.com> --- Changes in v7: - Move the content in header file into coresight-tnoc.c. - Use scoped_guard() to replace spin_lock(). - Invoke coresight_trace_id_put_system_id() for registration failure. - Link to v6: https://lore.kernel.org/r/20250522-trace-noc-v6-0-f5a9bcae90ee@quicinc.com Changes in v6: - Add a newline after return statements. - Use 'x &= foo' to replace 'x = x & foo'. - Use 'x |= foo' to replace 'x = x | foo'. - Link to v5: https://lore.kernel.org/r/20250512-trace-noc-v5-0-f2ef070baee5@quicinc.com Changes in v5: - update cover-letter to describe the Interconnect TNOC. - Link to v4: https://lore.kernel.org/r/20250415-trace-noc-v4-0-979938fedfd8@quicinc.com Changes in v4: - Fix dt_binding warning. - update mask of trace_noc amba_id. - Modify driver comments. - rename TRACE_NOC_SYN_VAL to TRACE_NOC_SYNC_INTERVAL. - Link to v3: https://lore.kernel.org/r/20250411-trace-noc-v3-0-1f19ddf7699b@quicinc.com Changes in v3: - Remove unnecessary sysfs nodes. - update commit messages. - Use 'writel' instead of 'write_relaxed' when writing to the register for the last time. - Add trace_id ops. - Link to v2: https://lore.kernel.org/r/20250226-trace-noc-driver-v2-0-8afc6584afc5@quici… Changes in v2: - Modified the format of DT binging file. - Fix compile warnings. - Link to v1: https://lore.kernel.org/r/46643089-b88d-49dc-be05-7bf0bb21f847@quicinc.com --- Yuanfang Zhang (2): dt-bindings: arm: Add device Trace Network On Chip definition coresight: add coresight Trace Network On Chip driver .../bindings/arm/qcom,coresight-tnoc.yaml | 111 +++++++++++ drivers/hwtracing/coresight/Kconfig | 13 ++ drivers/hwtracing/coresight/Makefile | 1 + drivers/hwtracing/coresight/coresight-tnoc.c | 216 +++++++++++++++++++++ 4 files changed, 341 insertions(+) --- base-commit: a2cc6ff5ec8f91bc463fd3b0c26b61166a07eb11 change-id: 20250403-trace-noc-f8286b30408e Best regards, -- Yuanfang Zhang <quic_yuanfang(a)quicinc.com>

1 month

[GIT PULL] coresight: updates for Linux v6.16

by Suzuki K Poulose

Hi Greg, Please find the CoreSight self-hosted tracing subsystem updates for Linux v6.16. Kindly pull, Suzuki --- The following changes since commit 9c32cda43eb78f78c73aee4aa344b777714e259b: Linux 6.15-rc3 (2025-04-20 13:43:47 -0700) are available in the Git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/coresight/linux.git tags/coresight-next-v6.16 for you to fetch changes up to 408c97c4a5e0b634dcd15bf8b8808b382e888164: coresight: prevent deactivate active config while enabling the config (2025-05-20 16:38:54 +0100) ---------------------------------------------------------------- coresight: updates for Linux v6.16 CoreSight self-hosted trace driver subsystem updates for Linux v6.16 includes: - Clear CLAIM tags on device probe if self-hosted tags are set. - Support for perf AUX pause/resume for CoreSight ETM PMU driver, with trace collection at pause. - Miscellaneous fixes for the subsystem Signed-off-by: Suzuki K Poulose <suzuki.poulose(a)arm.com> ---------------------------------------------------------------- Andy Shevchenko (1): coresight: cti: Replace inclusion by struct fwnode_handle forward declaration Dmitry Baryshkov (1): dt-bindings: arm: arm,coresight-static-replicator: add optional clocks James Clark (8): coresight: Convert tag clear function to take a struct csdev_access coresight: Only check bottom two claim bits coresight: Add claim tag warnings and debug messages coresight: etm3x: Convert raw base pointer to struct coresight access coresight: Clear self hosted claim tag on probe coresight: Remove inlines from static function definitions coresight: Remove extern from function declarations coresight: Add a KUnit test for coresight_find_default_sink() Junhao He (1): coresight: Fixes device's owner field for registered using coresight_init_driver() Leo Yan (9): coresight: replicator: Fix panic for clearing claim tag coresight: etm4x: Extract the trace unit controlling coresight: Introduce pause and resume APIs for source coresight: etm4x: Hook pause and resume callbacks coresight: perf: Support AUX trace pause and resume coresight: tmc: Re-enable sink after buffer update coresight: perf: Update buffer on AUX pause Documentation: coresight: Document AUX pause and resume coresight: etm4x: Fix timestamp bit field handling Mao Jinlong (2): coresight: Disable MMIO logging for coresight stm driver coresight: tmc: fix failure to disable/enable ETF after reading Yabin Cui (2): coresight: catu: Introduce refcount and spinlock for enabling/disabling coresight: core: Disable helpers for devices that fail to enable Yeoreum Yun (3): coresight/etm4: fix missing disable active config coresight: holding cscfg_csdev_lock while removing cscfg from csdev coresight: prevent deactivate active config while enabling the config .../arm/arm,coresight-static-replicator.yaml | 13 ++ Documentation/trace/coresight/coresight-perf.rst | 31 ++++ drivers/hwtracing/coresight/Kconfig | 9 ++ drivers/hwtracing/coresight/Makefile | 3 + drivers/hwtracing/coresight/coresight-catu.c | 39 +++-- drivers/hwtracing/coresight/coresight-catu.h | 1 + drivers/hwtracing/coresight/coresight-config.h | 2 +- drivers/hwtracing/coresight/coresight-core.c | 131 ++++++++++++----- drivers/hwtracing/coresight/coresight-cpu-debug.c | 3 +- drivers/hwtracing/coresight/coresight-cti-core.c | 2 + drivers/hwtracing/coresight/coresight-cti.h | 3 +- drivers/hwtracing/coresight/coresight-etb10.c | 4 +- drivers/hwtracing/coresight/coresight-etm-perf.c | 84 ++++++++++- drivers/hwtracing/coresight/coresight-etm.h | 6 +- drivers/hwtracing/coresight/coresight-etm3x-core.c | 28 ++-- .../hwtracing/coresight/coresight-etm3x-sysfs.c | 8 +- drivers/hwtracing/coresight/coresight-etm4x-core.c | 158 +++++++++++++++------ .../hwtracing/coresight/coresight-etm4x-sysfs.c | 8 +- drivers/hwtracing/coresight/coresight-etm4x.h | 2 + drivers/hwtracing/coresight/coresight-funnel.c | 4 +- .../hwtracing/coresight/coresight-kunit-tests.c | 74 ++++++++++ drivers/hwtracing/coresight/coresight-platform.c | 26 ++-- drivers/hwtracing/coresight/coresight-priv.h | 22 +-- drivers/hwtracing/coresight/coresight-replicator.c | 6 +- drivers/hwtracing/coresight/coresight-stm.c | 8 +- .../coresight/coresight-syscfg-configfs.c | 2 +- drivers/hwtracing/coresight/coresight-syscfg.c | 51 +++++-- drivers/hwtracing/coresight/coresight-tmc-core.c | 11 +- drivers/hwtracing/coresight/coresight-tmc-etf.c | 20 ++- drivers/hwtracing/coresight/coresight-tmc-etr.c | 26 ++-- drivers/hwtracing/coresight/coresight-tpiu.c | 2 +- drivers/hwtracing/coresight/coresight-trbe.c | 18 +-- include/linux/coresight.h | 44 +++--- 33 files changed, 624 insertions(+), 225 deletions(-) create mode 100644 drivers/hwtracing/coresight/coresight-kunit-tests.c

1 month, 1 week

[PATCH v3 0/2] coresight: etm4x: Refactor trace filter

by Leo Yan

This series is minor refactoring for trace filter and comes from the previous patch set [1]. The first patch introduces a new helper has_feat_trf() for detecing if FEAT_TRF is implemented. This is more readable. The second patch refactors the ts_source_show() function. It simplifies to directly return the TS value when FEAT_TRF is implemented. [1] https://lore.kernel.org/linux-arm-kernel/20250519174945.2245271-1-leo.yan@a… Changes from v2: - Added the has_feat_trf() helper for more readable (James Clark) Leo Yan (2): coresight: etm4x: Introduce has_feat_trf() helper coresight: etm4x: Refactor returning TS field drivers/hwtracing/coresight/coresight-etm4x-core.c | 8 ++++---- drivers/hwtracing/coresight/coresight-etm4x-sysfs.c | 18 +++--------------- drivers/hwtracing/coresight/coresight-etm4x.h | 9 +++++++++ 3 files changed, 16 insertions(+), 19 deletions(-) -- 2.34.1

1 month, 1 week

Re: [PATCH v6 0/3] coresight: prevent deactivate active config while enabling the config

by Suzuki K Poulose

On Wed, 14 May 2025 17:19:48 +0100, Yeoreum Yun wrote: > While enable active config via cscfg_csdev_enable_active_config(), > active config could be deactivated via configfs' sysfs interface. > This could make UAF issue in below scenario: > > CPU0 CPU1 > (sysfs enable) load module > cscfg_load_config_sets() > activate config. // sysfs > (sys_active_cnt == 1) > ... > cscfg_csdev_enable_active_config() > lock(csdev->cscfg_csdev_lock) > // here load config activate by CPU1 > unlock(csdev->cscfg_csdev_lock) > > [...] Applied, thanks! [1/3] coresight/etm4: fix missing disable active config https://git.kernel.org/coresight/c/895b12b7 [2/3] coresight: holding cscfg_csdev_lock while removing cscfg from csdev https://git.kernel.org/coresight/c/53b9e265 [3/3] coresight: prevent deactivate active config while enabling the config https://git.kernel.org/coresight/c/408c97c4 Best regards, -- Suzuki K Poulose <suzuki.poulose(a)arm.com>

1 month, 1 week

[PATCH v2 0/2] coresight: etm4x: Fix timestamp regression

by Leo Yan

The timestamp appears all zeros with latest kernel, which is caused by wrong bit field setting. The first patch fixes the regression. The second patch refactors the ts_source_show() function. It simplifies the code for directly returning the TS value. Changes from v1: - Retained the older condition check (Suzuki). Leo Yan (2): coresight: etm4x: Fix timestamp bit field handling coresight: etm4x: Refactor returning TS field drivers/hwtracing/coresight/coresight-etm4x-core.c | 2 +- drivers/hwtracing/coresight/coresight-etm4x-sysfs.c | 16 ++-------------- 2 files changed, 3 insertions(+), 15 deletions(-) -- 2.34.1

1 month, 1 week

[PATCH v2] coresight: tmc: fix failure to disable/enable ETF after reading

by Mao Jinlong

ETF may fail to re-enable after reading, and driver->reading will not be set to false, this will cause failure to enable/disable to ETF. This change set driver->reading to false even if re-enabling fail. Fixes: 669c4614236a ("coresight: tmc: Don't enable TMC when it's not ready.") Co-developed-by: Yuanfang Zhang <quic_yuanfang(a)quicinc.com> Signed-off-by: Yuanfang Zhang <quic_yuanfang(a)quicinc.com> Signed-off-by: Mao Jinlong <quic_jinlmao(a)quicinc.com> --- drivers/hwtracing/coresight/coresight-tmc-etf.c | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-tmc-etf.c b/drivers/hwtracing/coresight/coresight-tmc-etf.c index d858740001c2..c9e2d95ae295 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etf.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etf.c @@ -747,7 +747,6 @@ int tmc_read_unprepare_etb(struct tmc_drvdata *drvdata) char *buf = NULL; enum tmc_mode mode; unsigned long flags; - int rc = 0; /* config types are set a boot time and never change */ if (WARN_ON_ONCE(drvdata->config_type != TMC_CONFIG_TYPE_ETB && @@ -773,11 +772,7 @@ int tmc_read_unprepare_etb(struct tmc_drvdata *drvdata) * can't be NULL. */ memset(drvdata->buf, 0, drvdata->size); - rc = __tmc_etb_enable_hw(drvdata); - if (rc) { - raw_spin_unlock_irqrestore(&drvdata->spinlock, flags); - return rc; - } + __tmc_etb_enable_hw(drvdata); } else { /* * The ETB/ETF is not tracing and the buffer was just read. -- 2.25.1

1 month, 1 week

[PATCH] coresight: etm4x: Fix timestamp bit field handling

by Leo Yan

Timestamps in the trace data appear as all zeros on recent kernels, although the feature works correctly on old kernels (e.g., v6.12). Since commit c382ee674c8b ("arm64/sysreg/tools: Move TRFCR definitions to sysreg"), the TRFCR_ELx_TS_{VIRTUAL|GUEST_PHYSICAL|PHYSICAL} macros were updated to remove the bit shift. As a result, the driver no longer shifts bits when operates the timestamp field. Fix this by using the FIELD_PREP() and FIELD_GET() helpers. Simplify the ts_source_show() function: return -1 when the value is zero, as this indciates an invalid value; otherwise return the decoded TS value directly. Reported-by: Tamas Zsoldos <tamas.zsoldos(a)arm.com> Fixes: c382ee674c8b ("arm64/sysreg/tools: Move TRFCR definitions to sysreg") Signed-off-by: Leo Yan <leo.yan(a)arm.com> --- .../hwtracing/coresight/coresight-etm4x-core.c | 2 +- .../hwtracing/coresight/coresight-etm4x-sysfs.c | 17 ++--------------- 2 files changed, 3 insertions(+), 16 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c index 6a5898355a83..acb4a58e4bb9 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c @@ -1237,7 +1237,7 @@ static void cpu_detect_trace_filtering(struct etmv4_drvdata *drvdata) * tracing at the kernel EL and EL0, forcing to use the * virtual time as the timestamp. */ - trfcr = (TRFCR_EL1_TS_VIRTUAL | + trfcr = (FIELD_PREP(TRFCR_EL1_TS_MASK, TRFCR_EL1_TS_VIRTUAL) | TRFCR_EL1_ExTRE | TRFCR_EL1_E0TRE); diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c index 49d5fb87a74b..8a2749eeb9a5 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c @@ -2315,23 +2315,10 @@ static ssize_t ts_source_show(struct device *dev, int val; struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); - if (!drvdata->trfcr) { + val = FIELD_GET(TRFCR_EL1_TS_MASK, drvdata->trfcr); + if (!val) val = -1; - goto out; - } - - switch (drvdata->trfcr & TRFCR_EL1_TS_MASK) { - case TRFCR_EL1_TS_VIRTUAL: - case TRFCR_EL1_TS_GUEST_PHYSICAL: - case TRFCR_EL1_TS_PHYSICAL: - val = FIELD_GET(TRFCR_EL1_TS_MASK, drvdata->trfcr); - break; - default: - val = -1; - break; - } -out: return sysfs_emit(buf, "%d\n", val); } static DEVICE_ATTR_RO(ts_source); -- 2.34.1

1 month, 1 week

Re: [PATCH v6 3/3] coresight: prevent deactivate active config while enabling the config

by Leo Yan

On Wed, May 14, 2025 at 05:19:51PM +0100, Yeoreum Yun wrote: > While enable active config via cscfg_csdev_enable_active_config(), > active config could be deactivated via configfs' sysfs interface. > This could make UAF issue in below scenario: > > CPU0 CPU1 > (sysfs enable) load module > cscfg_load_config_sets() > activate config. // sysfs > (sys_active_cnt == 1) > ... > cscfg_csdev_enable_active_config() > lock(csdev->cscfg_csdev_lock) > // here load config activate by CPU1 > unlock(csdev->cscfg_csdev_lock) > > deactivate config // sysfs > (sys_activec_cnt == 0) > cscfg_unload_config_sets() > unload module > > // access to config_desc which freed > // while unloading module. > cscfg_csdev_enable_config > > To address this, use cscfg_config_desc's active_cnt as a reference count > which will be holded when > - activate the config. > - enable the activated config. > and put the module reference when config_active_cnt == 0. > > Fixes: f8cce2ff3c04 ("coresight: syscfg: Add API to activate and enable configurations") > Signed-off-by: Yeoreum Yun <yeoreum.yun(a)arm.com> Reviewed-by: Leo Yan <leo.yan(a)arm.com> > --- > .../hwtracing/coresight/coresight-config.h | 2 +- > .../hwtracing/coresight/coresight-syscfg.c | 49 +++++++++++++------ > 2 files changed, 35 insertions(+), 16 deletions(-) > > diff --git a/drivers/hwtracing/coresight/coresight-config.h b/drivers/hwtracing/coresight/coresight-config.h > index b9ebc9fcfb7f..90fd937d3bd8 100644 > --- a/drivers/hwtracing/coresight/coresight-config.h > +++ b/drivers/hwtracing/coresight/coresight-config.h > @@ -228,7 +228,7 @@ struct cscfg_feature_csdev { > * @feats_csdev:references to the device features to enable. > */ > struct cscfg_config_csdev { > - const struct cscfg_config_desc *config_desc; > + struct cscfg_config_desc *config_desc; > struct coresight_device *csdev; > bool enabled; > struct list_head node; > diff --git a/drivers/hwtracing/coresight/coresight-syscfg.c b/drivers/hwtracing/coresight/coresight-syscfg.c > index 23017612f2ea..83dad24e0116 100644 > --- a/drivers/hwtracing/coresight/coresight-syscfg.c > +++ b/drivers/hwtracing/coresight/coresight-syscfg.c > @@ -869,6 +869,25 @@ void cscfg_csdev_reset_feats(struct coresight_device *csdev) > } > EXPORT_SYMBOL_GPL(cscfg_csdev_reset_feats); > > +static bool cscfg_config_desc_get(struct cscfg_config_desc *config_desc) > +{ > + if (!atomic_fetch_inc(&config_desc->active_cnt)) { > + /* must ensure that config cannot be unloaded in use */ > + if (unlikely(cscfg_owner_get(config_desc->load_owner))) { > + atomic_dec(&config_desc->active_cnt); > + return false; > + } > + } > + > + return true; > +} > + > +static void cscfg_config_desc_put(struct cscfg_config_desc *config_desc) > +{ > + if (!atomic_dec_return(&config_desc->active_cnt)) > + cscfg_owner_put(config_desc->load_owner); > +} > + > /* > * This activate configuration for either perf or sysfs. Perf can have multiple > * active configs, selected per event, sysfs is limited to one. > @@ -892,22 +911,17 @@ static int _cscfg_activate_config(unsigned long cfg_hash) > if (config_desc->available == false) > return -EBUSY; > > - /* must ensure that config cannot be unloaded in use */ > - err = cscfg_owner_get(config_desc->load_owner); > - if (err) > + if (!cscfg_config_desc_get(config_desc)) { > + err = -EINVAL; > break; > + } > + > /* > * increment the global active count - control changes to > * active configurations > */ > atomic_inc(&cscfg_mgr->sys_active_cnt); > > - /* > - * mark the descriptor as active so enable config on a > - * device instance will use it > - */ > - atomic_inc(&config_desc->active_cnt); > - > err = 0; > dev_dbg(cscfg_device(), "Activate config %s.\n", config_desc->name); > break; > @@ -922,9 +936,8 @@ static void _cscfg_deactivate_config(unsigned long cfg_hash) > > list_for_each_entry(config_desc, &cscfg_mgr->config_desc_list, item) { > if ((unsigned long)config_desc->event_ea->var == cfg_hash) { > - atomic_dec(&config_desc->active_cnt); > atomic_dec(&cscfg_mgr->sys_active_cnt); > - cscfg_owner_put(config_desc->load_owner); > + cscfg_config_desc_put(config_desc); > dev_dbg(cscfg_device(), "Deactivate config %s.\n", config_desc->name); > break; > } > @@ -1049,7 +1062,7 @@ int cscfg_csdev_enable_active_config(struct coresight_device *csdev, > unsigned long cfg_hash, int preset) > { > struct cscfg_config_csdev *config_csdev_active = NULL, *config_csdev_item; > - const struct cscfg_config_desc *config_desc; > + struct cscfg_config_desc *config_desc; > unsigned long flags; > int err = 0; > > @@ -1064,8 +1077,8 @@ int cscfg_csdev_enable_active_config(struct coresight_device *csdev, > raw_spin_lock_irqsave(&csdev->cscfg_csdev_lock, flags); > list_for_each_entry(config_csdev_item, &csdev->config_csdev_list, node) { > config_desc = config_csdev_item->config_desc; > - if ((atomic_read(&config_desc->active_cnt)) && > - ((unsigned long)config_desc->event_ea->var == cfg_hash)) { > + if (((unsigned long)config_desc->event_ea->var == cfg_hash) && > + cscfg_config_desc_get(config_desc)) { > config_csdev_active = config_csdev_item; > csdev->active_cscfg_ctxt = (void *)config_csdev_active; > break; > @@ -1099,7 +1112,11 @@ int cscfg_csdev_enable_active_config(struct coresight_device *csdev, > err = -EBUSY; > raw_spin_unlock_irqrestore(&csdev->cscfg_csdev_lock, flags); > } > + > + if (err) > + cscfg_config_desc_put(config_desc); > } > + > return err; > } > EXPORT_SYMBOL_GPL(cscfg_csdev_enable_active_config); > @@ -1138,8 +1155,10 @@ void cscfg_csdev_disable_active_config(struct coresight_device *csdev) > raw_spin_unlock_irqrestore(&csdev->cscfg_csdev_lock, flags); > > /* true if there was an enabled active config */ > - if (config_csdev) > + if (config_csdev) { > cscfg_csdev_disable_config(config_csdev); > + cscfg_config_desc_put(config_csdev->config_desc); > + } > } > EXPORT_SYMBOL_GPL(cscfg_csdev_disable_active_config); > > -- > LEVI:{C3F47F37-75D8-414A-A8BA-3980EC8A46D7} >

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