CoreSight

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2 participants
2695 discussions

Re: [PATCH 1/2] coresight: etm4x: Report whether the PMU counts external output 1

by Leo Yan

Hi Amir, Thanks for the patch. I have a few initial comments below. We may have further feedback after our internal review. On Wed, Sep 30, 2026 at 11:37:43PM -0700, Amir Ayupov wrote: [...] > #define CS_CFG_MATCH_CLASS_SRC_ALL 0x0001 /* match any source */ > #define CS_CFG_MATCH_CLASS_SRC_ETM4 0x0002 /* match any ETMv4 device */ > +/* ETM external output 1 is countable by the PMU as TRCEXTOUT1 */ > +#define CS_CFG_MATCH_CAP_PMU_EXTOUT1 0x0004 Do we need to tie this capability to TRCEXTOUT1? For example, Neoverse V2 exposes TRCEXTOUT0 through TRCEXTOUT3 as PMU events. > /* flags defining device instance matching - used in config match desc data. */ > #define CS_CFG_MATCH_INST_ANY 0x80000000 /* any instance of a class */ > diff --git a/drivers/hwtracing/coresight/coresight-etm4x-cfg.c b/drivers/hwtracing/coresight/coresight-etm4x-cfg.c > index e1a59b4345052..2847d2d7f7bed 100644 > --- a/drivers/hwtracing/coresight/coresight-etm4x-cfg.c > +++ b/drivers/hwtracing/coresight/coresight-etm4x-cfg.c > @@ -174,9 +174,14 @@ static int etm4_cfg_load_feature(struct coresight_device *csdev, > > int etm4_cscfg_register(struct coresight_device *csdev) > { > + struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); > struct cscfg_csdev_feat_ops ops; > + u32 match_flags = CS_CFG_ETM4_MATCH_FLAGS; > > ops.load_feat = &etm4_cfg_load_feature; > > - return cscfg_register_csdev(csdev, CS_CFG_ETM4_MATCH_FLAGS, &ops); > + if (drvdata->pmu_extout1) > + match_flags |= CS_CFG_MATCH_CAP_PMU_EXTOUT1; > + > + return cscfg_register_csdev(csdev, match_flags, &ops); The current matching logic succeeds if a device and feature share any flag bit. If the feature sets both CS_CFG_MATCH_CLASS_SRC_ETM4 and CS_CFG_MATCH_CAP_PMU_EXTOUT1, it will still load on an ETM4 device that lacks the capability. Could we check the capability separately when loading the feature, perhaps in cscfg_load_feat_csdev(), and skip it on unsupported devices? > +static bool etm4_pmu_has_extout1(struct etmv4_drvdata *drvdata) > +{ > + int pmuver = read_pmuver(); > + > + if (!is_midr_in_range_list(etm4_pmu_extout1_cpus)) > + return false; Based on specific CPU variant, we should already have identified TRCEXTOUT has supported. So either we only base on MIDR list or we can figure out a reliable way to detect the feature dynamically. > + > + /* PMCEID0_EL0[63:32] describe events 0x4000-0x401f from PMUv3p1 */ > + if (!pmuv3_implemented(pmuver) || pmuver < ID_AA64DFR0_EL1_PMUVer_V3P1) > + return false; > + if (!(read_pmceid0() & BIT_ULL(32 + ARMV8_PMUV3_PERFCTR_TRCEXTOUT1 - > + ARMV8_PMUV3_EXT_COMMON_EVENT_BASE))) > + return false; > + > + /* nr_event is TRCIDR0.NUMEVENT, the number of events minus one */ > + return drvdata->nr_event >= 1; > +} [...] > @@ -1116,6 +1116,13 @@ int cscfg_csdev_enable_active_config(struct coresight_device *csdev, > > if (err) > cscfg_config_desc_put(config_desc); > + } else { > + /* > + * The configuration is active but was not loaded on this > + * device, for example because the device lacks a capability > + * its features require. Fail rather than trace without it. > + */ > + err = -EINVAL; > } This fixes a pre-existing issue. It is worther to put it in a separate patch with fixes tag: An early return would also avoid the normal enable path's indentation: if (!config_csdev_active) return -EINVAL; err = cscfg_csdev_enable_config(config_csdev_active, preset); ... Thanks, Leo

3 weeks, 5 days

Re: [PATCH 2/2] perf: arm_spe: Prefer large AUX mappings

by Leo Yan

On Thu, Oct 01, 2026 at 08:16:09AM +0100, Will Deacon wrote: > On Wed, Sep 30, 2026 at 05:43:11PM +0100, Leo Yan wrote: > > How about adding a field to struct pmu to specify a preferred maximum > > page order for the AUX buffer? The perf core could try that order first > > and fall back to smaller orders if the allocation fails. > > I'm not sure that's thr right place for it, really. The driver has no > clue about whether it makes sense to use large contiguous mappings or > not, so I'd have thought that decision should be driven from userspace > (e.g. like MADV_HUGEPAGE) because it really depends on the user's > preference and isn't a fixed property of the hardware. Here MADV_HUGEPAGE cannot directly apply on this case: perf allocates the AUX pages during mmap, while TRBE accesses them through a separate kernel vmap() mapping. MADV_HUGEPAGE is applied after mmap, but a preference (or flag) would need to be specified before the AUX mmap. > > For example, the Neoverse V2 TRM documents: > > > > L1 Trace Buffer Extension (TRBE) TLB: 1 entry > > Wow, they really pulled out the stops for that implementation. I bet > we're supposed to be grateful for that entry! Yeah, Neoverse V3 was improved to have two entries. Even so, I was told it still suffers from TLB misses, so still needs a large mapping granule. > > Given the single L1 TRBE TLB entry, the TRBE driver could prefer > > PMD_ORDER (2 MiB with 4 KiB pages) to reduce TLB pressure. This reflects > > the hardware characteristic. > > > > This could be a trade-off instead of using PERF_PMU_CAP_AUX_PREFER_LARGE, > > avoiding large contiguous allocations that could reintroduce the Android > > OOM issue. I did a quick test with this approach and the results look > > positive. > > I really don't want the driver to second-guess userspace based on whatever > information it happens to have hard-coded about the specific CPU it's > running on. The kernel already takes the PERF_PMU_CAP_AUX_PREFER_LARGE flag from a PMU; a preferred maximum order would let the driver give it a bounded value. I do not intend to hard-code or guess a preference for a particular CPU variant. We can map TRBE or SPE buffer at PMD granularity. On a 4 KiB-page system, PMD_ORDER is order 9, or 2 MiB. Requesting a larger contiguous chunk cannot increase the mapping granule, so I would cap the preference there. It remains a preference: perf can fall back to smaller orders when allocation fails. Exposing the preference to userspace also seems problematic. Users generally lack the hardware details needed to choose an appropriate value. Even if tools provide a default, the same policy would need to be duplicated across perf, simpleperf, and proprietary tools. I don't think userspace tools are the right place for this policy. Thanks, Leo

4 weeks

Re: [PATCH 5/5] ARM: dts: qcom: apq8064: Drop PCLK from static replicator

by Leo Yan

On Fri, Oct 02, 2026 at 07:05:14PM +0300, Dmitry Baryshkov wrote: > On Fri, Oct 02, 2026 at 04:33:28PM +0100, Leo Yan wrote: > > On Fri, Oct 02, 2026 at 06:21:36PM +0300, Dmitry Baryshkov wrote: > > > On Fri, Oct 02, 2026 at 04:07:24PM +0100, Leo Yan wrote: > > > > The APQ8064 static replicator has no registers to program, so it > > > > does not need an APB clock. Remove its RPM_QDSS_CLK reference. > > > > Other programmable CoreSight devices keep their clock references. > > > > > > QDSS clock is not actually the APB one, it's required for the coresight > > > (or to access some of the regs) if I remember correctly. > > > > If so, it might be atclk for clocking the module rather than the > > register interface. Could you confirm this? > > > > The replicator is just a middle component on the data path. I read > > that it shares the same clock with other CoreSight components, so it > > should still be safe to remove the clock from the replicator node, > > as other components on the path will ensure that the clock is enabled. > > Unfortunately it might be hard to find info for this platform nowadays. How about rename RPM_QDSS_CLK on the static replicator as "atclk", the optional clock name supported by its binding. replicator { compatible = "arm,coresight-static-replicator"; clocks = <&rpmcc RPM_QDSS_CLK>; - clock-names = "apb_pclk"; + clock-names = "atclk"; I would leave the AMBA CoreSight nodes in the same dtsi unchanged for now. They need an apb_pclk lookup for register access, and so far we have no evidence to justify adding the same RPM clock again as atclk. Please let me know if this works for you. Thanks, Leo

4 weeks

[PATCH RESEND v13 00/14] fix several inconsistencies with sysfs configuration in etmX

by Yeoreum Yun

The current ETMx configuration via sysfs can lead to the following inconsistencies: - If a configuration is modified via sysfs while a perf session is active, the running configuration may differ between before a sched-out and after a subsequent sched-in. - If a perf session and sysfs session tries to enable concurrently, configuration from configfs could be corrupted (etm4). - There is chance to corrupt drvdata->config if perf session tries to enabled among handling cscfg_csdev_disable_active_config() in etm4_disable_sysfs() (etm4). To resolve these inconsistencies, the configuration should be separated into: - curr_config, which is applied configuration for the current session - config, which stores the settings configured via sysfs. and apply configuration from configfs after taking a mode. Patch History ============= from v12 to v13: - add r-b tags - Link to v12: https://lore.kernel.org/r/20260924-separate_etm_cfg_v2-v12-0-a2b41d2f7c2b@a… from v11 to v12: - rename active_config to curr_config. - rename config to sysfs_config. - remove redundant config argument in etmX_args. - add read-back and copy from curr_config to sysfs_config TRCSEQSTR (seq_state). - add r-b and t-b tags. - Link to v11: https://lore.kernel.org/r/20260915-separate_etm_cfg_v2-v11-0-d2b258d51747@a… from v10 to v11: - replace direct register read from etm3 sysfs with IPI. - fix issue cntr_val and others field which required to be shown after sysfs session disable. - prohibit the write for some etm3 sysfs while sysfs session is enabled. - drop locktype change in etm3 - Link to v10: https://lore.kernel.org/r/20260911-separate_etm_cfg_v2-v10-0-1b715d95927a@a… from v9 to v10: - rebase to coresight/next - https://lore.kernel.org/all/20260725113645.57519-1-yeoreum.yun@arm.com/ from v8 to v9: - add feat_csdev_lock guard interface. - set feat_csdev->drv_spinlock as NULL for etmv4_drvdata. - https://lore.kernel.org/all/20260629090007.1718746-1-yeoreum.yun@arm.com/ from v7 to v8: - accept @Leo Yan' suggestion to handle error. - small minor fixes following @Suzuki' suggestion. - https://lore.kernel.org/all/20260519154812.254884-1-yeoreum.yun@arm.com/ from v6 to v7: - rebase on coresight/next - add ETM_MAX_SEQ_TRANSITIONS define - remove redundant patch relavent cpu-hotplug as coresight-pm patch merged. - https://lore.kernel.org/all/20260422132203.977549-1-yeoreum.yun@arm.com/ from v5 to v6: - fix missing of calling cscfg_csdev_disable_active_config() - add rb & fixes tags. - add ss_status field in etm4x_drvdata to expose STATUS and PENDING bits. - https://lore.kernel.org/all/20260415165528.3369607-1-yeoreum.yun@arm.com/ from v4 to v5: - add rb-tag. - fix underflow issue for nrseqstate. - fix wrong check in etm4_sspcicrn_present(). - remove redundant fields on etmv4_save_state. - rename caps->ss_status to ss_cmp. - fix wrong location of etm4_release_trace_id. - https://lore.kernel.org/all/20260413142003.3549310-1-yeoreum.yun@arm.com/ from v3 to v4: - change etm_drvdata->spinlock type to raw_spin_lock_t - remove redundant call etmX_enable_hw() with starting_cpu() callsback. - fix missing trace id release. - add missing docs. - https://lore.kernel.org/all/20260412175506.412301-1-yeoreum.yun@arm.com/ from v2 to v3: - fix build error for etm3x. - fix checkpatch warning. - https://lore.kernel.org/all/20260410074310.2693385-1-yeoreum.yun@arm.com/ from v1 to v2 - rebased to v7.0-rc7. - introduce etmX_caps structure to save etmX's capabilities. - remove ss_status from etmv4_config. - modify active_config after taking a mode (perf/sysfs). - https://lore.kernel.org/all/20260317181705.2456271-1-yeoreum.yun@arm.com/ --- Yeoreum Yun (14): coresight: etm4x: read-back TRCSEQSTR at disabling and prohibit modifying seq_state while enabling. coresight: etm4x: prohibit modifying cntr_val while session is enabled coresight: etm3x: prohibit modifying cntr_val and reset while session is enabled coresight: etm4x: fix inconsistencies with sysfs configuration coresight: etm3x: fix inconsistencies with sysfs configuration coresight: etm3x: remove redundant cpu online check on etm_enable_sysfs() coresight: etm4x: introduce struct etm4_caps coresight: etm4x: exclude ss_status from drvdata->config coresight: etm4x: remove s_ex_level from config coresight: etm4x: rename local config as curr_config referring drvdata->curr_config coresight: etm4x: rename drvdata->config to sysfs_config coresight: etm3x: introduce struct etm_caps coresight: etm3x: rename local config as curr_config referring drvdata->curr_config coresight: etm3x: rename drvdata->config to sysfs_config drivers/hwtracing/coresight/coresight-config.c | 18 +- drivers/hwtracing/coresight/coresight-config.h | 22 + drivers/hwtracing/coresight/coresight-etm.h | 48 +- drivers/hwtracing/coresight/coresight-etm3x-core.c | 196 +++-- .../hwtracing/coresight/coresight-etm3x-sysfs.c | 461 +++++----- drivers/hwtracing/coresight/coresight-etm4x-cfg.c | 14 +- drivers/hwtracing/coresight/coresight-etm4x-core.c | 567 ++++++------ .../hwtracing/coresight/coresight-etm4x-sysfs.c | 961 +++++++++++---------- drivers/hwtracing/coresight/coresight-etm4x.h | 199 +++-- 9 files changed, 1340 insertions(+), 1146 deletions(-) --- base-commit: a3281934612608db9e1d24aaf913c846e913de89 change-id: 20260911-separate_etm_cfg_v2-3518a168cbff Best regards, -- Sincerely, Yeoreum Yun

1 month

[PATCH v13 00/14] fix several inconsistencies with sysfs configuration in etmX

by Yeoreum Yun

1 month

Re: [PATCH 5/5] ARM: dts: qcom: apq8064: Drop PCLK from static replicator

by Leo Yan

On Fri, Oct 02, 2026 at 06:21:36PM +0300, Dmitry Baryshkov wrote: > On Fri, Oct 02, 2026 at 04:07:24PM +0100, Leo Yan wrote: > > The APQ8064 static replicator has no registers to program, so it > > does not need an APB clock. Remove its RPM_QDSS_CLK reference. > > Other programmable CoreSight devices keep their clock references. > > QDSS clock is not actually the APB one, it's required for the coresight > (or to access some of the regs) if I remember correctly. If so, it might be atclk for clocking the module rather than the register interface. Could you confirm this? The replicator is just a middle component on the data path. I read that it shares the same clock with other CoreSight components, so it should still be safe to remove the clock from the replicator node, as other components on the path will ensure that the clock is enabled. Thanks, Leo

1 month

[PATCH 0/5] arm: coresight: Clean up funnel and replicator clocks

by Leo Yan

This series documents optional atclk for static CoreSight links and removes unused clock references from several device trees. It also describes the programmable Zynq-7000 funnel as dynamic. Signed-off-by: Leo Yan <leo.yan(a)arm.com> --- Leo Yan (5): dt-bindings: arm: coresight: Limit static replicator to atclk dt-bindings: arm: coresight: Allow atclk for static funnel arm64: dts: hisilicon: Drop PCLK from static CoreSight links ARM: dts: zynq: Use dynamic CoreSight funnel and trim clocks ARM: dts: qcom: apq8064: Drop PCLK from static replicator .../bindings/arm/arm,coresight-static-funnel.yaml | 6 ++++++ .../arm/arm,coresight-static-replicator.yaml | 11 ++-------- arch/arm/boot/dts/qcom/qcom-apq8064.dtsi | 3 --- arch/arm/boot/dts/xilinx/zynq-7000.dtsi | 24 ++++++++++------------ .../arm64/boot/dts/hisilicon/hi3660-coresight.dtsi | 4 ---- .../arm64/boot/dts/hisilicon/hi6220-coresight.dtsi | 2 -- 6 files changed, 19 insertions(+), 31 deletions(-) --- base-commit: 551c722f40809618230001baccf219193e22fc5a change-id: 20261001-arm_coresight_hi3660_remove_dynamic_funnel_clocks-d277556abe8d Best regards, -- Leo Yan <leo.yan(a)arm.com>

1 month

[PATCH v2 0/4] perf: cs-etm: HW_ID improvements

by James Clark

The driver might not always be able to write HW_IDs, but we don't need them for unformatted mode anyway, so fix that in commit ("perf cs-etm: Synthesize missing HW_ID mappings for raw trace"). Include some other minor improvements encountered on the way to appease Sashiko, like properly freeing queues and ("perf: cs-etm: Respect --no-itrace option") makes debugging broken Coresight perf.data files easier. Signed-off-by: James Clark <james.clark(a)linaro.org> --- Changes in v2: - Drop driver changes and move to https://lore.kernel.org/linux-perf-users/20261001-james-cs-retry-hw_id-v1-0… - Don't process any HW_IDs for unformatted queues, just create decoders unconditionally with trace ID 1. - Use zfree() instead of etmq->decoder = NULL - Remove dependency on "[PATCH v2 00/14] perf cs-etm: Per-thread mode fixes and snapshot wrap support", it wasn't functionally dependant, just touching some of the same lines. - Link to v1: https://patch.msgid.link/20260821-james-cs-hw_id-output-failure-v1-0-9d532d… --- James Clark (3): perf: cs-etm: Don't add global v0 HW_IDs to unformatted queues perf cs-etm: Free partially created queues perf: cs-etm: Respect --no-itrace option Leo Yan (1): perf cs-etm: Synthesize missing HW_ID mappings for raw trace tools/perf/util/auxtrace.c | 2 +- tools/perf/util/auxtrace.h | 1 + tools/perf/util/cs-etm-decoder/cs-etm-decoder.c | 12 +- tools/perf/util/cs-etm-decoder/cs-etm-decoder.h | 2 +- tools/perf/util/cs-etm.c | 184 +++++++++++++++--------- 5 files changed, 123 insertions(+), 78 deletions(-) --- base-commit: 78148c85297024ffe7a709acb7cc4fc907271176 change-id: 20260706-james-cs-hw_id-output-failure-1d06d042ef96 prerequisite-change-id: 20260605-james-cs-unformatted-per-thread-fix-50e723aa7f0e:v2 prerequisite-patch-id: 1aa32269a3a7dc76840dd8a24cb5a8715507e898 prerequisite-patch-id: ef471f468351462f67efa58a09a3461306ac5a0a prerequisite-patch-id: c78946cf4ec1c7722570865403a3562625bdaa33 prerequisite-patch-id: 0b953eee0252db3c7ba3ef1e3397048a94482ca2 prerequisite-patch-id: 27da72c2f01bcc68205bbcc14d5019369c02cb83 prerequisite-patch-id: 365c6d5f71c754e4c690b5ebed3453565bb5b809 prerequisite-patch-id: 64e9419a41082a2db3daf255baf0fb40efbae5dd prerequisite-patch-id: 1dc2e6ef8e76b369736b4c88560302861b2e4faf prerequisite-patch-id: b7de38ec4d90f5b45d56390a4e5919a1d6439951 prerequisite-patch-id: 3548d5b161cfb8c11a166ca2b3228ca4821f1ca0 prerequisite-patch-id: 97e66600218a2b32e5b21d0abcb6321590f98de9 prerequisite-patch-id: 292282b20bd8ad7d096ee7ffbc55dcfb75455f53 prerequisite-patch-id: c80259b47850ba65c985c85a29c8cf4948463d59 Best regards, -- James Clark <james.clark(a)linaro.org>

1 month

[PATCH v2] coresight: trbe: Hide enable_sink sysfs file

by James Clark

TRBE doesn't support sysfs mode, but the enable_sink file can still be successfully written to enable the device, and only attempting to enable the source would later fail. Avoid misleading users by adding a flag that devices can use to hide either the enable_sink or enable_source files, and set it for TRBE. Don't set it for ETE as it's possible that ETE could appear on the legacy bus and work with sysfs, and writing to enable_source already reports EINVAL if the device doesn't support sysfs mode. Signed-off-by: James Clark <james.clark(a)linaro.org> --- Changes in v2: - Re-use CORESIGHT_DESC flags in csdev instead of converting to bool. - Hide all remaining attrs after label instead of only source and sink attrs as there aren't any others anyway (Leo). - Link to v1: https://lore.kernel.org/r/20260507-james-cs-hide-trbe-enable-v1-1-b4e40439f… --- drivers/hwtracing/coresight/coresight-core.c | 1 + drivers/hwtracing/coresight/coresight-sysfs.c | 15 +++++++++------ drivers/hwtracing/coresight/coresight-trbe.c | 7 +++++++ include/linux/coresight.h | 4 ++++ 4 files changed, 21 insertions(+), 6 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-core.c b/drivers/hwtracing/coresight/coresight-core.c index f7b1308a759c..a0c098980096 100644 --- a/drivers/hwtracing/coresight/coresight-core.c +++ b/drivers/hwtracing/coresight/coresight-core.c @@ -1543,6 +1543,7 @@ coresight_init_device(struct coresight_desc *desc) csdev->ops = desc->ops; csdev->access = desc->access; csdev->orphan = true; + csdev->flags = desc->flags; if (desc->flags & CORESIGHT_DESC_CPU_BOUND) { csdev->cpu = desc->cpu; diff --git a/drivers/hwtracing/coresight/coresight-sysfs.c b/drivers/hwtracing/coresight/coresight-sysfs.c index 4b010f8bc4c0..75000fe64fda 100644 --- a/drivers/hwtracing/coresight/coresight-sysfs.c +++ b/drivers/hwtracing/coresight/coresight-sysfs.c @@ -346,16 +346,19 @@ static ssize_t label_show(struct device *dev, } static DEVICE_ATTR_RO(label); -static umode_t label_is_visible(struct kobject *kobj, - struct attribute *attr, int n) +static umode_t coresight_attr_is_visible(struct kobject *kobj, + struct attribute *attr, int n) { struct device *dev = kobj_to_dev(kobj); + struct coresight_device *csdev = to_coresight_device(dev); if (attr == &dev_attr_label.attr) { if (fwnode_property_present(dev_fwnode(dev), "label")) return attr->mode; else return 0; + } else if (csdev->flags & CORESIGHT_DESC_NO_SYSFS_MODE) { + return 0; } return attr->mode; @@ -369,7 +372,7 @@ static struct attribute *coresight_sink_attrs[] = { static struct attribute_group coresight_sink_group = { .attrs = coresight_sink_attrs, - .is_visible = label_is_visible, + .is_visible = coresight_attr_is_visible, }; __ATTRIBUTE_GROUPS(coresight_sink); @@ -381,7 +384,7 @@ static struct attribute *coresight_source_attrs[] = { static struct attribute_group coresight_source_group = { .attrs = coresight_source_attrs, - .is_visible = label_is_visible, + .is_visible = coresight_attr_is_visible, }; __ATTRIBUTE_GROUPS(coresight_source); @@ -392,7 +395,7 @@ static struct attribute *coresight_link_attrs[] = { static struct attribute_group coresight_link_group = { .attrs = coresight_link_attrs, - .is_visible = label_is_visible, + .is_visible = coresight_attr_is_visible, }; __ATTRIBUTE_GROUPS(coresight_link); @@ -403,7 +406,7 @@ static struct attribute *coresight_helper_attrs[] = { static struct attribute_group coresight_helper_group = { .attrs = coresight_helper_attrs, - .is_visible = label_is_visible, + .is_visible = coresight_attr_is_visible, }; __ATTRIBUTE_GROUPS(coresight_helper); diff --git a/drivers/hwtracing/coresight/coresight-trbe.c b/drivers/hwtracing/coresight/coresight-trbe.c index c7cbca45f2de..eca8e13a9744 100644 --- a/drivers/hwtracing/coresight/coresight-trbe.c +++ b/drivers/hwtracing/coresight/coresight-trbe.c @@ -1348,6 +1348,13 @@ static void arm_trbe_register_coresight_cpu(struct trbe_drvdata *drvdata, int cp desc.dev = dev; desc.cpu = cpu; desc.flags = CORESIGHT_DESC_CPU_BOUND; + /* + * ETE isn't connected to TRBE with a link like other Coresight devices + * and the TRBE driver has been written to always assume Perf mode, so + * Prevent sysfs from being used. + */ + desc.flags |= CORESIGHT_DESC_NO_SYSFS_MODE; + trbe_csdev = coresight_register(&desc); if (IS_ERR(trbe_csdev)) goto cpu_clear; diff --git a/include/linux/coresight.h b/include/linux/coresight.h index add0579cad88..6cd1d01b843b 100644 --- a/include/linux/coresight.h +++ b/include/linux/coresight.h @@ -142,6 +142,8 @@ struct csdev_access { }) #define CORESIGHT_DESC_CPU_BOUND BIT(0) +/* Device can't be activated from sysfs, only via Perf. */ +#define CORESIGHT_DESC_NO_SYSFS_MODE BIT(1) /** * struct coresight_desc - description of a component required from drivers @@ -310,6 +312,8 @@ struct coresight_device { struct list_head config_csdev_list; raw_spinlock_t cscfg_csdev_lock; void *active_cscfg_ctxt; + /* CORESIGHT_DESC_[x] flags */ + u32 flags; }; /* --- base-commit: c8eb4a8dd259fb2b215da32764fa8c6c76519896 change-id: 20260506-james-cs-hide-trbe-enable-3c8d784e72d8 Best regards, -- James Clark <james.clark(a)linaro.org>

1 month

Re: [PATCH] dt-bindings: arm: coresight: Allow funnel clocks

by Leo Yan

On Thu, Oct 01, 2026 at 07:04:44AM -0500, Rob Herring wrote: [...] > > The question is that a static funnel does not need to program any > > registers, so in theory it should only need atclk as the module's core > > clock, but not the APB programming clock (apb_pclk). > > > > Maybe I did not get this right when I initially enabled the static > > funnel in hi3660-coresight.dtsi. We should probably remove pclk from the > > static funnel node. > > Yes. I suppose in theory it has some clock, but if pclk needed to be > enabled, it is shared with all the other coresight components and > enabled anyways. And there's no atclk defined, so 'clocks' can just > be removed. Can you send a patch to do that, and I'll drop this one. Sure, I will prepare a patch for hi3660-coresight.dtsi. > zynq7000 is even more of a mess I just noticed... Agreed. It should bind to "arm,coresight-dynamic-funnel" instead. However, I'm afraid the "dbg_trc" and "dbg_apb" clocks are never touched by either the CoreSight driver or the AMBA driver after switching to the dynamic funnel. These clocks should therefore be removed from all CoreSight nodes. Thanks, Leo

1 month

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