CoreSight

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2565 discussions

[PATCH v5 00/11] CoreSight: Refactor power management for ETMv3/4

by Leo Yan

This series is extracted from the CoreSight power management fixes and refactoring [1], focusing on ETMv3/4 power management. This series has been verified on Juno-r2 platform. [1] https://lore.kernel.org/linux-arm-kernel/20250915-arm_coresight_power_manag… --- Changes in v5: - Added more info for removing redundant DSB in etm4_{enable|disable}_trace_unit() (Suzuki/Levi). - Dropped moving isb() out from etm4_{enable|disable}_trace_unit() (Suzuki). - Reordered patches to move fixes earlier. - Link to v4: https://lore.kernel.org/r/20251024-arm_coresight_power_management_fix-v4-0-… Changes in v4: - Added patch 10 for retaining sequencer state in ETMv4 driver (Mike). - Added Mike's review tags. - Added James' test tags. - Link to v3: https://lore.kernel.org/r/20250915-arm_coresight_power_management_fix-v3-0-… Changes in v3: - Fixed building failure in ETMv3 driver (kernel test robot). - Refactoring ETMv3 change for checking CPU ID (Levi). - Fixed NULL pointer issue during CPU idle (James). - Fixed lockdep complaint for HARDIRQ-safe and HARDIRA-unsafe (James). - Fixed acquiring mutex in atomic context (James). - Rebased on the latest coresight-next branch. - Link to v2: https://lore.kernel.org/r/20250701-arm_cs_pm_fix_v3-v2-0-23ebb864fcc1@arm.c… Changes in v2: - Refactored ETMv4 suspend and resume for reusing the normal enabling and disabling flows (James). - Used a per-CPU structure to maintain path pointers (James). - Supported helpers in CPU PM flows (James). - Fixed the SMP-safe access to device mode. - Fixed the context synchronization in ETMv4x driver. - Link to v1: https://lore.kernel.org/linux-arm-kernel/20250516160742.1200904-1-leo.yan@a… Signed-off-by: Leo Yan <leo.yan(a)arm.com> --- Leo Yan (11): coresight: Change device mode to atomic type coresight: etm4x: Always set tracer's device mode on target CPU coresight: etm3x: Always set tracer's device mode on target CPU coresight: etm4x: Correct polling IDLE bit coresight: etm4x: Add context synchronization before enabling trace coresight: etm4x: Properly control filter in CPU idle with FEAT_TRF coresight: etm4x: Remove the redundant DSB coresight: etm4x: Remove the state_needs_restore flag coresight: etm4x: Add flag to control single-shot restart coresight: etm4x: Retain sequencer state coresight: etm4x: Reuse normal enable and disable logic in CPU idle drivers/hwtracing/coresight/coresight-etm3x-core.c | 59 ++-- drivers/hwtracing/coresight/coresight-etm4x-core.c | 347 +++++++-------------- drivers/hwtracing/coresight/coresight-etm4x.h | 62 ---- include/linux/coresight.h | 25 +- 4 files changed, 157 insertions(+), 336 deletions(-) --- base-commit: 6146a0f1dfae5d37442a9ddcba012add260bceb0 change-id: 20250909-arm_coresight_power_management_fix-139873f942e8 Best regards, -- Leo Yan <leo.yan(a)arm.com>

3 weeks, 4 days

Re: [PATCH v2 0/3] coresight: replace the void pointer with coresight_path pointer

by Suzuki K Poulose

On Thu, 25 Sep 2025 18:42:30 +0800, Jie Gan wrote: > Patch 1: > Fix the issue that the catu cannot correctly read the handle of the AUX > event which is caused by the commit[1]. > > [1] 080ee83cc361 ("Coresight: Change functions to accept the coresight_path") > > Exeception call trace: > tmc_etr_get_buffer+0x30/0x80 [coresight_tmc] (P) > catu_enable_hw+0xbc/0x3d0 [coresight_catu] > catu_enable+0x70/0xe0 [coresight_catu] > coresight_enable_path+0xb0/0x258 [coresight] > > [...] Applied, thanks! [1/3] coresight: tmc: add the handle of the event to the path https://git.kernel.org/coresight/c/aaa5abcc9d44 [2/3] coresight: change helper_ops to accept coresight_path https://git.kernel.org/coresight/c/94baedb51dea [3/3] coresight: change the sink_ops to accept coresight_path https://git.kernel.org/coresight/c/b139702a8896 Best regards, -- Suzuki K Poulose <suzuki.poulose(a)arm.com>

3 weeks, 5 days

Re: [PATCH v3] coresight: ETR: Fix ETR buffer use-after-free issue

by Suzuki K Poulose

On Tue, 21 Oct 2025 16:45:25 +0800, Xiaoqi Zhuang wrote: > When ETR is enabled as CS_MODE_SYSFS, if the buffer size is changed > and enabled again, currently sysfs_buf will point to the newly > allocated memory(buf_new) and free the old memory(buf_old). But the > etr_buf that is being used by the ETR remains pointed to buf_old, not > updated to buf_new. In this case, it will result in a memory > use-after-free issue. > > [...] Applied, thanks! [1/1] coresight: ETR: Fix ETR buffer use-after-free issue https://git.kernel.org/coresight/c/35501ac3c7d4 Best regards, -- Suzuki K Poulose <suzuki.poulose(a)arm.com>

4 weeks, 1 day

Re: [PATCH] coresight: tpdm: remove redundant check for drvdata

by Suzuki K Poulose

On Fri, 07 Nov 2025 14:16:39 +0800, Jie Gan wrote: > Remove the redundant check for drvdata data because the drvdata here already > has been guarranted to be non-NULL. > > Applied, thanks! [1/1] coresight: tpdm: remove redundant check for drvdata https://git.kernel.org/coresight/c/aa5edd1b5ece Best regards, -- Suzuki K Poulose <suzuki.poulose(a)arm.com>

4 weeks, 1 day

Re: [PATCH] coresight: tpdm: remove redundant check for drvdata

by Suzuki K Poulose

On 07/11/2025 06:16, Jie Gan wrote: > Remove the redundant check for drvdata data because the drvdata here already > has been guarranted to be non-NULL. > > Fixes: 350ba15ae187 ("coresight-tpdm: Add nodes for dsb msr support") > Fixes: 8e8804145a46 ("coresight-tpdm: Add msr register support for CMB") This doesn't need to be backported as such, as it is a cleanup. I will drop the Fixes tag and merge this. Suzuki > Signed-off-by: Jie Gan <jie.gan(a)oss.qualcomm.com> > --- > drivers/hwtracing/coresight/coresight-tpdm.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/hwtracing/coresight/coresight-tpdm.c b/drivers/hwtracing/coresight/coresight-tpdm.c > index 0e3896c12f07..06e0a905a67d 100644 > --- a/drivers/hwtracing/coresight/coresight-tpdm.c > +++ b/drivers/hwtracing/coresight/coresight-tpdm.c > @@ -1402,11 +1402,11 @@ static int tpdm_probe(struct device *dev, struct resource *res) > if (ret) > return ret; > > - if (drvdata && tpdm_has_dsb_dataset(drvdata)) > + if (tpdm_has_dsb_dataset(drvdata)) > of_property_read_u32(drvdata->dev->of_node, > "qcom,dsb-msrs-num", &drvdata->dsb_msr_num); > > - if (drvdata && tpdm_has_cmb_dataset(drvdata)) > + if (tpdm_has_cmb_dataset(drvdata)) > of_property_read_u32(drvdata->dev->of_node, > "qcom,cmb-msrs-num", &drvdata->cmb_msr_num); > } else { > > --- > base-commit: df5d79720b152e7ff058f11ed7e88d5b5c8d2a0c > change-id: 20251107-fix_tpdm_redundant_check-a5a7bad4b7c8 > prerequisite-change-id: 20251028-add_static_tpdm_support-1f62477857e2:v4 > prerequisite-patch-id: eda8dd6884b831cb10affc22477aece39c78b408 > prerequisite-patch-id: 7beb8b17d54ff21bc57eab10b56e6ffcfa4d1963 > prerequisite-patch-id: f6f1e78dba3f1d3b1191ab827adab5a3b7b2326a > > Best regards,

4 weeks, 1 day

[PATCH] coresight: tmc: Prevent sysfs parameter changes if sink in use

by Mike Leach

The sysfs files that change the operational parameters for TMC buffer_size, stop_on_flush and trigger_cntr are writable when the TMC is in use. The new values will have no effect and be silently ignored. Alter the sysfs functions to return -EBUSY if the TMC is currently in use, and also protect the write values using the spinlock. Signed-off-by: Mike Leach <mike.leach(a)linaro.org> --- .../hwtracing/coresight/coresight-tmc-core.c | 41 ++++++++++++++++--- 1 file changed, 35 insertions(+), 6 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-tmc-core.c b/drivers/hwtracing/coresight/coresight-tmc-core.c index 36599c431be6..a1216a1f9681 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-core.c +++ b/drivers/hwtracing/coresight/coresight-tmc-core.c @@ -489,15 +489,24 @@ static ssize_t trigger_cntr_store(struct device *dev, const char *buf, size_t size) { int ret; - unsigned long val; + unsigned long val, flags; struct tmc_drvdata *drvdata = dev_get_drvdata(dev->parent); ret = kstrtoul(buf, 16, &val); if (ret) return ret; + /* do not permit write if the sink is currently in use */ + raw_spin_lock_irqsave(&drvdata->spinlock, flags); + if (coresight_get_mode(drvdata->csdev) != CS_MODE_DISABLED) { + ret = -EBUSY; + goto out; + } drvdata->trigger_cntr = val; - return size; + ret = size; +out: + raw_spin_unlock_irqrestore(&drvdata->spinlock, flags); + return ret; } static DEVICE_ATTR_RW(trigger_cntr); @@ -514,7 +523,7 @@ static ssize_t buffer_size_store(struct device *dev, const char *buf, size_t size) { int ret; - unsigned long val; + unsigned long val, flags; struct tmc_drvdata *drvdata = dev_get_drvdata(dev->parent); /* Only permitted for TMC-ETRs */ @@ -527,8 +536,18 @@ static ssize_t buffer_size_store(struct device *dev, /* The buffer size should be page aligned */ if (val & (PAGE_SIZE - 1)) return -EINVAL; + + /* do not permit write if the sink is currently in use */ + raw_spin_lock_irqsave(&drvdata->spinlock, flags); + if (coresight_get_mode(drvdata->csdev) != CS_MODE_DISABLED) { + ret = -EBUSY; + goto out; + } drvdata->size = val; - return size; + ret = size; +out: + raw_spin_unlock_irqrestore(&drvdata->spinlock, flags); + return ret; } static DEVICE_ATTR_RW(buffer_size); @@ -547,17 +566,27 @@ static ssize_t stop_on_flush_store(struct device *dev, { int ret; u8 val; + unsigned long flags; struct tmc_drvdata *drvdata = dev_get_drvdata(dev->parent); ret = kstrtou8(buf, 0, &val); if (ret) return ret; + + /* do not permit write if the sink is currently in use */ + raw_spin_lock_irqsave(&drvdata->spinlock, flags); + if (coresight_get_mode(drvdata->csdev) != CS_MODE_DISABLED) { + ret = -EBUSY; + goto out; + } if (val) drvdata->stop_on_flush = true; else drvdata->stop_on_flush = false; - - return size; + ret = size; +out: + raw_spin_unlock_irqrestore(&drvdata->spinlock, flags); + return ret; } static DEVICE_ATTR_RW(stop_on_flush); -- 2.32.0

1 month

Re: [subset] [PATCH v4 0/3] coresight: add static TPDM support

by Suzuki K Poulose

On Tue, 28 Oct 2025 18:11:39 +0800, Jie Gan wrote: > The static TPDM function as a dummy source, however, it is essential > to enable the port connected to the TPDA and configure the element size. > Without this, the TPDA cannot correctly receive trace data from the > static TPDM. Since the static TPDM does not require MMIO mapping to > access its registers, a clock controller is not mandatory for its > operation. > > [...] Applied, thanks! [1/3] dt-bindings: arm: document the static TPDM compatible https://git.kernel.org/coresight/c/8d204b6f1f7a [2/3] coresight: tpdm: add static tpdm support https://git.kernel.org/coresight/c/14ae052f7947 Best regards, -- Suzuki K Poulose <suzuki.poulose(a)arm.com>

1 month

Re: [PATCH v4 3/3] arm64: dts: qcom: lemans: enable static TPDM

by Suzuki K Poulose

On 28/10/2025 10:11, Jie Gan wrote: > Enable static TPDM device for lemans. > > Reviewed-by: Konrad Dybcio <konrad.dybcio(a)oss.qualcomm.com> > Signed-off-by: Jie Gan <jie.gan(a)oss.qualcomm.com> Assuming this goes via some other tree: Acked-by: Suzuki K Poulose <suzuki.poulose(a)arm.com> > --- > arch/arm64/boot/dts/qcom/lemans.dtsi | 105 +++++++++++++++++++++++++++++++++++ > 1 file changed, 105 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/lemans.dtsi b/arch/arm64/boot/dts/qcom/lemans.dtsi > index 0b154d57ba24..8a93b353d11c 100644 > --- a/arch/arm64/boot/dts/qcom/lemans.dtsi > +++ b/arch/arm64/boot/dts/qcom/lemans.dtsi > @@ -2961,6 +2961,14 @@ funnel1_in4: endpoint { > <&apss_funnel1_out>; > }; > }; > + > + port@5 { > + reg = <5>; > + > + funnel1_in5: endpoint { > + remote-endpoint = <&dlct0_funnel_out>; > + }; > + }; > }; > }; > > @@ -3118,6 +3126,60 @@ etr1_out: endpoint { > }; > }; > > + tpda@4ad3000 { > + compatible = "qcom,coresight-tpda", "arm,primecell"; > + reg = <0x0 0x4ad3000 0x0 0x1000>; > + > + clocks = <&aoss_qmp>; > + clock-names = "apb_pclk"; > + > + in-ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@10 { > + reg = <16>; > + dlct0_tpda_in16: endpoint { > + remote-endpoint = <&turing0_funnel_out>; > + }; > + }; > + }; > + > + out-ports { > + port { > + dlct0_tpda_out: endpoint { > + remote-endpoint = > + <&dlct0_funnel_in0>; > + }; > + }; > + }; > + > + }; > + > + funnel@4ad4000 { > + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; > + reg = <0x0 0x4ad4000 0x0 0x1000>; > + > + clocks = <&aoss_qmp>; > + clock-names = "apb_pclk"; > + > + in-ports { > + port { > + dlct0_funnel_in0: endpoint { > + remote-endpoint = <&dlct0_tpda_out>; > + }; > + }; > + }; > + > + out-ports { > + port { > + dlct0_funnel_out: endpoint { > + remote-endpoint = <&funnel1_in5>; > + }; > + }; > + }; > + }; > + > funnel@4b04000 { > compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; > reg = <0x0 0x4b04000 0x0 0x1000>; > @@ -3390,6 +3452,35 @@ aoss_cti: cti@4b13000 { > clock-names = "apb_pclk"; > }; > > + funnel@4b83000 { > + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; > + reg = <0x0 0x4b83000 0x0 0x1000>; > + > + clocks = <&aoss_qmp>; > + clock-names = "apb_pclk"; > + > + in-ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@1 { > + reg = <1>; > + > + turing0_funnel_in1: endpoint { > + remote-endpoint = <&turing_llm_tpdm_out>; > + }; > + }; > + }; > + > + out-ports { > + port { > + turing0_funnel_out: endpoint { > + remote-endpoint = <&dlct0_tpda_in16>; > + }; > + }; > + }; > + }; > + > etm@6040000 { > compatible = "arm,primecell"; > reg = <0x0 0x6040000 0x0 0x1000>; > @@ -8269,6 +8360,20 @@ arch_timer: timer { > <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; > }; > > + turing-llm-tpdm { > + compatible = "qcom,coresight-static-tpdm"; > + > + qcom,cmb-element-bits = <32>; > + > + out-ports { > + port { > + turing_llm_tpdm_out: endpoint { > + remote-endpoint = <&turing0_funnel_in1>; > + }; > + }; > + }; > + }; > + > pcie0: pcie@1c00000 { > compatible = "qcom,pcie-sa8775p"; > reg = <0x0 0x01c00000 0x0 0x3000>, >

1 month

Re: [PATCH v4 2/3] coresight: tpdm: add static tpdm support

by Suzuki K Poulose

On 28/10/2025 10:11, Jie Gan wrote: > The static TPDM function as a dummy source, however, it is essential > to enable the port connected to the TPDA and configure the element size. > Without this, the TPDA cannot correctly receive trace data from the > static TPDM. Since the static TPDM does not require MMIO mapping to > access its registers, a clock controller is not mandatory for its > operation. > > Signed-off-by: Jie Gan <jie.gan(a)oss.qualcomm.com> > --- > drivers/hwtracing/coresight/coresight-tpda.c | 7 -- > drivers/hwtracing/coresight/coresight-tpdm.c | 174 ++++++++++++++++++++++----- > drivers/hwtracing/coresight/coresight-tpdm.h | 12 ++ > 3 files changed, 154 insertions(+), 39 deletions(-) > > diff --git a/drivers/hwtracing/coresight/coresight-tpda.c b/drivers/hwtracing/coresight/coresight-tpda.c > index 333b3cb23685..3a3825d27f86 100644 > --- a/drivers/hwtracing/coresight/coresight-tpda.c > +++ b/drivers/hwtracing/coresight/coresight-tpda.c > @@ -22,13 +22,6 @@ > > DEFINE_CORESIGHT_DEVLIST(tpda_devs, "tpda"); > > -static bool coresight_device_is_tpdm(struct coresight_device *csdev) > -{ > - return (coresight_is_device_source(csdev)) && > - (csdev->subtype.source_subtype == > - CORESIGHT_DEV_SUBTYPE_SOURCE_TPDM); > -} > - > static void tpda_clear_element_size(struct coresight_device *csdev) > { > struct tpda_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); > diff --git a/drivers/hwtracing/coresight/coresight-tpdm.c b/drivers/hwtracing/coresight/coresight-tpdm.c > index 7214e65097ec..0e3896c12f07 100644 > --- a/drivers/hwtracing/coresight/coresight-tpdm.c > +++ b/drivers/hwtracing/coresight/coresight-tpdm.c > @@ -470,6 +470,9 @@ static void tpdm_enable_cmb(struct tpdm_drvdata *drvdata) > */ > static void __tpdm_enable(struct tpdm_drvdata *drvdata) > { > + if (coresight_is_static_tpdm(drvdata->csdev)) > + return; > + > CS_UNLOCK(drvdata->base); > > tpdm_enable_dsb(drvdata); > @@ -532,6 +535,9 @@ static void tpdm_disable_cmb(struct tpdm_drvdata *drvdata) > /* TPDM disable operations */ > static void __tpdm_disable(struct tpdm_drvdata *drvdata) > { > + if (coresight_is_static_tpdm(drvdata->csdev)) > + return; > + > CS_UNLOCK(drvdata->base); > > tpdm_disable_dsb(drvdata); > @@ -595,6 +601,30 @@ static int tpdm_datasets_setup(struct tpdm_drvdata *drvdata) > return 0; > } > > +static int static_tpdm_datasets_setup(struct tpdm_drvdata *drvdata, struct device *dev) > +{ > + /* setup datasets for static TPDM */ > + if (fwnode_property_present(dev->fwnode, "qcom,dsb-element-bits") && > + (!drvdata->dsb)) { > + drvdata->dsb = devm_kzalloc(drvdata->dev, > + sizeof(*drvdata->dsb), GFP_KERNEL); > + > + if (!drvdata->dsb) > + return -ENOMEM; > + } > + > + if (fwnode_property_present(dev->fwnode, "qcom,cmb-element-bits") && > + (!drvdata->cmb)) { > + drvdata->cmb = devm_kzalloc(drvdata->dev, > + sizeof(*drvdata->cmb), GFP_KERNEL); > + > + if (!drvdata->cmb) > + return -ENOMEM; > + } > + > + return 0; > +} > + > static ssize_t reset_dataset_store(struct device *dev, > struct device_attribute *attr, > const char *buf, > @@ -1342,10 +1372,9 @@ static const struct attribute_group *tpdm_attr_grps[] = { > NULL, > }; > > -static int tpdm_probe(struct amba_device *adev, const struct amba_id *id) > +static int tpdm_probe(struct device *dev, struct resource *res) > { > void __iomem *base; > - struct device *dev = &adev->dev; > struct coresight_platform_data *pdata; > struct tpdm_drvdata *drvdata; > struct coresight_desc desc = { 0 }; > @@ -1354,32 +1383,37 @@ static int tpdm_probe(struct amba_device *adev, const struct amba_id *id) > pdata = coresight_get_platform_data(dev); > if (IS_ERR(pdata)) > return PTR_ERR(pdata); > - adev->dev.platform_data = pdata; > + dev->platform_data = pdata; > > /* driver data*/ > drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL); > if (!drvdata) > return -ENOMEM; > - drvdata->dev = &adev->dev; > + drvdata->dev = dev; > dev_set_drvdata(dev, drvdata); > > - base = devm_ioremap_resource(dev, &adev->res); > - if (IS_ERR(base)) > - return PTR_ERR(base); > + if (res) { > + base = devm_ioremap_resource(dev, res); > + if (IS_ERR(base)) > + return PTR_ERR(base); > > - drvdata->base = base; > + drvdata->base = base; > + ret = tpdm_datasets_setup(drvdata); > + if (ret) > + return ret; > > - ret = tpdm_datasets_setup(drvdata); > - if (ret) > - return ret; > - > - if (drvdata && tpdm_has_dsb_dataset(drvdata)) > - of_property_read_u32(drvdata->dev->of_node, > - "qcom,dsb-msrs-num", &drvdata->dsb_msr_num); > + if (drvdata && tpdm_has_dsb_dataset(drvdata)) > + of_property_read_u32(drvdata->dev->of_node, > + "qcom,dsb-msrs-num", &drvdata->dsb_msr_num); > > - if (drvdata && tpdm_has_cmb_dataset(drvdata)) > - of_property_read_u32(drvdata->dev->of_node, > - "qcom,cmb-msrs-num", &drvdata->cmb_msr_num); > + if (drvdata && tpdm_has_cmb_dataset(drvdata)) > + of_property_read_u32(drvdata->dev->of_node, > + "qcom,cmb-msrs-num", &drvdata->cmb_msr_num); minor nit: drvdata is guranteed to be !NULL, as we err out if it was. This can be fixed up as separate patch. Suzuki > + } else { > + ret = static_tpdm_datasets_setup(drvdata, dev); > + if (ret) > + return ret; > + } > > /* Set up coresight component description */ > desc.name = coresight_alloc_device_name(&tpdm_devs, dev); > @@ -1388,34 +1422,51 @@ static int tpdm_probe(struct amba_device *adev, const struct amba_id *id) > desc.type = CORESIGHT_DEV_TYPE_SOURCE; > desc.subtype.source_subtype = CORESIGHT_DEV_SUBTYPE_SOURCE_TPDM; > desc.ops = &tpdm_cs_ops; > - desc.pdata = adev->dev.platform_data; > - desc.dev = &adev->dev; > + desc.pdata = dev->platform_data; > + desc.dev = dev; > desc.access = CSDEV_ACCESS_IOMEM(base); > - desc.groups = tpdm_attr_grps; > + if (res) > + desc.groups = tpdm_attr_grps; > drvdata->csdev = coresight_register(&desc); > if (IS_ERR(drvdata->csdev)) > return PTR_ERR(drvdata->csdev); > > spin_lock_init(&drvdata->spinlock); > > - /* Decrease pm refcount when probe is done.*/ > - pm_runtime_put(&adev->dev); > - > return 0; > } > > -static void tpdm_remove(struct amba_device *adev) > +static int tpdm_remove(struct device *dev) > { > - struct tpdm_drvdata *drvdata = dev_get_drvdata(&adev->dev); > + struct tpdm_drvdata *drvdata = dev_get_drvdata(dev); > > coresight_unregister(drvdata->csdev); > + > + return 0; > +} > + > +static int dynamic_tpdm_probe(struct amba_device *adev, > + const struct amba_id *id) > +{ > + int ret; > + > + ret = tpdm_probe(&adev->dev, &adev->res); > + if (!ret) > + pm_runtime_put(&adev->dev); > + > + return ret; > +} > + > +static void dynamic_tpdm_remove(struct amba_device *adev) > +{ > + tpdm_remove(&adev->dev); > } > > /* > * Different TPDM has different periph id. > * The difference is 0-7 bits' value. So ignore 0-7 bits. > */ > -static const struct amba_id tpdm_ids[] = { > +static const struct amba_id dynamic_tpdm_ids[] = { > { > .id = 0x001f0e00, > .mask = 0x00ffff00, > @@ -1423,17 +1474,76 @@ static const struct amba_id tpdm_ids[] = { > { 0, 0, NULL }, > }; > > -static struct amba_driver tpdm_driver = { > +MODULE_DEVICE_TABLE(amba, dynamic_tpdm_ids); > + > +static struct amba_driver dynamic_tpdm_driver = { > .drv = { > .name = "coresight-tpdm", > .suppress_bind_attrs = true, > }, > - .probe = tpdm_probe, > - .id_table = tpdm_ids, > - .remove = tpdm_remove, > + .probe = dynamic_tpdm_probe, > + .id_table = dynamic_tpdm_ids, > + .remove = dynamic_tpdm_remove, > }; > > -module_amba_driver(tpdm_driver); > +static int tpdm_platform_probe(struct platform_device *pdev) > +{ > + struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); > + int ret; > + > + pm_runtime_get_noresume(&pdev->dev); > + pm_runtime_set_active(&pdev->dev); > + pm_runtime_enable(&pdev->dev); > + > + ret = tpdm_probe(&pdev->dev, res); > + pm_runtime_put(&pdev->dev); > + if (ret) > + pm_runtime_disable(&pdev->dev); > + > + return ret; > +} > + > +static void tpdm_platform_remove(struct platform_device *pdev) > +{ > + struct tpdm_drvdata *drvdata = dev_get_drvdata(&pdev->dev); > + > + if (WARN_ON(!drvdata)) > + return; > + > + tpdm_remove(&pdev->dev); > + pm_runtime_disable(&pdev->dev); > +} > + > +static const struct of_device_id static_tpdm_match[] = { > + {.compatible = "qcom,coresight-static-tpdm"}, > + {} > +}; > + > +MODULE_DEVICE_TABLE(of, static_tpdm_match); > + > +static struct platform_driver static_tpdm_driver = { > + .probe = tpdm_platform_probe, > + .remove = tpdm_platform_remove, > + .driver = { > + .name = "coresight-static-tpdm", > + .of_match_table = static_tpdm_match, > + .suppress_bind_attrs = true, > + }, > +}; > + > +static int __init tpdm_init(void) > +{ > + return coresight_init_driver("tpdm", &dynamic_tpdm_driver, &static_tpdm_driver, > + THIS_MODULE); > +} > + > +static void __exit tpdm_exit(void) > +{ > + coresight_remove_driver(&dynamic_tpdm_driver, &static_tpdm_driver); > +} > + > +module_init(tpdm_init); > +module_exit(tpdm_exit); > > MODULE_LICENSE("GPL"); > MODULE_DESCRIPTION("Trace, Profiling & Diagnostic Monitor driver"); > diff --git a/drivers/hwtracing/coresight/coresight-tpdm.h b/drivers/hwtracing/coresight/coresight-tpdm.h > index b11754389734..2867f3ab8186 100644 > --- a/drivers/hwtracing/coresight/coresight-tpdm.h > +++ b/drivers/hwtracing/coresight/coresight-tpdm.h > @@ -343,4 +343,16 @@ struct tpdm_dataset_attribute { > enum dataset_mem mem; > u32 idx; > }; > + > +static inline bool coresight_device_is_tpdm(struct coresight_device *csdev) > +{ > + return (coresight_is_device_source(csdev)) && > + (csdev->subtype.source_subtype == > + CORESIGHT_DEV_SUBTYPE_SOURCE_TPDM); > +} > + > +static inline bool coresight_is_static_tpdm(struct coresight_device *csdev) > +{ > + return (coresight_device_is_tpdm(csdev) && !csdev->access.base); > +} > #endif /* _CORESIGHT_CORESIGHT_TPDM_H */ >

1 month

Re: [PATCH v5 0/2] Add Qualcomm extended CTI support

by Mike Leach

Hi, On Mon, 3 Nov 2025 at 08:46, Yingchao Deng <yingchao.deng(a)oss.qualcomm.com> wrote: > > >Hi, > > > >This set is looking good now and appears to be getting close to being ready. > > > >There are a few minor issues in the second patch and a few items that > >need to be confirmed. > >1) I note that you removed the code to prevent calling claim/disclaim. > >Does this mean that you confirm that you have tested the patch update > >for claim tags I posted works on your system? > > I just tested this patch, the default value of qcom_cti's CLAIMSET register is 0xf, > and unlike the standard CTI (write 0 is no effect), it can be written with 0. > So, is it acceptable to write 0 to the claimset register of qcom_cti after reading the > devarch register during the probe phase? > > devarch = readl_relaxed(drvdata->base + CORESIGHT_DEVARCH); > if (CTI_DEVARCH_ARCHITECT(devarch) == ARCHITECT_QCOM) { > drvdata->subtype = QCOM_CTI; > drvdata->offsets = cti_extended_offset; > writel_relaxed(0, drvdata->base + CORESIGHT_CLAIMSET); > } else { > drvdata->subtype = ARM_STD_CTI; > drvdata->offsets = cti_normal_offset; > } > OK - if you look at v2 of the cliam tag set you will see we introduce a "claim_tag_info" attribute to the coresight_device structure. This is initially set to CS_CLAIM_TAG_UNKNOWN, and on the first claim/disclaim API call the claim tags validity will be tested and a value of CS_CLAIM_TAG_STD_PROTOCOL or CS_CLAIM_TAG_NOT_IMPL set, skipping the test on all subsequent claim calls. if you set this in the probe function i.e. csdev->claim_tag_info = CS_CLAIM_TAG_NOT_IMPL, then the claim tags will not be used. whichever method you use, please ensure a comment appears in the code describing why the workaround is necessary. Regards Mike > >2) In patch 2 I made some comments in regard to ARCH values - please > >confirm that these are accurate and have been tested as working on > >your system > > Yes, the bits 31:20 in qcom_cti's DEVARCH register are 0x8EF. > > >3) As mentioned in the comments to patch 2 - you need to update the > >docs for the new sysfs selection file you have added > > Will update in v6. > > Thanks > Yingchao > > > > >Thanks and Regards > > > >Mike > > > >On Mon, 20 Oct 2025 at 08:12, Yingchao Deng > ><yingchao.deng(a)oss.qualcomm.com> wrote: > >> > >> The QCOM extended CTI is a heavily parameterized version of ARM’s CSCTI. > >> It allows a debugger to send to trigger events to a processor or to send > >> a trigger event to one or more processors when a trigger event occurs on > >> another processor on the same SoC, or even between SoCs. > >> > >> QCOM extended CTI supports up to 128 triggers. And some of the register > >> offsets are changed. > >> > >> The commands to configure CTI triggers are the same as ARM's CTI. > >> > >> Changes in v5: > >> 1. Move common part in qcom-cti.h to coresight-cti.h. > >> 2. Convert trigger usage fields to dynamic bitmaps and arrays. > >> 3. Fix holes in struct cti_config to save some space. > >> 4. Revert the previous changes related to the claim tag in > >> cti_enable/disable_hw. > >> Link to v4 - https://lore.kernel.org/linux-arm-msm/20250902-extended_cti-v4-1-7677de04b4… > >> > >> Changes in v4: > >> 1. Read the DEVARCH registers to identify Qualcomm CTI. > >> 2. Add a reg_idx node, and refactor the coresight_cti_reg_show() and > >> coresight_cti_reg_store() functions accordingly. > >> 3. The register offsets specific to Qualcomm CTI are moved to qcom_cti.h. > >> Link to v3 - https://lore.kernel.org/linux-arm-msm/20250722081405.2947294-1-quic_jinlmao… > >> > >> Changes in v3: > >> 1. Rename is_extended_cti() to of_is_extended_cti(). > >> 2. Add the missing 'i' when write the CTI trigger registers. > >> 3. Convert the multi-line output in sysfs to single line. > >> 4. Initialize offset arrays using designated initializer. > >> Link to V2 - https://lore.kernel.org/all/20250429071841.1158315-3-quic_jinlmao@quicinc.c… > >> > >> Changes in V2: > >> 1. Add enum for compatible items. > >> 2. Move offset arrays to coresight-cti-core > >> > >> Signed-off-by: Jinlong Mao <jinlong.mao(a)oss.qualcomm.com> > >> Signed-off-by: Yingchao Deng <yingchao.deng(a)oss.qualcomm.com> > >> --- > >> Yingchao Deng (2): > >> coresight: cti: Convert trigger usage fields to dynamic bitmaps and arrays > >> coresight: cti: Add Qualcomm extended CTI support > >> > >> drivers/hwtracing/coresight/coresight-cti-core.c | 144 +++++++++++++--- > >> .../hwtracing/coresight/coresight-cti-platform.c | 16 +- > >> drivers/hwtracing/coresight/coresight-cti-sysfs.c | 184 +++++++++++++++------ > >> drivers/hwtracing/coresight/coresight-cti.h | 60 ++++++- > >> drivers/hwtracing/coresight/qcom-cti.h | 29 ++++ > >> 5 files changed, 346 insertions(+), 87 deletions(-) > >> --- > >> base-commit: 1fdbb3ff1233e204e26f9f6821ae9c125a055229 > >> change-id: 20251016-extended_cti-2a426c8894b1 > >> > >> Best regards, > >> -- > >> Yingchao Deng <yingchao.deng(a)oss.qualcomm.com> > >> -- Mike Leach Principal Engineer, ARM Ltd. Manchester Design Centre. UK

1 month

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