CoreSight

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2545 discussions

Re: [PATCH v3] coresight: ETR: Fix ETR buffer use-after-free issue

by Leo Yan

On Tue, Oct 21, 2025 at 04:45:25PM +0800, Xiaoqi Zhuang wrote: > When ETR is enabled as CS_MODE_SYSFS, if the buffer size is changed > and enabled again, currently sysfs_buf will point to the newly > allocated memory(buf_new) and free the old memory(buf_old). But the > etr_buf that is being used by the ETR remains pointed to buf_old, not > updated to buf_new. In this case, it will result in a memory > use-after-free issue. > > Fix this by checking ETR's mode before updating and releasing buf_old, > if the mode is CS_MODE_SYSFS, then skip updating and releasing it. > > Fixes: bd2767ec3df2 ("coresight: Fix run time warnings while reusing ETR buffer") > Signed-off-by: Xiaoqi Zhuang <xiaoqi.zhuang(a)oss.qualcomm.com> Tested on my Juno board with below steps: 1) Enable the first path: ETM2 -> ETR0 echo 1 > /sys/bus/coresight/devices/tmc_etr0/enable_sink echo 1 > /sys/bus/coresight/devices/etm2/enable_source 2) Enlarge buffer size from 1MiB to 4MiB cat /sys/bus/coresight/devices/tmc_etr0/buffer_size 0x100000 echo 0x400000 > /sys/bus/coresight/devices/tmc_etr0/buffer_size 3) Enable the second path: ETM0 -> ETR0 echo 1 > /sys/bus/coresight/devices/etm0/enable_source 4) Disable paths echo 0 > /sys/bus/coresight/devices/etm0/enable_source echo 0 > /sys/bus/coresight/devices/etm2/enable_source Without this patch, the oops will be triggered when disable paths. I can confirm this patch does dismiss the issue. Tested-by: Leo Yan <leo.yan(a)arm.com> > --- > Changes in v3: > - Add a fix tag for the fix patch. > - Link to v2: https://lore.kernel.org/r/20251021-fix_etr_issue-v2-1-80c40c9cac8c@oss.qual… > > Changes in v2: > - Exit earlier to avoid allocating memory unnecessarily. > - Link to v1: https://lore.kernel.org/r/20251020-fix_etr_issue-v1-1-902ab51770b4@oss.qual… > --- > drivers/hwtracing/coresight/coresight-tmc-etr.c | 7 +++++++ > 1 file changed, 7 insertions(+) > > diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtracing/coresight/coresight-tmc-etr.c > index b07fcdb3fe1a..800be06598c1 100644 > --- a/drivers/hwtracing/coresight/coresight-tmc-etr.c > +++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c > @@ -1250,6 +1250,13 @@ static struct etr_buf *tmc_etr_get_sysfs_buffer(struct coresight_device *csdev) > * with the lock released. > */ > raw_spin_lock_irqsave(&drvdata->spinlock, flags); > + > + /* > + * If the ETR is already enabled, continue with the existing buffer. > + */ > + if (coresight_get_mode(csdev) == CS_MODE_SYSFS) > + goto out; > + > sysfs_buf = READ_ONCE(drvdata->sysfs_buf); > if (!sysfs_buf || (sysfs_buf->size != drvdata->size)) { > raw_spin_unlock_irqrestore(&drvdata->spinlock, flags); > > --- > base-commit: 98ac9cc4b4452ed7e714eddc8c90ac4ae5da1a09 > change-id: 20251020-fix_etr_issue-02c706dbc899 > > Best regards, > -- > Xiaoqi Zhuang <xiaoqi.zhuang(a)oss.qualcomm.com> > >

2 weeks, 6 days

[PATCH v4 00/11] CoreSight: Refactor power management for ETMv3/4

by Leo Yan

This series is extracted from the CoreSight power management fixes and refactoring [1], focusing on ETMv3/4 power management. The remaining parts will be sent out separately. Hopefully, this makes things easier for us to review and merge. Compared to the previous version, only one new patch has been added — to retain the sequencer state for ETMv4. No other changes are included. This series has been verified on Juno-r2 platform. [1] https://lore.kernel.org/linux-arm-kernel/20250915-arm_coresight_power_manag… --- Changes in v4: - Added patch 10 for retaining sequencer state in ETMv4 driver (Mike). - Added Mike's review tags. - Added James' test tags. - Link to v3: https://lore.kernel.org/r/20250915-arm_coresight_power_management_fix-v3-0-… Changes in v3: - Fixed building failure in ETMv3 driver (kernel test robot). - Refactoring ETMv3 change for checking CPU ID (Levi). - Fixed NULL pointer issue during CPU idle (James). - Fixed lockdep complaint for HARDIRQ-safe and HARDIRA-unsafe (James). - Fixed acquiring mutex in atomic context (James). - Rebased on the latest coresight-next branch. - Link to v2: https://lore.kernel.org/r/20250701-arm_cs_pm_fix_v3-v2-0-23ebb864fcc1@arm.c… Changes in v2: - Refactored ETMv4 suspend and resume for reusing the normal enabling and disabling flows (James). - Used a per-CPU structure to maintain path pointers (James). - Supported helpers in CPU PM flows (James). - Fixed the SMP-safe access to device mode. - Fixed the context synchronization in ETMv4x driver. - Link to v1: https://lore.kernel.org/linux-arm-kernel/20250516160742.1200904-1-leo.yan@a… Signed-off-by: Leo Yan <leo.yan(a)arm.com> --- Leo Yan (11): coresight: Change device mode to atomic type coresight: etm4x: Always set tracer's device mode on target CPU coresight: etm3x: Always set tracer's device mode on target CPU coresight: etm4x: Correct polling IDLE bit coresight: etm4x: Ensure context synchronization is not ignored coresight: etm4x: Add context synchronization before enabling trace coresight: etm4x: Properly control filter in CPU idle with FEAT_TRF coresight: etm4x: Remove the state_needs_restore flag coresight: etm4x: Add flag to control single-shot restart coresight: etm4x: Retain sequencer state coresight: etm4x: Reuse normal enable and disable logic in CPU idle drivers/hwtracing/coresight/coresight-etm3x-core.c | 59 ++-- drivers/hwtracing/coresight/coresight-etm4x-core.c | 372 +++++++-------------- drivers/hwtracing/coresight/coresight-etm4x.h | 62 ---- include/linux/coresight.h | 25 +- 4 files changed, 175 insertions(+), 343 deletions(-) --- base-commit: 6fab32bb6508abbb8b7b1c5498e44f0c32320ed5 change-id: 20250909-arm_coresight_power_management_fix-139873f942e8 Best regards, -- Leo Yan <leo.yan(a)arm.com>

3 weeks, 1 day

Re: [PATCH v5 0/2] Add Qualcomm extended CTI support

by Mike Leach

Hi, This set is looking good now and appears to be getting close to being ready. There are a few minor issues in the second patch and a few items that need to be confirmed. 1) I note that you removed the code to prevent calling claim/disclaim. Does this mean that you confirm that you have tested the patch update for claim tags I posted works on your system? 2) In patch 2 I made some comments in regard to ARCH values - please confirm that these are accurate and have been tested as working on your system 3) As mentioned in the comments to patch 2 - you need to update the docs for the new sysfs selection file you have added Thanks and Regards Mike On Mon, 20 Oct 2025 at 08:12, Yingchao Deng <yingchao.deng(a)oss.qualcomm.com> wrote: > > The QCOM extended CTI is a heavily parameterized version of ARM’s CSCTI. > It allows a debugger to send to trigger events to a processor or to send > a trigger event to one or more processors when a trigger event occurs on > another processor on the same SoC, or even between SoCs. > > QCOM extended CTI supports up to 128 triggers. And some of the register > offsets are changed. > > The commands to configure CTI triggers are the same as ARM's CTI. > > Changes in v5: > 1. Move common part in qcom-cti.h to coresight-cti.h. > 2. Convert trigger usage fields to dynamic bitmaps and arrays. > 3. Fix holes in struct cti_config to save some space. > 4. Revert the previous changes related to the claim tag in > cti_enable/disable_hw. > Link to v4 - https://lore.kernel.org/linux-arm-msm/20250902-extended_cti-v4-1-7677de04b4… > > Changes in v4: > 1. Read the DEVARCH registers to identify Qualcomm CTI. > 2. Add a reg_idx node, and refactor the coresight_cti_reg_show() and > coresight_cti_reg_store() functions accordingly. > 3. The register offsets specific to Qualcomm CTI are moved to qcom_cti.h. > Link to v3 - https://lore.kernel.org/linux-arm-msm/20250722081405.2947294-1-quic_jinlmao… > > Changes in v3: > 1. Rename is_extended_cti() to of_is_extended_cti(). > 2. Add the missing 'i' when write the CTI trigger registers. > 3. Convert the multi-line output in sysfs to single line. > 4. Initialize offset arrays using designated initializer. > Link to V2 - https://lore.kernel.org/all/20250429071841.1158315-3-quic_jinlmao@quicinc.c… > > Changes in V2: > 1. Add enum for compatible items. > 2. Move offset arrays to coresight-cti-core > > Signed-off-by: Jinlong Mao <jinlong.mao(a)oss.qualcomm.com> > Signed-off-by: Yingchao Deng <yingchao.deng(a)oss.qualcomm.com> > --- > Yingchao Deng (2): > coresight: cti: Convert trigger usage fields to dynamic bitmaps and arrays > coresight: cti: Add Qualcomm extended CTI support > > drivers/hwtracing/coresight/coresight-cti-core.c | 144 +++++++++++++--- > .../hwtracing/coresight/coresight-cti-platform.c | 16 +- > drivers/hwtracing/coresight/coresight-cti-sysfs.c | 184 +++++++++++++++------ > drivers/hwtracing/coresight/coresight-cti.h | 60 ++++++- > drivers/hwtracing/coresight/qcom-cti.h | 29 ++++ > 5 files changed, 346 insertions(+), 87 deletions(-) > --- > base-commit: 1fdbb3ff1233e204e26f9f6821ae9c125a055229 > change-id: 20251016-extended_cti-2a426c8894b1 > > Best regards, > -- > Yingchao Deng <yingchao.deng(a)oss.qualcomm.com> > -- Mike Leach Principal Engineer, ARM Ltd. Manchester Design Centre. UK

3 weeks, 5 days

[PATCH 00/12] coresight: Add CPU cluster funnel/replicator/tmc support

by Yuanfang Zhang

This patch series introduces support for CPU cluster local CoreSight components, including funnel, replicator, and TMC, which reside inside CPU cluster power domains. These components require special handling due to power domain constraints. Unlike system-level CoreSight devices, CPU cluster local components share the power domain of the CPU cluster. When the cluster enters low-power mode (LPM), the registers of these components become inaccessible. Importantly, `pm_runtime_get` calls alone are insufficient to bring the CPU cluster out of LPM, making standard register access unreliable in such cases. To address this, the series introduces: - Device tree bindings for CPU cluster local funnel, replicator, and TMC. - Introduce a cpumask to record the CPUs belonging to the cluster where the cpu cluster local component resides. - Safe register access via smp_call_function_single() on CPUs within the associated cpumask, ensuring the cluster is power-resident during access. - Delayed probe support for CPU cluster local components when all CPUs of this CPU cluster are offline, re-probe the component when any CPU in the cluster comes online. - Introduce `cs_mode` to link enable interfaces to avoid the use smp_call_function_single() under perf mode. Patch summary: Patch 1: Adds device tree bindings for CPU cluster funnel/replicator/TMC devices. Patches 2–3: Add support for CPU cluster funnel. Patches 4-6: Add support for CPU cluster replicator. Patches 7-10: Add support for CPU cluster TMC. Patch 11: Add 'cs_mode' to link enable functions. Patches 12-13: Add Coresight nodes for APSS debug block for x1e80100 and fix build issue. Verification: This series has been verified on sm8750. Test steps for delay probe: 1. limit the system to enable at most 6 CPU cores during boot. 2. echo 1 >/sys/bus/cpu/devices/cpu6/online. 3. check whether ETM6 and ETM7 have been probed. Test steps for sysfs mode: echo 1 >/sys/bus/coresight/devices/tmc_etf0/enable_sink echo 1 >/sys/bus/coresight/devices/etm0/enable_source echo 1 >/sys/bus/coresight/devices/etm6/enable_source echo 0 >/sys/bus/coresight/devices/etm0/enable_source echo 0 >/sys/bus/coresight/devicse/etm6/enable_source echo 0 >/sys/bus/coresight/devices/tmc_etf0/enable_sink echo 1 >/sys/bus/coresight/devices/tmc_etf1/enable_sink echo 1 >/sys/bus/coresight/devcies/etm0/enable_source cat /dev/tmc_etf1 >/tmp/etf1.bin echo 0 >/sys/bus/coresight/devices/etm0/enable_source echo 0 >/sys/bus/coresight/devices/tmc_etf1/enable_sink echo 1 >/sys/bus/coresight/devices/tmc_etf2/enable_sink echo 1 >/sys/bus/coresight/devices/etm6/enable_source cat /dev/tmc_etf2 >/tmp/etf2.bin echo 0 >/sys/bus/coresight/devices/etm6/enable_source echo 0 >/sys/bus/coresight/devices/tmc_etf2/enable_sink Test steps for sysfs node: cat /sys/bus/coresight/devices/tmc_etf*/mgmt/* cat /sys/bus/coresight/devices/funnel*/funnel_ctrl cat /sys/bus/coresight/devices/replicator*/mgmt/* Test steps for perf mode: perf record -a -e cs_etm//k -- sleep 5 Signed-off-by: Yuanfang Zhang <yuanfang.zhang(a)oss.qualcomm.com> --- Yuanfang Zhang (12): dt-bindings: arm: coresight: Add cpu cluster tmc/funnel/replicator support coresight-funnel: Add support for CPU cluster funnel coresight-funnel: Handle delay probe for CPU cluster funnel coresight-replicator: Add support for CPU cluster replicator coresight-replicator: Handle delayed probe for CPU cluster replicator coresight-replicator: Update mgmt_attrs for CPU cluster replicator compatibility coresight-tmc: Add support for CPU cluster ETF and refactor probe flow coresight-tmc-etf: Refactor enable function for CPU cluster ETF support coresight-tmc: Update tmc_mgmt_attrs for CPU cluster TMC compatibility coresight-tmc: Handle delayed probe for CPU cluster TMC coresight: add 'cs_mode' to link enable functions arm64: dts: qcom: x1e80100: add Coresight nodes for APSS debug block .../bindings/arm/arm,coresight-dynamic-funnel.yaml | 23 +- .../arm/arm,coresight-dynamic-replicator.yaml | 22 +- .../devicetree/bindings/arm/arm,coresight-tmc.yaml | 22 +- arch/arm64/boot/dts/qcom/x1e80100.dtsi | 885 +++++++++++++++++++++ arch/arm64/boot/dts/qcom/x1p42100.dtsi | 12 + drivers/hwtracing/coresight/coresight-core.c | 7 +- drivers/hwtracing/coresight/coresight-funnel.c | 260 +++++- drivers/hwtracing/coresight/coresight-replicator.c | 343 +++++++- drivers/hwtracing/coresight/coresight-tmc-core.c | 396 +++++++-- drivers/hwtracing/coresight/coresight-tmc-etf.c | 105 ++- drivers/hwtracing/coresight/coresight-tmc.h | 10 + drivers/hwtracing/coresight/coresight-tnoc.c | 3 +- drivers/hwtracing/coresight/coresight-tpda.c | 3 +- include/linux/coresight.h | 3 +- 14 files changed, 1912 insertions(+), 182 deletions(-) --- base-commit: 01f96b812526a2c8dcd5c0e510dda37e09ec8bcd change-id: 20251016-cpu_cluster_component_pm-ce518f510433 Best regards, -- Yuanfang Zhang <yuanfang.zhang(a)oss.qualcomm.com>

3 weeks, 5 days

Re: [PATCH v5 2/2] coresight: cti: Add Qualcomm extended CTI support

by Mike Leach

Hi, On Mon, 20 Oct 2025 at 08:12, Yingchao Deng <yingchao.deng(a)oss.qualcomm.com> wrote: > > The QCOM extended CTI is a heavily parameterized version of ARM’s CSCTI. > It allows a debugger to send to trigger events to a processor or to send > a trigger event to one or more processors when a trigger event occurs > on another processor on the same SoC, or even between SoCs. Qualcomm CTI > implementation differs from the standard CTI in the following aspects: > > 1. The number of supported triggers is extended to 128. > 2. Several register offsets differ from the CoreSight specification. > > Signed-off-by: Jinlong Mao <jinglong.mao(a)oss.qualcomm.com> > Signed-off-by: Yingchao Deng <yingchao.deng(a)oss.qualcomm.com> > --- > drivers/hwtracing/coresight/coresight-cti-core.c | 86 +++++++++-- > drivers/hwtracing/coresight/coresight-cti-sysfs.c | 174 +++++++++++++++++----- > drivers/hwtracing/coresight/coresight-cti.h | 43 +++++- > drivers/hwtracing/coresight/qcom-cti.h | 29 ++++ > 4 files changed, 281 insertions(+), 51 deletions(-) > > diff --git a/drivers/hwtracing/coresight/coresight-cti-core.c b/drivers/hwtracing/coresight/coresight-cti-core.c > index 8c9cec832898..5330db7eecf1 100644 > --- a/drivers/hwtracing/coresight/coresight-cti-core.c > +++ b/drivers/hwtracing/coresight/coresight-cti-core.c > @@ -21,6 +21,55 @@ > > #include "coresight-priv.h" > #include "coresight-cti.h" > +#include "qcom-cti.h" > + > +static const u32 cti_normal_offset[] = { > + [INDEX_CTIINTACK] = CTIINTACK, > + [INDEX_CTIAPPSET] = CTIAPPSET, > + [INDEX_CTIAPPCLEAR] = CTIAPPCLEAR, > + [INDEX_CTIAPPPULSE] = CTIAPPPULSE, > + [INDEX_CTIINEN] = CTIINEN(0), > + [INDEX_CTIOUTEN] = CTIOUTEN(0), > + [INDEX_CTITRIGINSTATUS] = CTITRIGINSTATUS, > + [INDEX_CTITRIGOUTSTATUS] = CTITRIGOUTSTATUS, > + [INDEX_CTICHINSTATUS] = CTICHINSTATUS, > + [INDEX_CTICHOUTSTATUS] = CTICHOUTSTATUS, > + [INDEX_CTIGATE] = CTIGATE, > + [INDEX_ASICCTL] = ASICCTL, > + [INDEX_ITCHINACK] = ITCHINACK, > + [INDEX_ITTRIGINACK] = ITTRIGINACK, > + [INDEX_ITCHOUT] = ITCHOUT, > + [INDEX_ITTRIGOUT] = ITTRIGOUT, > + [INDEX_ITCHOUTACK] = ITCHOUTACK, > + [INDEX_ITTRIGOUTACK] = ITTRIGOUTACK, > + [INDEX_ITCHIN] = ITCHIN, > + [INDEX_ITTRIGIN] = ITTRIGIN, > + [INDEX_ITCTRL] = CORESIGHT_ITCTRL, > +}; > + > +static const u32 cti_extended_offset[] = { > + [INDEX_CTIINTACK] = QCOM_CTIINTACK, > + [INDEX_CTIAPPSET] = QCOM_CTIAPPSET, > + [INDEX_CTIAPPCLEAR] = QCOM_CTIAPPCLEAR, > + [INDEX_CTIAPPPULSE] = QCOM_CTIAPPPULSE, > + [INDEX_CTIINEN] = QCOM_CTIINEN, > + [INDEX_CTIOUTEN] = QCOM_CTIOUTEN, > + [INDEX_CTITRIGINSTATUS] = QCOM_CTITRIGINSTATUS, > + [INDEX_CTITRIGOUTSTATUS] = QCOM_CTITRIGOUTSTATUS, > + [INDEX_CTICHINSTATUS] = QCOM_CTICHINSTATUS, > + [INDEX_CTICHOUTSTATUS] = QCOM_CTICHOUTSTATUS, > + [INDEX_CTIGATE] = QCOM_CTIGATE, > + [INDEX_ASICCTL] = QCOM_ASICCTL, > + [INDEX_ITCHINACK] = QCOM_ITCHINACK, > + [INDEX_ITTRIGINACK] = QCOM_ITTRIGINACK, > + [INDEX_ITCHOUT] = QCOM_ITCHOUT, > + [INDEX_ITTRIGOUT] = QCOM_ITTRIGOUT, > + [INDEX_ITCHOUTACK] = QCOM_ITCHOUTACK, > + [INDEX_ITTRIGOUTACK] = QCOM_ITTRIGOUTACK, > + [INDEX_ITCHIN] = QCOM_ITCHIN, > + [INDEX_ITTRIGIN] = QCOM_ITTRIGIN, > + [INDEX_ITCTRL] = CORESIGHT_ITCTRL, > +}; > > /* > * CTI devices can be associated with a PE, or be connected to CoreSight > @@ -70,15 +119,16 @@ void cti_write_all_hw_regs(struct cti_drvdata *drvdata) > > /* write the CTI trigger registers */ > for (i = 0; i < config->nr_trig_max; i++) { > - writel_relaxed(config->ctiinen[i], drvdata->base + CTIINEN(i)); > + writel_relaxed(config->ctiinen[i], > + drvdata->base + cti_offset(drvdata, INDEX_CTIINEN, i)); > writel_relaxed(config->ctiouten[i], > - drvdata->base + CTIOUTEN(i)); > + drvdata->base + cti_offset(drvdata, INDEX_CTIOUTEN, i)); > } > > /* other regs */ > - writel_relaxed(config->ctigate, drvdata->base + CTIGATE); > - writel_relaxed(config->asicctl, drvdata->base + ASICCTL); > - writel_relaxed(config->ctiappset, drvdata->base + CTIAPPSET); > + writel_relaxed(config->ctigate, drvdata->base + cti_offset(drvdata, INDEX_CTIGATE, 0)); > + writel_relaxed(config->asicctl, drvdata->base + cti_offset(drvdata, INDEX_ASICCTL, 0)); > + writel_relaxed(config->ctiappset, drvdata->base + cti_offset(drvdata, INDEX_CTIAPPSET, 0)); > > /* re-enable CTI */ > writel_relaxed(1, drvdata->base + CTICONTROL); > @@ -214,6 +264,9 @@ void cti_write_intack(struct device *dev, u32 ackval) > /* DEVID[19:16] - number of CTM channels */ > #define CTI_DEVID_CTMCHANNELS(devid_val) ((int) BMVAL(devid_val, 16, 19)) > > +/* DEVARCH[31:21] - ARCHITECT */ > +#define CTI_DEVARCH_ARCHITECT(devarch_val) ((int)BMVAL(devarch_val, 21, 31)) > + > static int cti_set_default_config(struct device *dev, > struct cti_drvdata *drvdata) > { > @@ -394,8 +447,8 @@ int cti_channel_trig_op(struct device *dev, enum cti_chan_op op, > > /* update the local register values */ > chan_bitmask = BIT(channel_idx); > - reg_offset = (direction == CTI_TRIG_IN ? CTIINEN(trigger_idx) : > - CTIOUTEN(trigger_idx)); > + reg_offset = (direction == CTI_TRIG_IN ? cti_offset(drvdata, INDEX_CTIINEN, trigger_idx) : > + cti_offset(drvdata, INDEX_CTIOUTEN, trigger_idx)); > > raw_spin_lock(&drvdata->spinlock); > > @@ -479,19 +532,19 @@ int cti_channel_setop(struct device *dev, enum cti_chan_set_op op, > case CTI_CHAN_SET: > config->ctiappset |= chan_bitmask; > reg_value = config->ctiappset; > - reg_offset = CTIAPPSET; > + reg_offset = cti_offset(drvdata, INDEX_CTIAPPSET, 0); > break; > > case CTI_CHAN_CLR: > config->ctiappset &= ~chan_bitmask; > reg_value = chan_bitmask; > - reg_offset = CTIAPPCLEAR; > + reg_offset = cti_offset(drvdata, INDEX_CTIAPPCLEAR, 0); > break; > > case CTI_CHAN_PULSE: > config->ctiappset &= ~chan_bitmask; > reg_value = chan_bitmask; > - reg_offset = CTIAPPPULSE; > + reg_offset = cti_offset(drvdata, INDEX_CTIAPPPULSE, 0); > break; > > default: > @@ -894,6 +947,7 @@ static int cti_probe(struct amba_device *adev, const struct amba_id *id) > struct coresight_desc cti_desc; > struct coresight_platform_data *pdata = NULL; > struct resource *res = &adev->res; > + u32 devarch; > > /* driver data*/ > drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL); > @@ -980,9 +1034,19 @@ static int cti_probe(struct amba_device *adev, const struct amba_id *id) > drvdata->csdev_release = drvdata->csdev->dev.release; > drvdata->csdev->dev.release = cti_device_release; > > + /* qcom_cti*/ perhaps this comment could be "check architect value"? > + devarch = readl_relaxed(drvdata->base + CORESIGHT_DEVARCH); > + if (CTI_DEVARCH_ARCHITECT(devarch) == ARCHITECT_QCOM) { > + drvdata->subtype = QCOM_CTI; > + drvdata->offsets = cti_extended_offset; > + } else { > + drvdata->subtype = ARM_STD_CTI; > + drvdata->offsets = cti_normal_offset; > + } > + > /* all done - dec pm refcount */ > pm_runtime_put(&adev->dev); > - dev_info(&drvdata->csdev->dev, "CTI initialized\n"); > + dev_info(&drvdata->csdev->dev, "CTI initialized %d\n", drvdata->subtype); Here extend string to "CTI Intialized; subtype=%d\n" > return 0; > > pm_release: > diff --git a/drivers/hwtracing/coresight/coresight-cti-sysfs.c b/drivers/hwtracing/coresight/coresight-cti-sysfs.c > index a9df77215141..88fd1c9c0101 100644 > --- a/drivers/hwtracing/coresight/coresight-cti-sysfs.c > +++ b/drivers/hwtracing/coresight/coresight-cti-sysfs.c > @@ -172,9 +172,8 @@ static struct attribute *coresight_cti_attrs[] = { > > /* register based attributes */ > > -/* Read registers with power check only (no enable check). */ > -static ssize_t coresight_cti_reg_show(struct device *dev, > - struct device_attribute *attr, char *buf) > +static ssize_t coresight_cti_mgmt_reg_show(struct device *dev, > + struct device_attribute *attr, char *buf) > { > struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent); > struct cs_off_attribute *cti_attr = container_of(attr, struct cs_off_attribute, attr); > @@ -189,6 +188,39 @@ static ssize_t coresight_cti_reg_show(struct device *dev, > return sysfs_emit(buf, "0x%x\n", val); > } > > +/* Read registers with power check only (no enable check). */ > +static ssize_t coresight_cti_reg_show(struct device *dev, > + struct device_attribute *attr, char *buf) > +{ > + struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent); > + struct cs_off_attribute *cti_attr = container_of(attr, struct cs_off_attribute, attr); > + u32 val = 0, idx = drvdata->config.regs_idx; This needs to be inside the spin lock > + > + pm_runtime_get_sync(dev->parent); > + raw_spin_lock(&drvdata->spinlock); > + if (drvdata->config.hw_powered) { > + switch (cti_attr->off) { > + case INDEX_CTITRIGINSTATUS: > + case INDEX_CTITRIGOUTSTATUS: > + case INDEX_ITTRIGINACK: > + case INDEX_ITTRIGOUT: > + case INDEX_ITTRIGOUTACK: > + case INDEX_ITTRIGIN: > + val = readl_relaxed(drvdata->base + > + cti_offset(drvdata, cti_attr->off, idx)); > + break; > + > + default: > + val = readl_relaxed(drvdata->base + cti_offset(drvdata, cti_attr->off, 0)); > + break; > + } > + } > + > + raw_spin_unlock(&drvdata->spinlock); > + pm_runtime_put_sync(dev->parent); > + return sysfs_emit(buf, "0x%x\n", val); > +} > + > /* Write registers with power check only (no enable check). */ > static __maybe_unused ssize_t coresight_cti_reg_store(struct device *dev, > struct device_attribute *attr, > @@ -197,19 +229,38 @@ static __maybe_unused ssize_t coresight_cti_reg_store(struct device *dev, > struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent); > struct cs_off_attribute *cti_attr = container_of(attr, struct cs_off_attribute, attr); > unsigned long val = 0; > + u32 idx = drvdata->config.regs_idx; > this needs to be inside the spinlock > if (kstrtoul(buf, 0, &val)) > return -EINVAL; > > pm_runtime_get_sync(dev->parent); > raw_spin_lock(&drvdata->spinlock); > - if (drvdata->config.hw_powered) > - cti_write_single_reg(drvdata, cti_attr->off, val); > + if (drvdata->config.hw_powered) { > + switch (cti_attr->off) { > + case INDEX_ITTRIGINACK: > + case INDEX_ITTRIGOUT: > + cti_write_single_reg(drvdata, cti_offset(drvdata, cti_attr->off, idx), val); > + break; > + > + default: > + cti_write_single_reg(drvdata, cti_offset(drvdata, cti_attr->off, 0), val); > + break; > + } > + } > raw_spin_unlock(&drvdata->spinlock); > pm_runtime_put_sync(dev->parent); > return size; > } > > +#define coresight_cti_mgmt_reg(name, offset) \ > + (&((struct cs_off_attribute[]) { \ > + { \ > + __ATTR(name, 0444, coresight_cti_mgmt_reg_show, NULL), \ > + offset \ > + } \ > + })[0].attr.attr) > + > #define coresight_cti_reg(name, offset) \ > (&((struct cs_off_attribute[]) { \ > { \ > @@ -237,17 +288,17 @@ static __maybe_unused ssize_t coresight_cti_reg_store(struct device *dev, > > /* coresight management registers */ > static struct attribute *coresight_cti_mgmt_attrs[] = { > - coresight_cti_reg(devaff0, CTIDEVAFF0), > - coresight_cti_reg(devaff1, CTIDEVAFF1), > - coresight_cti_reg(authstatus, CORESIGHT_AUTHSTATUS), > - coresight_cti_reg(devarch, CORESIGHT_DEVARCH), > - coresight_cti_reg(devid, CORESIGHT_DEVID), > - coresight_cti_reg(devtype, CORESIGHT_DEVTYPE), > - coresight_cti_reg(pidr0, CORESIGHT_PERIPHIDR0), > - coresight_cti_reg(pidr1, CORESIGHT_PERIPHIDR1), > - coresight_cti_reg(pidr2, CORESIGHT_PERIPHIDR2), > - coresight_cti_reg(pidr3, CORESIGHT_PERIPHIDR3), > - coresight_cti_reg(pidr4, CORESIGHT_PERIPHIDR4), > + coresight_cti_mgmt_reg(devaff0, CTIDEVAFF0), > + coresight_cti_mgmt_reg(devaff1, CTIDEVAFF1), > + coresight_cti_mgmt_reg(authstatus, CORESIGHT_AUTHSTATUS), > + coresight_cti_mgmt_reg(devarch, CORESIGHT_DEVARCH), > + coresight_cti_mgmt_reg(devid, CORESIGHT_DEVID), > + coresight_cti_mgmt_reg(devtype, CORESIGHT_DEVTYPE), > + coresight_cti_mgmt_reg(pidr0, CORESIGHT_PERIPHIDR0), > + coresight_cti_mgmt_reg(pidr1, CORESIGHT_PERIPHIDR1), > + coresight_cti_mgmt_reg(pidr2, CORESIGHT_PERIPHIDR2), > + coresight_cti_mgmt_reg(pidr3, CORESIGHT_PERIPHIDR3), > + coresight_cti_mgmt_reg(pidr4, CORESIGHT_PERIPHIDR4), > NULL, > }; > > @@ -258,13 +309,15 @@ static struct attribute *coresight_cti_mgmt_attrs[] = { > * If inaccessible & pcached_val not NULL then show cached value. > */ > static ssize_t cti_reg32_show(struct device *dev, char *buf, > - u32 *pcached_val, int reg_offset) > + u32 *pcached_val, int index) > { > u32 val = 0; > struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent); > struct cti_config *config = &drvdata->config; > + int reg_offset; > > raw_spin_lock(&drvdata->spinlock); > + reg_offset = cti_offset(drvdata, index, 0); > if ((reg_offset >= 0) && cti_active(config)) { > CS_UNLOCK(drvdata->base); > val = readl_relaxed(drvdata->base + reg_offset); > @@ -284,11 +337,12 @@ static ssize_t cti_reg32_show(struct device *dev, char *buf, > * if reg_offset >= 0 then write through if enabled. > */ > static ssize_t cti_reg32_store(struct device *dev, const char *buf, > - size_t size, u32 *pcached_val, int reg_offset) > + size_t size, u32 *pcached_val, int index) > { > unsigned long val; > struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent); > struct cti_config *config = &drvdata->config; > + int reg_offset; > > if (kstrtoul(buf, 0, &val)) > return -EINVAL; > @@ -298,6 +352,7 @@ static ssize_t cti_reg32_store(struct device *dev, const char *buf, > if (pcached_val) > *pcached_val = (u32)val; > > + reg_offset = cti_offset(drvdata, index, 0); > /* write through if offset and enabled */ > if ((reg_offset >= 0) && cti_active(config)) > cti_write_single_reg(drvdata, reg_offset, val); > @@ -306,14 +361,14 @@ static ssize_t cti_reg32_store(struct device *dev, const char *buf, > } > > /* Standard macro for simple rw cti config registers */ > -#define cti_config_reg32_rw(name, cfgname, offset) \ > +#define cti_config_reg32_rw(name, cfgname, index) \ > static ssize_t name##_show(struct device *dev, \ > struct device_attribute *attr, \ > char *buf) \ > { \ > struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent); \ > return cti_reg32_show(dev, buf, \ > - &drvdata->config.cfgname, offset); \ > + &drvdata->config.cfgname, index); \ > } \ > \ > static ssize_t name##_store(struct device *dev, \ > @@ -322,7 +377,7 @@ static ssize_t name##_store(struct device *dev, \ > { \ > struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent); \ > return cti_reg32_store(dev, buf, size, \ > - &drvdata->config.cfgname, offset); \ > + &drvdata->config.cfgname, index); \ > } \ > static DEVICE_ATTR_RW(name) > > @@ -356,6 +411,46 @@ static ssize_t inout_sel_store(struct device *dev, > } > static DEVICE_ATTR_RW(inout_sel); > > +/* > + * QCOM CTI supports up to 128 triggers, there are 6 registers need to be > + * expanded to up to 4 instances, and regs_idx can be used to indicate which > + * one is in use. > + * CTITRIGINSTATUS, CTITRIGOUTSTATUS, > + * ITTRIGIN, ITTRIGOUT, > + * ITTRIGINACK, ITTRIGOUTACK. All the other selection indexes are of the form xxx_sel - this should be something along the lines of "ext_reg_sel" for consistency Additionally this information needs to appear as an entry in the documentation file Documentation/ABI/testing/sysfs-bus-coresight-devices-cti so users are aware of which registers this select relates to. > + */ > +static ssize_t regs_idx_show(struct device *dev, > + struct device_attribute *attr, > + char *buf) > +{ > + u32 val; > + struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent); > + > + raw_spin_lock(&drvdata->spinlock); > + val = drvdata->config.regs_idx; > + raw_spin_unlock(&drvdata->spinlock); > + return sprintf(buf, "%d\n", val); > +} > + > +static ssize_t regs_idx_store(struct device *dev, > + struct device_attribute *attr, > + const char *buf, size_t size) > +{ > + unsigned long val; > + struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent); > + > + if (kstrtoul(buf, 0, &val)) > + return -EINVAL; > + if (val > ((drvdata->config.nr_trig_max + 31) / 32 - 1)) > + return -EINVAL; > + > + raw_spin_lock(&drvdata->spinlock); > + drvdata->config.regs_idx = val; > + raw_spin_unlock(&drvdata->spinlock); > + return size; > +} > +static DEVICE_ATTR_RW(regs_idx); see above - cheange to ..._sel > + > static ssize_t inen_show(struct device *dev, > struct device_attribute *attr, > char *buf) > @@ -389,7 +484,7 @@ static ssize_t inen_store(struct device *dev, > > /* write through if enabled */ > if (cti_active(config)) > - cti_write_single_reg(drvdata, CTIINEN(index), val); > + cti_write_single_reg(drvdata, cti_offset(drvdata, INDEX_CTIINEN, index), val); > raw_spin_unlock(&drvdata->spinlock); > return size; > } > @@ -428,7 +523,7 @@ static ssize_t outen_store(struct device *dev, > > /* write through if enabled */ > if (cti_active(config)) > - cti_write_single_reg(drvdata, CTIOUTEN(index), val); > + cti_write_single_reg(drvdata, cti_offset(drvdata, INDEX_CTIOUTEN, index), val); > raw_spin_unlock(&drvdata->spinlock); > return size; > } > @@ -448,9 +543,9 @@ static ssize_t intack_store(struct device *dev, > } > static DEVICE_ATTR_WO(intack); > > -cti_config_reg32_rw(gate, ctigate, CTIGATE); > -cti_config_reg32_rw(asicctl, asicctl, ASICCTL); > -cti_config_reg32_rw(appset, ctiappset, CTIAPPSET); > +cti_config_reg32_rw(gate, ctigate, INDEX_CTIGATE); > +cti_config_reg32_rw(asicctl, asicctl, INDEX_ASICCTL); > +cti_config_reg32_rw(appset, ctiappset, INDEX_CTIAPPSET); > > static ssize_t appclear_store(struct device *dev, > struct device_attribute *attr, > @@ -504,6 +599,7 @@ static DEVICE_ATTR_WO(apppulse); > */ > static struct attribute *coresight_cti_regs_attrs[] = { > &dev_attr_inout_sel.attr, > + &dev_attr_regs_idx.attr, > &dev_attr_inen.attr, > &dev_attr_outen.attr, > &dev_attr_gate.attr, > @@ -512,20 +608,20 @@ static struct attribute *coresight_cti_regs_attrs[] = { > &dev_attr_appset.attr, > &dev_attr_appclear.attr, > &dev_attr_apppulse.attr, > - coresight_cti_reg(triginstatus, CTITRIGINSTATUS), > - coresight_cti_reg(trigoutstatus, CTITRIGOUTSTATUS), > - coresight_cti_reg(chinstatus, CTICHINSTATUS), > - coresight_cti_reg(choutstatus, CTICHOUTSTATUS), > + coresight_cti_reg(triginstatus, INDEX_CTITRIGINSTATUS), > + coresight_cti_reg(trigoutstatus, INDEX_CTITRIGOUTSTATUS), > + coresight_cti_reg(chinstatus, INDEX_CTICHINSTATUS), > + coresight_cti_reg(choutstatus, INDEX_CTICHOUTSTATUS), > #ifdef CONFIG_CORESIGHT_CTI_INTEGRATION_REGS > - coresight_cti_reg_rw(itctrl, CORESIGHT_ITCTRL), > - coresight_cti_reg(ittrigin, ITTRIGIN), > - coresight_cti_reg(itchin, ITCHIN), > - coresight_cti_reg_rw(ittrigout, ITTRIGOUT), > - coresight_cti_reg_rw(itchout, ITCHOUT), > - coresight_cti_reg(itchoutack, ITCHOUTACK), > - coresight_cti_reg(ittrigoutack, ITTRIGOUTACK), > - coresight_cti_reg_wo(ittriginack, ITTRIGINACK), > - coresight_cti_reg_wo(itchinack, ITCHINACK), > + coresight_cti_reg_rw(itctrl, INDEX_ITCTRL), > + coresight_cti_reg(ittrigin, INDEX_ITTRIGIN), > + coresight_cti_reg(itchin, INDEX_ITCHIN), > + coresight_cti_reg_rw(ittrigout, INDEX_ITTRIGOUT), > + coresight_cti_reg_rw(itchout, INDEX_ITCHOUT), > + coresight_cti_reg(itchoutack, INDEX_ITCHOUTACK), > + coresight_cti_reg(ittrigoutack, INDEX_ITTRIGOUTACK), > + coresight_cti_reg_wo(ittriginack, INDEX_ITTRIGINACK), > + coresight_cti_reg_wo(itchinack, INDEX_ITCHINACK), > #endif > NULL, > }; > diff --git a/drivers/hwtracing/coresight/coresight-cti.h b/drivers/hwtracing/coresight/coresight-cti.h > index 0bd71407ef34..034d6fd1590b 100644 > --- a/drivers/hwtracing/coresight/coresight-cti.h > +++ b/drivers/hwtracing/coresight/coresight-cti.h > @@ -57,7 +57,38 @@ struct fwnode_handle; > * Max of in and out defined in the DEVID register. > * - pick up actual number used from .dts parameters if present. > */ > -#define CTIINOUTEN_MAX 32 > +#define CTIINOUTEN_MAX 128 > + > +/* Qcom CTI supports up to 128 triggers*/ > +enum cti_subtype { > + ARM_STD_CTI, > + QCOM_CTI, > +}; > + > +/* These registers are remapped in Qcom CTI*/ > +enum cti_offset_index { > + INDEX_CTIINTACK, > + INDEX_CTIAPPSET, > + INDEX_CTIAPPCLEAR, > + INDEX_CTIAPPPULSE, > + INDEX_CTIINEN, > + INDEX_CTIOUTEN, > + INDEX_CTITRIGINSTATUS, > + INDEX_CTITRIGOUTSTATUS, > + INDEX_CTICHINSTATUS, > + INDEX_CTICHOUTSTATUS, > + INDEX_CTIGATE, > + INDEX_ASICCTL, > + INDEX_ITCHINACK, > + INDEX_ITTRIGINACK, > + INDEX_ITCHOUT, > + INDEX_ITTRIGOUT, > + INDEX_ITCHOUTACK, > + INDEX_ITTRIGOUTACK, > + INDEX_ITCHIN, > + INDEX_ITTRIGIN, > + INDEX_ITCTRL, > +}; > > /** > * Group of related trigger signals > @@ -149,6 +180,9 @@ struct cti_config { > bool trig_filter_enable; > u8 xtrig_rchan_sel; > > + /* qcom_cti regs' index */ > + u8 regs_idx; rename to ..._sel as per comments above. This value also needs to be reset in the chan_xtrigs_reset_store() function in coresight-cti-sysfs.c > + > /* cti cross trig programmable regs */ > u8 ctiinout_sel; > u32 ctiappset; > @@ -181,6 +215,8 @@ struct cti_drvdata { > struct cti_config config; > struct list_head node; > void (*csdev_release)(struct device *dev); > + enum cti_subtype subtype; > + const u32 *offsets; > }; > > /* > @@ -234,6 +270,11 @@ struct coresight_platform_data * > coresight_cti_get_platform_data(struct device *dev); > const char *cti_plat_get_node_name(struct fwnode_handle *fwnode); > > +static inline u32 cti_offset(struct cti_drvdata *drvdata, int index, int num) > +{ > + return drvdata->offsets[index] + 4 * num; > +} > + > /* cti powered and enabled */ > static inline bool cti_active(struct cti_config *cfg) > { > diff --git a/drivers/hwtracing/coresight/qcom-cti.h b/drivers/hwtracing/coresight/qcom-cti.h > new file mode 100644 > index 000000000000..eaa551ff118a > --- /dev/null > +++ b/drivers/hwtracing/coresight/qcom-cti.h > @@ -0,0 +1,29 @@ > +/* SPDX-License-Identifier: GPL-2.0-only > + * > + * Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved. > + */ > + > +#define ARCHITECT_QCOM 0x477 > + This value which is an 11 bit value, in bits 31:21 of the DEVARCH register, is co-incidentally the same as the top 12 bits 31:20 of the ARM DEVARCH register for standard ARM component. Bit 20 of DEVARCH is 1'b1 for present - the 11 bits 31:21 make the archiitect value. ARMs assigned JEDEC architect value 11h'23B which when shifted left by one and ORed with bit 20 gives a value of 12h'477 for bits 31:20. Assuming that your 11 bit JEDEC architect value is 0x477 then the top 12 bits of the qcom devarch register must be 12h'8EF I'd like to be sure that no errors have been made, please confim that bits 31:20 in your DEVARCH register are 0x8EF, and this patch has been tested as working on your system. Thanks and Regards Mike > +/* CTI programming registers */ > +#define QCOM_CTIINTACK 0x020 > +#define QCOM_CTIAPPSET 0x004 > +#define QCOM_CTIAPPCLEAR 0x008 > +#define QCOM_CTIAPPPULSE 0x00C > +#define QCOM_CTIINEN 0x400 > +#define QCOM_CTIOUTEN 0x800 > +#define QCOM_CTITRIGINSTATUS 0x040 > +#define QCOM_CTITRIGOUTSTATUS 0x060 > +#define QCOM_CTICHINSTATUS 0x080 > +#define QCOM_CTICHOUTSTATUS 0x084 > +#define QCOM_CTIGATE 0x088 > +#define QCOM_ASICCTL 0x08c > +/* Integration test registers */ > +#define QCOM_ITCHINACK 0xE70 > +#define QCOM_ITTRIGINACK 0xE80 > +#define QCOM_ITCHOUT 0xE74 > +#define QCOM_ITTRIGOUT 0xEA0 > +#define QCOM_ITCHOUTACK 0xE78 > +#define QCOM_ITTRIGOUTACK 0xEC0 > +#define QCOM_ITCHIN 0xE7C > +#define QCOM_ITTRIGIN 0xEE0 > > -- > 2.43.0 > -- Mike Leach Principal Engineer, ARM Ltd. Manchester Design Centre. UK

3 weeks, 5 days

Re: [PATCH v5 1/2] coresight: cti: Convert trigger usage fields to dynamic bitmaps and arrays

by Mike Leach

Hi, On Mon, 20 Oct 2025 at 08:12, Yingchao Deng <yingchao.deng(a)oss.qualcomm.com> wrote: > > Replace the fixed-size u32 fields in the cti_config and cti_trig_grp > structure with dynamically allocated bitmaps and arrays. This allows > memory to be allocated based on the actual number of triggers during probe > time, reducing memory footprint and improving scalability for platforms > with varying trigger counts. > Additionally, repack struct cti_config to reduce its size from 80 bytes to > 72 bytes. > > Signed-off-by: Yingchao Deng <yingchao.deng(a)oss.qualcomm.com> > --- > drivers/hwtracing/coresight/coresight-cti-core.c | 58 ++++++++++++++++------ > .../hwtracing/coresight/coresight-cti-platform.c | 16 +++--- > drivers/hwtracing/coresight/coresight-cti-sysfs.c | 10 ++-- > drivers/hwtracing/coresight/coresight-cti.h | 17 ++++--- > 4 files changed, 65 insertions(+), 36 deletions(-) > > diff --git a/drivers/hwtracing/coresight/coresight-cti-core.c b/drivers/hwtracing/coresight/coresight-cti-core.c > index 8fb30dd73fd2..8c9cec832898 100644 > --- a/drivers/hwtracing/coresight/coresight-cti-core.c > +++ b/drivers/hwtracing/coresight/coresight-cti-core.c > @@ -214,8 +214,8 @@ void cti_write_intack(struct device *dev, u32 ackval) > /* DEVID[19:16] - number of CTM channels */ > #define CTI_DEVID_CTMCHANNELS(devid_val) ((int) BMVAL(devid_val, 16, 19)) > > -static void cti_set_default_config(struct device *dev, > - struct cti_drvdata *drvdata) > +static int cti_set_default_config(struct device *dev, > + struct cti_drvdata *drvdata) > { > struct cti_config *config = &drvdata->config; > u32 devid; > @@ -234,12 +234,33 @@ static void cti_set_default_config(struct device *dev, > config->nr_trig_max = CTIINOUTEN_MAX; > } > > + config->trig_in_use = devm_bitmap_zalloc(dev, config->nr_trig_max, GFP_KERNEL); > + if (!config->trig_in_use) > + return -ENOMEM; > + > + config->trig_out_use = devm_bitmap_zalloc(dev, config->nr_trig_max, GFP_KERNEL); > + if (!config->trig_out_use) > + return -ENOMEM; > + > + config->trig_out_filter = devm_bitmap_zalloc(dev, config->nr_trig_max, GFP_KERNEL); > + if (!config->trig_out_filter) > + return -ENOMEM; > + > + config->ctiinen = devm_kcalloc(dev, config->nr_trig_max, sizeof(u32), GFP_KERNEL); > + if (!config->ctiinen) > + return -ENOMEM; > + > + config->ctiouten = devm_kcalloc(dev, config->nr_trig_max, sizeof(u32), GFP_KERNEL); > + if (!config->ctiouten) > + return -ENOMEM; > + > config->nr_ctm_channels = CTI_DEVID_CTMCHANNELS(devid); > > /* Most regs default to 0 as zalloc'ed except...*/ > config->trig_filter_enable = true; > config->ctigate = GENMASK(config->nr_ctm_channels - 1, 0); > config->enable_req_count = 0; > + return 0; > } > > /* > @@ -270,8 +291,10 @@ int cti_add_connection_entry(struct device *dev, struct cti_drvdata *drvdata, > cti_dev->nr_trig_con++; > > /* add connection usage bit info to overall info */ > - drvdata->config.trig_in_use |= tc->con_in->used_mask; > - drvdata->config.trig_out_use |= tc->con_out->used_mask; > + bitmap_or(drvdata->config.trig_in_use, drvdata->config.trig_in_use, > + tc->con_in->used_mask, drvdata->config.nr_trig_max); > + bitmap_or(drvdata->config.trig_out_use, drvdata->config.trig_out_use, > + tc->con_out->used_mask, drvdata->config.nr_trig_max); > > return 0; > } > @@ -293,12 +316,20 @@ struct cti_trig_con *cti_allocate_trig_con(struct device *dev, int in_sigs, > if (!in) > return NULL; > > + in->used_mask = devm_bitmap_alloc(dev, in_sigs, GFP_KERNEL); > + if (!in->used_mask) > + return NULL; > + > out = devm_kzalloc(dev, > offsetof(struct cti_trig_grp, sig_types[out_sigs]), > GFP_KERNEL); > if (!out) > return NULL; > > + out->used_mask = devm_bitmap_alloc(dev, out_sigs, GFP_KERNEL); > + if (!out->used_mask) > + return NULL; > + > tc->con_in = in; > tc->con_out = out; > tc->con_in->nr_sigs = in_sigs; > @@ -314,7 +345,6 @@ int cti_add_default_connection(struct device *dev, struct cti_drvdata *drvdata) > { > int ret = 0; > int n_trigs = drvdata->config.nr_trig_max; > - u32 n_trig_mask = GENMASK(n_trigs - 1, 0); > struct cti_trig_con *tc = NULL; > > /* > @@ -325,8 +355,9 @@ int cti_add_default_connection(struct device *dev, struct cti_drvdata *drvdata) > if (!tc) > return -ENOMEM; > > - tc->con_in->used_mask = n_trig_mask; > - tc->con_out->used_mask = n_trig_mask; > + bitmap_fill(tc->con_in->used_mask, n_trigs); > + bitmap_fill(tc->con_out->used_mask, n_trigs); > + > ret = cti_add_connection_entry(dev, drvdata, tc, NULL, "default"); > return ret; > } > @@ -339,7 +370,6 @@ int cti_channel_trig_op(struct device *dev, enum cti_chan_op op, > { > struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent); > struct cti_config *config = &drvdata->config; > - u32 trig_bitmask; > u32 chan_bitmask; > u32 reg_value; > int reg_offset; > @@ -349,18 +379,16 @@ int cti_channel_trig_op(struct device *dev, enum cti_chan_op op, > (trigger_idx >= config->nr_trig_max)) > return -EINVAL; > > - trig_bitmask = BIT(trigger_idx); > - > /* ensure registered triggers and not out filtered */ > if (direction == CTI_TRIG_IN) { > - if (!(trig_bitmask & config->trig_in_use)) > + if (!(test_bit(trigger_idx, config->trig_in_use))) > return -EINVAL; > } else { > - if (!(trig_bitmask & config->trig_out_use)) > + if (!(test_bit(trigger_idx, config->trig_out_use))) > return -EINVAL; > > if ((config->trig_filter_enable) && > - (config->trig_out_filter & trig_bitmask)) > + test_bit(trigger_idx, config->trig_out_filter)) > return -EINVAL; > } > > @@ -891,7 +919,9 @@ static int cti_probe(struct amba_device *adev, const struct amba_id *id) > raw_spin_lock_init(&drvdata->spinlock); > > /* initialise CTI driver config values */ > - cti_set_default_config(dev, drvdata); > + ret = cti_set_default_config(dev, drvdata); > + if (ret) > + return ret; > > pdata = coresight_cti_get_platform_data(dev); > if (IS_ERR(pdata)) { > diff --git a/drivers/hwtracing/coresight/coresight-cti-platform.c b/drivers/hwtracing/coresight/coresight-cti-platform.c > index d0ae10bf6128..4bef860a0484 100644 > --- a/drivers/hwtracing/coresight/coresight-cti-platform.c > +++ b/drivers/hwtracing/coresight/coresight-cti-platform.c > @@ -136,8 +136,8 @@ static int cti_plat_create_v8_etm_connection(struct device *dev, > goto create_v8_etm_out; > > /* build connection data */ > - tc->con_in->used_mask = 0xF0; /* sigs <4,5,6,7> */ > - tc->con_out->used_mask = 0xF0; /* sigs <4,5,6,7> */ > + bitmap_set(tc->con_in->used_mask, 4, 4); /* sigs <4,5,6,7> */ > + bitmap_set(tc->con_out->used_mask, 4, 4); /* sigs <4,5,6,7> */ > > /* > * The EXTOUT type signals from the ETM are connected to a set of input > @@ -194,10 +194,10 @@ static int cti_plat_create_v8_connections(struct device *dev, > goto of_create_v8_out; > > /* Set the v8 PE CTI connection data */ > - tc->con_in->used_mask = 0x3; /* sigs <0 1> */ > + bitmap_set(tc->con_in->used_mask, 0, 2); /* sigs <0 1> */ > tc->con_in->sig_types[0] = PE_DBGTRIGGER; > tc->con_in->sig_types[1] = PE_PMUIRQ; > - tc->con_out->used_mask = 0x7; /* sigs <0 1 2 > */ > + bitmap_set(tc->con_out->used_mask, 0, 3); /* sigs <0 1 2 > */ > tc->con_out->sig_types[0] = PE_EDBGREQ; > tc->con_out->sig_types[1] = PE_DBGRESTART; > tc->con_out->sig_types[2] = PE_CTIIRQ; > @@ -213,7 +213,7 @@ static int cti_plat_create_v8_connections(struct device *dev, > goto of_create_v8_out; > > /* filter pe_edbgreq - PE trigout sig <0> */ > - drvdata->config.trig_out_filter |= 0x1; > + set_bit(0, drvdata->config.trig_out_filter); > > of_create_v8_out: > return ret; > @@ -257,7 +257,7 @@ static int cti_plat_read_trig_group(struct cti_trig_grp *tgrp, > if (!err) { > /* set the signal usage mask */ > for (idx = 0; idx < tgrp->nr_sigs; idx++) > - tgrp->used_mask |= BIT(values[idx]); > + set_bit(values[idx], tgrp->used_mask); > } > > kfree(values); > @@ -331,7 +331,9 @@ static int cti_plat_process_filter_sigs(struct cti_drvdata *drvdata, > > err = cti_plat_read_trig_group(tg, fwnode, CTI_DT_FILTER_OUT_SIGS); > if (!err) > - drvdata->config.trig_out_filter |= tg->used_mask; > + bitmap_or(drvdata->config.trig_out_filter, > + drvdata->config.trig_out_filter, > + tg->used_mask, drvdata->config.nr_trig_max); > > kfree(tg); > return err; > diff --git a/drivers/hwtracing/coresight/coresight-cti-sysfs.c b/drivers/hwtracing/coresight/coresight-cti-sysfs.c > index 572b80ee96fb..a9df77215141 100644 > --- a/drivers/hwtracing/coresight/coresight-cti-sysfs.c > +++ b/drivers/hwtracing/coresight/coresight-cti-sysfs.c > @@ -711,10 +711,8 @@ static ssize_t trigout_filtered_show(struct device *dev, > struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent); > struct cti_config *cfg = &drvdata->config; > int size = 0, nr_trig_max = cfg->nr_trig_max; > - unsigned long mask = cfg->trig_out_filter; > > - if (mask) > - size = bitmap_print_to_pagebuf(true, buf, &mask, nr_trig_max); > + size = bitmap_print_to_pagebuf(true, buf, cfg->trig_out_filter, nr_trig_max); > return size; > } > static DEVICE_ATTR_RO(trigout_filtered); > @@ -926,9 +924,8 @@ static ssize_t trigin_sig_show(struct device *dev, > struct cti_trig_con *con = (struct cti_trig_con *)ext_attr->var; > struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent); > struct cti_config *cfg = &drvdata->config; > - unsigned long mask = con->con_in->used_mask; > > - return bitmap_print_to_pagebuf(true, buf, &mask, cfg->nr_trig_max); > + return bitmap_print_to_pagebuf(true, buf, con->con_in->used_mask, cfg->nr_trig_max); > } > > static ssize_t trigout_sig_show(struct device *dev, > @@ -940,9 +937,8 @@ static ssize_t trigout_sig_show(struct device *dev, > struct cti_trig_con *con = (struct cti_trig_con *)ext_attr->var; > struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent); > struct cti_config *cfg = &drvdata->config; > - unsigned long mask = con->con_out->used_mask; > > - return bitmap_print_to_pagebuf(true, buf, &mask, cfg->nr_trig_max); > + return bitmap_print_to_pagebuf(true, buf, con->con_out->used_mask, cfg->nr_trig_max); > } > > /* convert a sig type id to a name */ > diff --git a/drivers/hwtracing/coresight/coresight-cti.h b/drivers/hwtracing/coresight/coresight-cti.h > index 8362a47c939c..0bd71407ef34 100644 > --- a/drivers/hwtracing/coresight/coresight-cti.h > +++ b/drivers/hwtracing/coresight/coresight-cti.h > @@ -68,7 +68,7 @@ struct fwnode_handle; > */ > struct cti_trig_grp { > int nr_sigs; > - u32 used_mask; > + unsigned long *used_mask; > int sig_types[]; > }; > > @@ -146,20 +146,21 @@ struct cti_config { > bool hw_enabled; > bool hw_powered; > > - /* registered triggers and filtering */ > - u32 trig_in_use; > - u32 trig_out_use; > - u32 trig_out_filter; > bool trig_filter_enable; > u8 xtrig_rchan_sel; > > /* cti cross trig programmable regs */ > - u32 ctiappset; > u8 ctiinout_sel; > - u32 ctiinen[CTIINOUTEN_MAX]; > - u32 ctiouten[CTIINOUTEN_MAX]; > + u32 ctiappset; > u32 ctigate; > u32 asicctl; > + u32 *ctiinen; > + u32 *ctiouten; > + > + /* registered triggers and filtering */ > + unsigned long *trig_in_use; > + unsigned long *trig_out_use; > + unsigned long *trig_out_filter; > }; > > /** > > -- > 2.43.0 > This all looks good to me. Thanks Reviewed-by: Mike Leach <mike.leach(a)linaro.org> -- Mike Leach Principal Engineer, ARM Ltd. Manchester Design Centre. UK

3 weeks, 5 days

Re: [PATCH 01/12] dt-bindings: arm: coresight: Add cpu cluster tmc/funnel/replicator support

by Mike Leach

Hi, On Tue, 28 Oct 2025 at 09:09, Krzysztof Kozlowski <krzk(a)kernel.org> wrote: > > On Mon, Oct 27, 2025 at 11:28:03PM -0700, Yuanfang Zhang wrote: > > Add the following compatible strings to the bindings: > > - arm,coresight-cpu-funnel > > - arm,coresight-cpu-replicator > > - arm,coresight-cpu-tmc > These are redundant - the actual hardware has not changed - what has is how the device is powered up / down on the system > We see that from the diff. Explain here the hardware instead. > > > > > Each requires 'power-domains' when used. So why is this not used to adjust the power handling in the driver? Or another attribute. Look at the CTI bindings - these can be associated with a CPU or be a system CTI - we look at the cpu attribute to differentiate, not have two separate compatibles. Regards Mike > > > > Signed-off-by: Yuanfang Zhang <yuanfang.zhang(a)oss.qualcomm.com> > > --- > > .../bindings/arm/arm,coresight-dynamic-funnel.yaml | 23 +++++++++++++++++----- > > .../arm/arm,coresight-dynamic-replicator.yaml | 22 +++++++++++++++++---- > > .../devicetree/bindings/arm/arm,coresight-tmc.yaml | 22 +++++++++++++++++---- > > 3 files changed, 54 insertions(+), 13 deletions(-) > > > > diff --git a/Documentation/devicetree/bindings/arm/arm,coresight-dynamic-funnel.yaml b/Documentation/devicetree/bindings/arm/arm,coresight-dynamic-funnel.yaml > > index b74db15e5f8af2226b817f6af5f533b1bfc74736..8f32d4e3bbb750f5a6262db0032318875739cf81 100644 > > --- a/Documentation/devicetree/bindings/arm/arm,coresight-dynamic-funnel.yaml > > +++ b/Documentation/devicetree/bindings/arm/arm,coresight-dynamic-funnel.yaml > > @@ -28,19 +28,32 @@ select: > > properties: > > compatible: > > contains: > > - const: arm,coresight-dynamic-funnel > > + enum: > > + - arm,coresight-dynamic-funnel > > + - arm,coresight-cpu-funnel > > Keep alphabetical sorting. We asked this multiple times already. > > > required: > > - compatible > > > > allOf: > > - $ref: /schemas/arm/primecell.yaml# > > > > + - if: > > + properties: > > + compatible: > > + contains: > > + const: arm,coresight-cpu-funnel > > + then: > > + required: > > + - power-domains > > Just move the allOf to the bottom like in example-schema. > > > + > > properties: > > compatible: > > - items: > > - - const: arm,coresight-dynamic-funnel > > - - const: arm,primecell > > - > > Why do you remove this? > > > + oneOf: > > + - items: > > + - const: arm,coresight-dynamic-funnel > > + - const: arm,primecell > > + - items: > > + - const: arm,coresight-cpu-funnel > > Hm? Why do you need custom select if this is not primecell? And nothing > in commit msg explains why this is not primecell anymore. > > You have entire commit msg to say something useful, WHY you are doing > this, WHY you are doing it DIFFERENTLY. Don't say what you did - that's > obvious, we are capable of reading diffs. > > Best regards, > Krzysztof > -- Mike Leach Principal Engineer, ARM Ltd. Manchester Design Centre. UK

4 weeks

[PATCH v3 00/31] CoreSight: Address CPU Power Management Issues

by Leo Yan

This series addresses CPU power management issues in the CoreSight drivers. For easier review, the patches are organized into two categories: o Patches 01 ~ 10 focus on CPU power management within the ETM drivers. These patches fix SMP-safe access to the mode, correct context synchronization, and refactor the CPU suspend/resume flows. o Patches 11 ~ 31 extend CPU power management to cover activated paths, including helpers, links, and sinks. These changes move CPU PM and hotplug notifiers from the ETMv4 driver into the CoreSight core layer. Summary: - Patches 01 ~ 03: Fix device mode access in the SMP mode. - Patch 04 : A minor fix for polling bit. - Patches 05 ~ 07: Improve the context synchronization based on the ETM specification (IHI0064H.b) and Arm ARM (ARM DDI 0487 L.a). - Patches 08 ~ 10: Refactor the context save/restore flow in the ETMv4 driver, in the end, the CPU PM callbacks reuse the normal enabling and disabling flows. - Patches 11 ~ 17: Move CPU PM code from ETMv4 driver to the core layer. - Patches 18 ~ 23: Enhance the CTI driver for preparation dynamically controlling CTI devices in PM flows. This includes device mode handling in the CTI driver and distinguishing trace modes (Perf or SysFS). Refactor the PM notifier and improve locking usage (including for syscfg). - Patches 24 ~ 31: Support save and restore context for TRBE and manages activated paths during CPU idle and CPU hotplug. Verification: This series has been verified on Juno-r0 and r2 platform. Stress test script: #!/usr/bin/bash echo 1 > /sys/bus/coresight/devices/tmc_etr0/enable_sink while true; do echo 0 > /sys/devices/system/cpu/cpu2/online; echo 1 > /sys/devices/system/cpu/cpu2/online; done & while true; do echo 1 > /sys/bus/coresight/devices/etm2/enable_source; echo 0 > /sys/bus/coresight/devices/etm2/enable_source; done & Test script with kernel module insmod / rmmod: #!/bin/bash modules=( "coresight" "coresight_dummy" "coresight_replicator" "coresight_tpiu" "coresight_cpu_debug" "coresight_etb10" "coresight_stm" "coresight_trbe" "coresight_tmc" "coresight_ctcu" "coresight_catu" "coresight_etm4x" "coresight_cti" "coresight_funnel" "coresight_tnoc" ) module_dir="/mnt/build/drivers/hwtracing/coresight/" if [[ "$1" == "in" ]]; then echo "Inserting modules..." for mod in "${modules[@]}"; do modprobe $mod && echo "Loaded $mod" || echo "Failed to load $mod" done elif [[ "$1" == "rm" ]]; then echo "Removing modules..." # Remove in reverse order to respect dependencies for (( idx=${#modules[@]}-1 ; idx>=0 ; idx-- )); do mod="${modules[$idx]}" echo "Removing $mod..." rmmod "$mod" && echo "Removed $mod" || echo "Failed to remove $mod" done fi --- Changes in v3: - Fixed building failure in ETMv3 driver (kernel test robot). - Refactoring ETMv3 change for checking CPU ID (Levi). - Fixed NULL pointer issue during CPU idle (James). - Fixed lockdep complaint for HARDIRQ-safe and HARDIRA-unsafe (James). - Fixed acquiring mutex in atomic context (James). - Rebased on the latest coresight-next branch. - Link to v2: https://lore.kernel.org/r/20250701-arm_cs_pm_fix_v3-v2-0-23ebb864fcc1@arm.c… Changes in v2: - Refactored ETMv4 suspend and resume for reusing the normal enabling and disabling flows (James). - Used a per-CPU structure to maintain path pointers (James). - Supported helpers in CPU PM flows (James). - Fixed the SMP-safe access to device mode. - Fixed the context synchronization in ETMv4x driver. - Link to v1: https://lore.kernel.org/linux-arm-kernel/20250516160742.1200904-1-leo.yan@a… Signed-off-by: Leo Yan <leo.yan(a)arm.com> --- Leo Yan (30): coresight: Change device mode to atomic type coresight: etm4x: Always set tracer's device mode on target CPU coresight: etm3x: Always set tracer's device mode on target CPU coresight: etm4x: Correct polling IDLE bit coresight: etm4x: Ensure context synchronization is not ignored coresight: etm4x: Add context synchronization before enabling trace coresight: etm4x: Properly control filter in CPU idle with FEAT_TRF coresight: etm4x: Remove the state_needs_restore flag coresight: etm4x: Add flag to control single-shot restart coresight: etm4x: Reuse normal enable and disable logic in CPU idle coresight: Populate CPU ID into the coresight_device structure coresight: sysfs: Validate CPU online status for per-CPU sources coresight: Set per CPU source pointer coresight: Register CPU PM notifier in core layer coresight: etm4x: Hook CPU PM callbacks coresight: Add callback to determine if context save/restore is needed coresight: etm4x: Remove redundant condition checks in save and restore coresight: cti: Fix race condition by using device mode coresight: cti: Introduce CS_MODE_DEBUG mode coresight: cti: Register PM notifier after data initialization coresight: cti: Properly handle modes in CPU PM notifiers coresight: cti: Make spin lock usage consistent coresight: syscfg: Use spinlock to protect active variables coresight: Add per-CPU path pointer coresight: Add 'in_idle' argument to path enable/disable functions coresight: Control path during CPU idle coresight: Add PM callbacks for percpu sink coresight: Take hotplug lock in enable_source_store() for Sysfs mode coresight: Move CPU hotplug callbacks to core layer coresight: Manage activated path during CPU hotplug Yabin Cui (1): coresight: trbe: Save and restore state across CPU low power state drivers/hwtracing/coresight/coresight-catu.c | 1 + drivers/hwtracing/coresight/coresight-core.c | 337 ++++++++++++-- drivers/hwtracing/coresight/coresight-ctcu-core.c | 1 + drivers/hwtracing/coresight/coresight-cti-core.c | 69 ++- drivers/hwtracing/coresight/coresight-cti-sysfs.c | 2 +- drivers/hwtracing/coresight/coresight-dummy.c | 1 + drivers/hwtracing/coresight/coresight-etb10.c | 1 + drivers/hwtracing/coresight/coresight-etm3x-core.c | 55 ++- drivers/hwtracing/coresight/coresight-etm4x-core.c | 491 ++++++--------------- drivers/hwtracing/coresight/coresight-etm4x.h | 62 --- drivers/hwtracing/coresight/coresight-funnel.c | 1 + drivers/hwtracing/coresight/coresight-replicator.c | 1 + drivers/hwtracing/coresight/coresight-stm.c | 1 + drivers/hwtracing/coresight/coresight-syscfg.c | 22 +- drivers/hwtracing/coresight/coresight-syscfg.h | 2 + drivers/hwtracing/coresight/coresight-sysfs.c | 10 + drivers/hwtracing/coresight/coresight-tmc-core.c | 1 + drivers/hwtracing/coresight/coresight-tpda.c | 1 + drivers/hwtracing/coresight/coresight-tpdm.c | 1 + drivers/hwtracing/coresight/coresight-tpiu.c | 1 + drivers/hwtracing/coresight/coresight-trbe.c | 85 ++++ drivers/hwtracing/coresight/ultrasoc-smb.c | 1 + include/linux/coresight.h | 55 ++- 23 files changed, 687 insertions(+), 515 deletions(-) --- base-commit: 559d6c380ea0a27e71d0269410301303515e4179 change-id: 20250909-arm_coresight_power_management_fix-139873f942e8 Best regards, -- Leo Yan <leo.yan(a)arm.com>

4 weeks

Re: [PATCH v3 1/2] dt-bindings: arm: add CTCU device for QCS8300

by Suzuki K Poulose

On 13/10/2025 09:34, Jie Gan wrote: > The CTCU device for QCS8300 shares the same configurations as SA8775p. Add > a fallback to enable the CTCU for QCS8300 to utilize the compitable of the > SA8775p. > > Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski(a)linaro.org> > Signed-off-by: Jie Gan <jie.gan(a)oss.qualcomm.com> > --- > Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml | 9 +++++++-- > 1 file changed, 7 insertions(+), 2 deletions(-) > > diff --git a/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml b/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml > index c969c16c21ef..460f38ddbd73 100644 > --- a/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml > +++ b/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml > @@ -26,8 +26,13 @@ description: | > > properties: > compatible: > - enum: > - - qcom,sa8775p-ctcu > + oneOf: > + - items: > + - enum: > + - qcom,qcs8300-ctcu > + - const: qcom,sa8775p-ctcu > + - enum: > + - qcom,sa8775p-ctcu > > reg: > maxItems: 1 > Acked-by: Suzuki K Poulose <suzuki.poulose(a)arm.com>

4 weeks, 1 day

Re: [PATCH v4 05/11] coresight: etm4x: Ensure context synchronization is not ignored

by Suzuki K Poulose

On 27/10/2025 10:43, Yeoreum Yun wrote: > Hi Suzuki, >> On 24/10/2025 17:45, Leo Yan wrote: >>> As recommended in section 4.3.7 "Synchronization of register updates" of >>> ARM IHI0064H.b, a self-hosted trace analyzer should always executes an >>> ISB instruction after programming the trace unit registers. >>> >>> An ISB works as a context synchronization event; a DSB is not required. >>> Removes the redundant barrier in the enabling flow. >> >> It is required for MMIO based instances and must be retained. > > I think it seems fine. since the the etm4x device mmio is mapped as > Device-nGnRE and according to the section Leo mention: > > Synchronization when using the memory-mapped interface > .. > When disabling or enabling the trace unit, the trace analyzer must poll TRCSTATR to check the trace unit is either > idle or not idle, as described in Use of the trace unit main enable bit on page 4-169: > • When the memory is marked as Device-nGnRE or stronger. > — Write to enable or disable the trace unit. > — Poll TRCSTATR to ensure the previous write has completed. > — Execute an ISB operation. > > Therefore, we can omit the dsb in here. You are right, to be precise, as long as we quote the following, I am fine. Section 4.3.7, Synchronization when using the memory-mapped interface - When using the memory-mapped interface to program the trace unit, the trace analyzer must ensure that writes have completed, to ensure that the trace unit is fully programmed and either enabled or disabled. • If the memory marked is as Device-nGnRE or stronger, read back the value of any register in the trace unit. This relies on peripheral coherence order defined in the Arm architecture. Suzuki > > [...] > > Thanks. > > -- > Sincerely, > Yeoreum Yun

1 month

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