CoreSight

coresight@lists.linaro.org

3 participants
2715 discussions

[PATCH v11 0/9] fix several inconsistencies with sysfs configuration in etmX

by Yeoreum Yun

The current ETMx configuration via sysfs can lead to the following inconsistencies: - If a configuration is modified via sysfs while a perf session is active, the running configuration may differ between before a sched-out and after a subsequent sched-in. - If a perf session and sysfs session tries to enable concurrently, configuration from configfs could be corrupted (etm4). - There is chance to corrupt drvdata->config if perf session tries to enabled among handling cscfg_csdev_disable_active_config() in etm4_disable_sysfs() (etm4). To resolve these inconsistencies, the configuration should be separated into: - active_config, which is applied configuration for the current session - config, which stores the settings configured via sysfs. and apply configuration from configfs after taking a mode. Patch History ============= from v10 to 11: - replace direct register read from etm3 sysfs with IPI. - fix issue cntr_val and others field which required to be shown after sysfs session disable. - prohibit the write for some etm3 sysfs while sysfs session is enabled. - drop locktype change in etm3 - Link to v10: https://lore.kernel.org/r/20260911-separate_etm_cfg_v2-v10-0-1b715d95927a@a… from v9 to v10: - rebase to coresight/next - https://lore.kernel.org/all/20260725113645.57519-1-yeoreum.yun@arm.com/ from v8 to v9: - add feat_csdev_lock guard interface. - set feat_csdev->drv_spinlock as NULL for etmv4_drvdata. - https://lore.kernel.org/all/20260629090007.1718746-1-yeoreum.yun@arm.com/ from v7 to v8: - accept @Leo Yan' suggestion to handle error. - small minor fixes following @Suzuki' suggestion. - https://lore.kernel.org/all/20260519154812.254884-1-yeoreum.yun@arm.com/ from v6 to v7: - rebase on coresight/next - add ETM_MAX_SEQ_TRANSITIONS define - remove redundant patch relavent cpu-hotplug as coresight-pm patch merged. - https://lore.kernel.org/all/20260422132203.977549-1-yeoreum.yun@arm.com/ from v5 to v6: - fix missing of calling cscfg_csdev_disable_active_config() - add rb & fixes tags. - add ss_status field in etm4x_drvdata to expose STATUS and PENDING bits. - https://lore.kernel.org/all/20260415165528.3369607-1-yeoreum.yun@arm.com/ from v4 to v5: - add rb-tag. - fix underflow issue for nrseqstate. - fix wrong check in etm4_sspcicrn_present(). - remove redundant fields on etmv4_save_state. - rename caps->ss_status to ss_cmp. - fix wrong location of etm4_release_trace_id. - https://lore.kernel.org/all/20260413142003.3549310-1-yeoreum.yun@arm.com/ from v3 to v4: - change etm_drvdata->spinlock type to raw_spin_lock_t - remove redundant call etmX_enable_hw() with starting_cpu() callsback. - fix missing trace id release. - add missing docs. - https://lore.kernel.org/all/20260412175506.412301-1-yeoreum.yun@arm.com/ from v2 to v3: - fix build error for etm3x. - fix checkpatch warning. - https://lore.kernel.org/all/20260410074310.2693385-1-yeoreum.yun@arm.com/ from v1 to v2 - rebased to v7.0-rc7. - introduce etmX_caps structure to save etmX's capabilities. - remove ss_status from etmv4_config. - modify active_config after taking a mode (perf/sysfs). - https://lore.kernel.org/all/20260317181705.2456271-1-yeoreum.yun@arm.com/ --- Yeoreum Yun (9): coresight: etm4x: prohibit modifying ss_status and cntr_val while session is enabled coresight: etm3x: prohibit modifying cntr_val and reset while session is enabled coresight: etm4x: fix inconsistencies with sysfs configuration coresight: etm3x: fix inconsistencies with sysfs configuration coresight: etm3x: remove redundant cpu online check on etm_enable_sysfs() coresight: etm4x: introduce struct etm4_caps coresight: etm4x: exclude ss_status from drvdata->config coresight: etm4x: remove s_ex_level from config coresight: etm3x: introduce struct etm_caps drivers/hwtracing/coresight/coresight-config.c | 18 +- drivers/hwtracing/coresight/coresight-config.h | 22 ++ drivers/hwtracing/coresight/coresight-etm.h | 46 ++- drivers/hwtracing/coresight/coresight-etm3x-core.c | 126 +++--- .../hwtracing/coresight/coresight-etm3x-sysfs.c | 104 +++-- drivers/hwtracing/coresight/coresight-etm4x-cfg.c | 14 +- drivers/hwtracing/coresight/coresight-etm4x-core.c | 426 +++++++++++---------- .../hwtracing/coresight/coresight-etm4x-sysfs.c | 210 ++++++---- drivers/hwtracing/coresight/coresight-etm4x.h | 196 +++++----- 9 files changed, 676 insertions(+), 486 deletions(-) --- base-commit: 9e3604d7369cfc0110100eb1a0acab1865ee2d18 change-id: 20260911-separate_etm_cfg_v2-3518a168cbff Best regards, -- Sincerely, Yeoreum Yun

1 month, 2 weeks

Re: [PATCH v2 1/1] coresight: syscfg: fix deadlock on device registration failure

by Leo Yan

On Mon, Sep 14, 2026 at 03:49:00PM +0800, Yingchao Deng wrote: > cscfg_create_device() calls put_device() on the error path while holding > cscfg_mutex. If device_register() fails, put_device() drops the last > reference and invokes cscfg_dev_release(), which takes cscfg_mutex again, > deadlocking. > > Module init and exit are serialized by the kernel, so cscfg_mutex is not > needed to protect the allocation and freeing of cscfg_mgr. Remove the > mutex from cscfg_dev_release() and take it only while cscfg_mgr fields > are being accessed. > > Fixes: 199380decc5f ("coresight: configfs: Fix unload of configurations on module exit") > Suggested-by: Leo Yan <leo.yan(a)arm.com> > Signed-off-by: Yingchao Deng <dengyingchao(a)kylinsec.com.cn> For this patch: Reviewed-by: Leo Yan <leo.yan(a)arm.com> Sashiko reported an issue for null pointer dereference if configfs init fails fails [1]. It is good to fix it using a separate patch: @@ -1299,8 +1299,10 @@ int __init cscfg_init(void) /* initialise configfs subsystem */ err = cscfg_configfs_init(cscfg_mgr); - if (err) - goto exit_err; + if (err) { + device_unregister(cscfg_device()); + return err; + } /* preload built-in configurations */ err = cscfg_preload(THIS_MODULE); @Yingchao, do you mind to work out a formal patch for this? Thanks, Leo [1] https://sashiko.dev/#/patchset/6CC680FFAC60931F%2B20260914074900.1711-1-den…

1 month, 2 weeks

Re: [PATCH v2] coresight: Check runtime PM resume result

by Leo Yan

On Wed, Sep 23, 2026 at 08:18:56PM -0400, Yuho Choi wrote: > @@ -843,7 +843,11 @@ static bool coresight_get_ref(struct coresight_device *csdev) > goto err_module; > > /* Make sure the device is powered on */ > - pm_runtime_get_sync(parent); > + if (pm_runtime_resume_and_get(parent) < 0) { > + module_put(drv->owner); > + goto err_module; > + } > + There is already a patch that does something similar and fixes the same errors across the CoreSight folder. See: https://lore.kernel.org/linux-arm-kernel/20260911-b4-coresight-runtime-pm-f…

1 month, 2 weeks

Re: [PATCH] dt-bindings: arm: Fix CoreSight CTI Kconfig symbol

by Mike Leach

On 9/16/26 20:57, Rob Herring wrote: > On Sat, Aug 22, 2026 at 10:19:12AM +0200, Karl Mehltretter wrote: >> The option exposing CoreSight CTI integration registers is >> CONFIG_CORESIGHT_CTI_INTEGRATION_REGS, not >> CONFIG_CORESIGHT_CTI_INTEGRATION_TEST. > > DT bindings should not be referring to kernel kconfig symbols (or > anything else in the kernel) in the first place. > Agreed - the comment in general is correct but the last sentence in the paragraph should drop the config reference. e.g. "This information might be found by using the CTI Integration Test registers to explore the trigger connections between CTI and other CoreSight components." The coresight/KConfig file itself adequately documents adding this support and the perils therein. Mike > Rob

1 month, 2 weeks

Re: [PATCH v2 1/1] coresight: syscfg: fix deadlock on device registration failure

by Mike Leach

Reviewed-by: Mike Leach <mike.leach(a)arm.com> On 9/14/26 08:49, Yingchao Deng wrote: > cscfg_create_device() calls put_device() on the error path while holding > cscfg_mutex. If device_register() fails, put_device() drops the last > reference and invokes cscfg_dev_release(), which takes cscfg_mutex again, > deadlocking. > > Module init and exit are serialized by the kernel, so cscfg_mutex is not > needed to protect the allocation and freeing of cscfg_mgr. Remove the > mutex from cscfg_dev_release() and take it only while cscfg_mgr fields > are being accessed. > > Fixes: 199380decc5f ("coresight: configfs: Fix unload of configurations on module exit") > Suggested-by: Leo Yan <leo.yan(a)arm.com> > Signed-off-by: Yingchao Deng <dengyingchao(a)kylinsec.com.cn> > --- > drivers/hwtracing/coresight/coresight-syscfg.c | 18 ++++++------------ > 1 file changed, 6 insertions(+), 12 deletions(-) > > diff --git a/drivers/hwtracing/coresight/coresight-syscfg.c b/drivers/hwtracing/coresight/coresight-syscfg.c > index 2bfdd7b45e49..2dd0b29f44e4 100644 > --- a/drivers/hwtracing/coresight/coresight-syscfg.c > +++ b/drivers/hwtracing/coresight/coresight-syscfg.c > @@ -1173,27 +1173,21 @@ struct device *cscfg_device(void) > /* Must have a release function or the kernel will complain on module unload */ > static void cscfg_dev_release(struct device *dev) > { > - mutex_lock(&cscfg_mutex); > kfree(cscfg_mgr); > cscfg_mgr = NULL; > - mutex_unlock(&cscfg_mutex); > } > > /* a device is needed to "own" some kernel elements such as sysfs entries. */ > static int cscfg_create_device(void) > { > struct device *dev; > - int err = -ENOMEM; > - > - mutex_lock(&cscfg_mutex); > - if (cscfg_mgr) { > - err = -EINVAL; > - goto create_dev_exit_unlock; > - } > + int err; > > cscfg_mgr = kzalloc_obj(struct cscfg_manager); > if (!cscfg_mgr) > - goto create_dev_exit_unlock; > + return -ENOMEM; > + > + mutex_lock(&cscfg_mutex); > > /* initialise the cscfg_mgr structure */ > INIT_LIST_HEAD(&cscfg_mgr->csdev_desc_list); > @@ -1204,6 +1198,8 @@ static int cscfg_create_device(void) > cscfg_mgr->load_state = CSCFG_NONE; > raw_spin_lock_init(&cscfg_mgr->sysfs_store_lock); > > + mutex_unlock(&cscfg_mutex); > + > /* setup the device */ > dev = cscfg_device(); > dev->release = cscfg_dev_release; > @@ -1213,8 +1209,6 @@ static int cscfg_create_device(void) > if (err) > put_device(dev); > > -create_dev_exit_unlock: > - mutex_unlock(&cscfg_mutex); > return err; > } >

1 month, 2 weeks

Re: [PATCH] coresight: cti: Add const to con_groups allocation type

by Mike Leach

Reviewed-by: Mike Leach <mike.leach(a)arm.com> On 9/17/26 22:14, Kees Cook wrote: > From: Kees Cook <kees+treewide(a)kernel.org> > > In preparation for making the devm_kmalloc family of allocators type > aware, we need to make sure that the returned type from the allocation > matches the type of the variable being assigned. (Before, the allocator > would always return "void *", which can be implicitly cast to any > pointer type.) > > The assigned type is "const struct attribute_group **", but the > converted allocation type would be "struct attribute_group **", which is > the same type without the const qualifier. As there is no general way to > safely add const qualifiers, take the size from the assignment target > instead. No change in allocation size results. > > Build tested ARCH=arm64 allmodconfig with GCC aarch64-linux-gnu 16.1.0: > drivers/hwtracing/coresight/coresight-cti-sysfs.o > > Assisted-by: LLM coccinelle > Signed-off-by: Kees Cook <kees+treewide(a)kernel.org> > --- > Cc: Suzuki K Poulose <suzuki.poulose(a)arm.com> > Cc: Mike Leach <mike.leach(a)arm.com> > Cc: James Clark <james.clark(a)linaro.org> > Cc: Leo Yan <leo.yan(a)arm.com> > Cc: Alexander Shishkin <alexander.shishkin(a)linux.intel.com> > Cc: <coresight(a)lists.linaro.org> > Cc: <linux-arm-kernel(a)lists.infradead.org> > --- > drivers/hwtracing/coresight/coresight-cti-sysfs.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/hwtracing/coresight/coresight-cti-sysfs.c b/drivers/hwtracing/coresight/coresight-cti-sysfs.c > index 3fe2c916d228..2ed5d8eb1dda 100644 > --- a/drivers/hwtracing/coresight/coresight-cti-sysfs.c > +++ b/drivers/hwtracing/coresight/coresight-cti-sysfs.c > @@ -1132,7 +1132,7 @@ static int cti_create_cons_groups(struct device *dev, struct cti_device *ctidev) > /* nr groups = dynamic + static + NULL terminator */ > nr_groups = ctidev->nr_trig_con + CORESIGHT_CTI_STATIC_GROUPS_MAX; > ctidev->con_groups = devm_kcalloc(dev, nr_groups, > - sizeof(struct attribute_group *), > + sizeof(*ctidev->con_groups), > GFP_KERNEL); > if (!ctidev->con_groups) > return -ENOMEM;

1 month, 2 weeks

[PATCH v10 0/8] fix several inconsistencies with sysfs configuration in etmX

by Yeoreum Yun

The current ETMx configuration via sysfs can lead to the following inconsistencies: - If a configuration is modified via sysfs while a perf session is active, the running configuration may differ between before a sched-out and after a subsequent sched-in. - If a perf session and sysfs session tries to enable concurrently, configuration from configfs could be corrupted (etm4). - There is chance to corrupt drvdata->config if perf session tries to enabled among handling cscfg_csdev_disable_active_config() in etm4_disable_sysfs() (etm4). To resolve these inconsistencies, the configuration should be separated into: - active_config, which is applied configuration for the current session - config, which stores the settings configured via sysfs. and apply configuration from configfs after taking a mode. Patch History ============= from v9 to v10: - rebase to coresight/next - https://lore.kernel.org/all/20260725113645.57519-1-yeoreum.yun@arm.com/ from v8 to v9: - add feat_csdev_lock guard interface. - set feat_csdev->drv_spinlock as NULL for etmv4_drvdata. - https://lore.kernel.org/all/20260629090007.1718746-1-yeoreum.yun@arm.com/ from v7 to v8: - accept @Leo Yan' suggestion to handle error. - small minor fixes following @Suzuki' suggestion. - https://lore.kernel.org/all/20260519154812.254884-1-yeoreum.yun@arm.com/ from v6 to v7: - rebase on coresight/next - add ETM_MAX_SEQ_TRANSITIONS define - remove redundant patch relavent cpu-hotplug as coresight-pm patch merged. - https://lore.kernel.org/all/20260422132203.977549-1-yeoreum.yun@arm.com/ from v5 to v6: - fix missing of calling cscfg_csdev_disable_active_config() - add rb & fixes tags. - add ss_status field in etm4x_drvdata to expose STATUS and PENDING bits. - https://lore.kernel.org/all/20260415165528.3369607-1-yeoreum.yun@arm.com/ from v4 to v5: - add rb-tag. - fix underflow issue for nrseqstate. - fix wrong check in etm4_sspcicrn_present(). - remove redundant fields on etmv4_save_state. - rename caps->ss_status to ss_cmp. - fix wrong location of etm4_release_trace_id. - https://lore.kernel.org/all/20260413142003.3549310-1-yeoreum.yun@arm.com/ from v3 to v4: - change etm_drvdata->spinlock type to raw_spin_lock_t - remove redundant call etmX_enable_hw() with starting_cpu() callsback. - fix missing trace id release. - add missing docs. - https://lore.kernel.org/all/20260412175506.412301-1-yeoreum.yun@arm.com/ from v2 to v3: - fix build error for etm3x. - fix checkpatch warning. - https://lore.kernel.org/all/20260410074310.2693385-1-yeoreum.yun@arm.com/ from v1 to v2 - rebased to v7.0-rc7. - introduce etmX_caps structure to save etmX's capabilities. - remove ss_status from etmv4_config. - modify active_config after taking a mode (perf/sysfs). - https://lore.kernel.org/all/20260317181705.2456271-1-yeoreum.yun@arm.com/ --- Yeoreum Yun (8): coresight: etm4x: fix inconsistencies with sysfs configuration coresight: etm3x: fix inconsistencies with sysfs configuration coresight: etm3x: change drvdata->spinlock type to raw_spin_lock_t coresight: etm3x: remove redundant cpu online check on etm_enable_sysfs() coresight: etm4x: introduce struct etm4_caps coresight: etm4x: exclude ss_status from drvdata->config coresight: etm4x: remove s_ex_level from config coresight: etm3x: introduce struct etm_caps drivers/hwtracing/coresight/coresight-config.c | 18 +- drivers/hwtracing/coresight/coresight-config.h | 22 ++ drivers/hwtracing/coresight/coresight-etm.h | 48 ++- drivers/hwtracing/coresight/coresight-etm3x-core.c | 96 ++--- .../hwtracing/coresight/coresight-etm3x-sysfs.c | 155 ++++---- drivers/hwtracing/coresight/coresight-etm4x-cfg.c | 14 +- drivers/hwtracing/coresight/coresight-etm4x-core.c | 413 +++++++++++---------- .../hwtracing/coresight/coresight-etm4x-sysfs.c | 204 +++++----- drivers/hwtracing/coresight/coresight-etm4x.h | 196 +++++----- 9 files changed, 645 insertions(+), 521 deletions(-) --- base-commit: 9e3604d7369cfc0110100eb1a0acab1865ee2d18 change-id: 20260911-separate_etm_cfg_v2-3518a168cbff Best regards, -- Sincerely, Yeoreum Yun

1 month, 3 weeks

Re: [PATCH 1/1] coresight: tmc-etr: Sync the trace buffer for the device

by Leo Yan

On Wed, Sep 16, 2026 at 11:04:20AM +0800, Jie Gan wrote: [...] > > From: Min Chen <min.chen(a)siengine.com> > > > > The flat ETR buffer comes from dma_alloc_noncoherent(), which zeroes it > > with CPU stores. The DMA API requires the caller to sync the buffer for > > the device before the device writes into it, but the TMC driver only > > ever syncs for the CPU afterwards. On a non-coherent sink the zero fill > > is therefore still dirty in cache when the ETR starts writing, and its > > write-back lands on top of the trace data. Good catch! I'm curious how you observed the dirty cache lines overwriting trace data in DDR and causing corruption. > Agree, without the sync, the dirty data may overwrites the trace data. > > Add a sync_for_device() buffer operation and call it from > > __tmc_etr_enable_hw() just before the TMC is enabled. I don't think __tmc_etr_enable_hw() is the best place for the sync, as it can be called frequently when an event is enabled, e.g. when a task is scheduled in or migrated between CPUs. We should be able to sync once after dma_alloc_noncoherent() instead. The issue is not limited to buffer init. The driver also injects barrier packets into the bounce buffer, which can race with the sink. Even worse, the barrier packet write may collide with trace data when they share a cache line. I think we should consider writing barrier packets directly into the AUX buffer. This would avoid stale cache data from barrier packet writes and simplify the flow without additional sync operations. Would you mind if I pick up this patch (keeping you as the author) and add a second patch to address the barrier packet issue? That part may need some several rounds refactoring so can have better shape, I think it would be easier to consolidate the fixes on my side. Thanks, Leo P.s. Please CC me on future CoreSight patches. If you're using the mainline ./scripts/get_maintainer.pl, it should add me automatically. I didn't receive this patch directly, which is why I'm replying to Jie's email (also thanks Jie's review).

1 month, 3 weeks

[PATCH 00/14] perf cs-etm: Per-thread mode fixes and snapshot wrap support

by James Clark

Fix a few issues with per-thread mode: - With TRBE, thread migrations hit a queue without a decoder assert - On nVHE, everything looks like guest trace instead of host - Tracing multiple threads didn't really work After adding a tests for those, it turns out there were some snapshot bugs not picked up by the other snapshot tests. That showed that the different snapshot searches for Intel BTS and Arm SPE were inconsistent and I think all tracers can benefit from using the same pointer fixup logic, so that gets refactored into the common auxtrace.c. Then SPE can just share the Intel BTS search as it was obviously copied from it originally. IntelPT keeps the more advanced duplicate data search, but in the future that could probably be made the common one and all tracers would benefit from using it (except maybe BTS if it always has a very small buffer, but I doubt the overhead of the duplicate search would be an issue). For now this is more of a refactor rather than behavioral change so don't do that yet. Signed-off-by: James Clark <james.clark(a)linaro.org> --- James Clark (14): perf cs-etm: Fix nVHE per-thread decoding perf cs-etm: Warn for invalid timestamp option perf cs-etm: Turn on context packet timestamps in per-thread mode perf cs-etm: Use per-CPU queues for per-thread mode perf cs-etm: Increase default timestamp generation period perf auxtrace: Turn Intel BTS snapshot search into a generic one perf arm-spe: Use generic snapshot search perf auxtrace: intel-pt: Use new snapshot_has_wrapped callback perf cs-etm: Queue partial AUX records perf cs-etm: Don't print missing buffers in snapshot mode perf auxtrace: cs-etm: Capture wrapped snapshots perf test: Allow infinite named_thread loops perf test: Add test for per-thread mode perf cs-etm: Test multiple per-thread threads Documentation/userspace-api/perf_ring_buffer.rst | 6 +- tools/perf/Documentation/perf-test.txt | 2 +- tools/perf/arch/arm/util/cs-etm.c | 30 ++++- tools/perf/arch/arm64/util/arm-spe.c | 147 +-------------------- tools/perf/arch/x86/util/intel-bts.c | 115 +--------------- tools/perf/arch/x86/util/intel-pt.c | 58 +++----- .../perf/tests/shell/coresight/per-thread-multi.sh | 78 +++++++++++ tools/perf/tests/shell/coresight/per-thread.sh | 48 +++++++ .../perf/tests/shell/coresight/raw_dump_stress.sh | 5 - tools/perf/tests/workloads/named_threads.c | 7 +- tools/perf/util/auxtrace.c | 136 +++++++++++++++++-- tools/perf/util/auxtrace.h | 20 ++- tools/perf/util/cs-etm.c | 98 ++++++++++---- 13 files changed, 382 insertions(+), 368 deletions(-) --- base-commit: bf10e6ee2ac3034c9068e03eed418fd16961984e change-id: 20260605-james-cs-unformatted-per-thread-fix-50e723aa7f0e Best regards, -- James Clark <james.clark(a)linaro.org>

1 month, 3 weeks

Re: [PATCH v10 3/5] coresight: cti: add Qualcomm extended CTI identification and quirks

by Mike Leach

On 6/15/26 13:32, Yingchao Deng wrote: > Qualcomm implements an extended variant of the ARM CoreSight CTI with a > different register layout and vendor-specific behavior. While the > programming model remains largely compatible, the register offsets differ > from the standard ARM CTI and require explicit handling. > > Detect Qualcomm CTIs via the DEVARCH register and record this in the CTI > driver data. Introduce a small mapping layer to translate standard CTI > register offsets to Qualcomm-specific offsets, allowing the rest of the > driver to use a common register access path. > > Additionally, handle a Qualcomm-specific quirk where the hardware does > not implement the CoreSight Claim tag protocol. Instead of clearing the > CLAIMSET register at probe time, bypass the claim/disclaim operations > entirely for Qualcomm CTIs by wrapping coresight_claim_device(), > coresight_disclaim_device_unlocked() and coresight_clear_self_claim_tag() > in thin helpers that early-return when is_qcom_cti is set. > > No functional change is intended for standard ARM CTI devices. > > Co-developed-by: Jinlong Mao <jinlong.mao(a)oss.qualcomm.com> > Signed-off-by: Jinlong Mao <jinlong.mao(a)oss.qualcomm.com> > Signed-off-by: Yingchao Deng <yingchao.deng(a)oss.qualcomm.com> > --- > drivers/hwtracing/coresight/coresight-cti-core.c | 47 +++++++++++++++-- > drivers/hwtracing/coresight/coresight-cti.h | 64 +++++++++++++++++++++++- > 2 files changed, 105 insertions(+), 6 deletions(-) > > diff --git a/drivers/hwtracing/coresight/coresight-cti-core.c b/drivers/hwtracing/coresight/coresight-cti-core.c > index fa758c535ccb..5b83dd4e603b 100644 > --- a/drivers/hwtracing/coresight/coresight-cti-core.c > +++ b/drivers/hwtracing/coresight/coresight-cti-core.c > @@ -73,6 +73,35 @@ void cti_write_all_hw_regs(struct cti_drvdata *drvdata) > CS_LOCK(drvdata->base); > } > > +/* > + * Qualcomm CTIs do not implement the CoreSight Claim tag protocol, so > + * bypass coresight_clear_self_claim_tag() for them. > + */ > +static void cti_clear_self_claim_tag(struct cti_drvdata *drvdata, > + struct csdev_access *csa) > +{ > + if (drvdata->is_qcom_cti) > + return; > + > + coresight_clear_self_claim_tag(csa); > +} > + > +static int cti_claim_device(struct cti_drvdata *drvdata) > +{ > + if (drvdata->is_qcom_cti) > + return 0; > + > + return coresight_claim_device(drvdata->csdev); > +} > + > +static void cti_unclaim_device_unlocked(struct cti_drvdata *drvdata) > +{ > + if (drvdata->is_qcom_cti) > + return; > + > + coresight_disclaim_device_unlocked(drvdata->csdev); > +} > + > /* write regs to hardware and enable */ > static int cti_enable_hw(struct cti_drvdata *drvdata) > { > @@ -86,7 +115,7 @@ static int cti_enable_hw(struct cti_drvdata *drvdata) > goto cti_state_unchanged; > > /* claim the device */ > - rc = coresight_claim_device(drvdata->csdev); > + rc = cti_claim_device(drvdata); > if (rc) > return rc; > > @@ -101,7 +130,6 @@ static int cti_enable_hw(struct cti_drvdata *drvdata) > static int cti_disable_hw(struct cti_drvdata *drvdata) > { > struct cti_config *config = &drvdata->config; > - struct coresight_device *csdev = drvdata->csdev; > > guard(raw_spinlock_irqsave)(&drvdata->spinlock); > > @@ -118,7 +146,7 @@ static int cti_disable_hw(struct cti_drvdata *drvdata) > /* disable CTI */ > writel_relaxed(0, drvdata->base + CTICONTROL); > > - coresight_disclaim_device_unlocked(csdev); > + cti_unclaim_device_unlocked(drvdata); > CS_LOCK(drvdata->base); > return 0; > } > @@ -144,6 +172,9 @@ void cti_write_intack(struct device *dev, u32 ackval) > /* DEVID[19:16] - number of CTM channels */ > #define CTI_DEVID_CTMCHANNELS(devid_val) ((int) BMVAL(devid_val, 16, 19)) > > +/* DEVARCH[31:21] - ARCHITECT */ > +#define CTI_DEVARCH_ARCHITECT(devarch_val) ((int)BMVAL(devarch_val, 21, 31)) > + > static int cti_set_default_config(struct device *dev, > struct cti_drvdata *drvdata) > { > @@ -684,6 +715,7 @@ static int cti_probe(struct amba_device *adev, const struct amba_id *id) > struct coresight_desc cti_desc = { 0 }; > struct coresight_platform_data *pdata = NULL; > struct resource *res = &adev->res; > + u32 devarch; > > /* driver data*/ > drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL); > @@ -708,6 +740,10 @@ static int cti_probe(struct amba_device *adev, const struct amba_id *id) > > raw_spin_lock_init(&drvdata->spinlock); > > + devarch = readl_relaxed(drvdata->base + CORESIGHT_DEVARCH); > + if (CTI_DEVARCH_ARCHITECT(devarch) == QCOM_ARCHITECT) > + drvdata->is_qcom_cti = true; > + > /* initialise CTI driver config values */ > ret = cti_set_default_config(dev, drvdata); > if (ret) > @@ -753,7 +789,7 @@ static int cti_probe(struct amba_device *adev, const struct amba_id *id) > cti_desc.groups = drvdata->ctidev.con_groups; > cti_desc.dev = dev; > > - coresight_clear_self_claim_tag(&cti_desc.access); > + cti_clear_self_claim_tag(drvdata, &cti_desc.access); > drvdata->csdev = coresight_register(&cti_desc); > if (IS_ERR(drvdata->csdev)) > return PTR_ERR(drvdata->csdev); > @@ -767,7 +803,8 @@ static int cti_probe(struct amba_device *adev, const struct amba_id *id) > > /* all done - dec pm refcount */ > pm_runtime_put(&adev->dev); > - dev_info(&drvdata->csdev->dev, "CTI initialized\n"); > + dev_info(&drvdata->csdev->dev, > + "%sCTI initialized\n", drvdata->is_qcom_cti ? "QCOM " : ""); > return 0; > } > > diff --git a/drivers/hwtracing/coresight/coresight-cti.h b/drivers/hwtracing/coresight/coresight-cti.h > index 634bdce5cdfd..4b6fd6b55114 100644 > --- a/drivers/hwtracing/coresight/coresight-cti.h > +++ b/drivers/hwtracing/coresight/coresight-cti.h > @@ -54,10 +54,36 @@ struct fwnode_handle; > /* > * CTI CSSoc 600 has a max of 32 trigger signals per direction. > * CTI CSSoc 400 has 8 IO triggers - other CTIs can be impl def. > + * QCOM CTI support up to 128 trigger signals per direction. > * Max of in and out defined in the DEVID register. > * - pick up actual number used from .dts parameters if present. I haven't seen anything in these patches that actually does check for max CTIINOUT values in .dts. Would it not be better to have a QCOM_CTIINOUTENMAX and set the max value in config based on the is_qcom_cti flag? Otherwise it appears that the standard arm CTIs are going to create a whole lot of unneeded/unused registers Regards Mike > */ > -#define CTIINOUTEN_MAX 32 > +#define CTIINOUTEN_MAX 128 > + > +/* QCOM CTI extension */ > +#define QCOM_ARCHITECT 0x477 > + > +#define QCOM_CTIINTACK 0x020 > +#define QCOM_CTIAPPSET 0x004 > +#define QCOM_CTIAPPCLEAR 0x008 > +#define QCOM_CTIAPPPULSE 0x00C > +#define QCOM_CTIINEN 0x400 > +#define QCOM_CTIOUTEN 0x800 > +#define QCOM_CTITRIGINSTATUS 0x040 > +#define QCOM_CTITRIGOUTSTATUS 0x060 > +#define QCOM_CTICHINSTATUS 0x080 > +#define QCOM_CTICHOUTSTATUS 0x084 > +#define QCOM_CTIGATE 0x088 > +#define QCOM_ASICCTL 0x08C > +/* Integration test registers */ > +#define QCOM_ITCHINACK 0xE70 > +#define QCOM_ITTRIGINACK 0xE80 > +#define QCOM_ITCHOUT 0xE74 > +#define QCOM_ITTRIGOUT 0xEA0 > +#define QCOM_ITCHOUTACK 0xE78 > +#define QCOM_ITTRIGOUTACK 0xEC0 > +#define QCOM_ITCHIN 0xE7C > +#define QCOM_ITTRIGIN 0xEE0 > > /** > * Group of related trigger signals > @@ -168,6 +194,9 @@ struct cti_config { > * @spinlock: Control data access to one at a time. > * @config: Configuration data for this CTI device. > * @node: List entry of this device in the list of CTI devices. > + * @is_qcom_cti: True if this CTI is a Qualcomm vendor-specific > + * variant that requires register offset translation > + * via cti_qcom_reg_off(). > */ > struct cti_drvdata { > void __iomem *base; > @@ -176,6 +205,7 @@ struct cti_drvdata { > raw_spinlock_t spinlock; > struct cti_config config; > struct list_head node; > + bool is_qcom_cti; > }; > > /* > @@ -229,9 +259,41 @@ struct coresight_platform_data * > coresight_cti_get_platform_data(struct device *dev); > const char *cti_plat_get_node_name(struct fwnode_handle *fwnode); > > +static inline u32 cti_qcom_reg_off(u32 offset) > +{ > + switch (offset) { > + case CTIINTACK: return QCOM_CTIINTACK; > + case CTIAPPSET: return QCOM_CTIAPPSET; > + case CTIAPPCLEAR: return QCOM_CTIAPPCLEAR; > + case CTIAPPPULSE: return QCOM_CTIAPPPULSE; > + case CTIINEN: return QCOM_CTIINEN; > + case CTIOUTEN: return QCOM_CTIOUTEN; > + case CTITRIGINSTATUS: return QCOM_CTITRIGINSTATUS; > + case CTITRIGOUTSTATUS: return QCOM_CTITRIGOUTSTATUS; > + case CTICHINSTATUS: return QCOM_CTICHINSTATUS; > + case CTICHOUTSTATUS: return QCOM_CTICHOUTSTATUS; > + case CTIGATE: return QCOM_CTIGATE; > + case ASICCTL: return QCOM_ASICCTL; > + case ITCHINACK: return QCOM_ITCHINACK; > + case ITTRIGINACK: return QCOM_ITTRIGINACK; > + case ITCHOUT: return QCOM_ITCHOUT; > + case ITTRIGOUT: return QCOM_ITTRIGOUT; > + case ITCHOUTACK: return QCOM_ITCHOUTACK; > + case ITTRIGOUTACK: return QCOM_ITTRIGOUTACK; > + case ITCHIN: return QCOM_ITCHIN; > + case ITTRIGIN: return QCOM_ITTRIGIN; > + > + default: > + return offset; > + } > +} > + > static inline void __iomem *__reg_addr(struct cti_drvdata *drvdata, > u32 off, u32 index) > { > + if (unlikely(drvdata->is_qcom_cti)) > + off = cti_qcom_reg_off(off); > + > return drvdata->base + off + index * sizeof(u32); > } > >

1 month, 4 weeks

← Newer
1
...
6
7
8
9
10
11
12
...
272
Older →

Jump to page:

2026

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

CoreSight