CoreSight

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2769 discussions

RE: [PATCH v13 7/8] coresight: tmc: integrate byte-cntr's sysfs_ops with tmc sysfs file_ops

by Mike Leach

Hi, > -----Original Message----- > From: Jie Gan <jie.gan(a)oss.qualcomm.com> > Sent: Monday, February 23, 2026 6:56 AM > To: Suzuki Poulose <Suzuki.Poulose(a)arm.com>; Mike Leach > <Mike.Leach(a)arm.com>; James Clark <james.clark(a)linaro.org>; Alexander > Shishkin <alexander.shishkin(a)linux.intel.com>; Rob Herring > <robh(a)kernel.org>; Krzysztof Kozlowski <krzk+dt(a)kernel.org>; Conor Dooley > <conor+dt(a)kernel.org>; Tingwei Zhang > <tingwei.zhang(a)oss.qualcomm.com>; Mao Jinlong > <jinlong.mao(a)oss.qualcomm.com>; Bjorn Andersson > <andersson(a)kernel.org>; Konrad Dybcio <konradybcio(a)kernel.org> > Cc: coresight(a)lists.linaro.org; linux-arm-kernel(a)lists.infradead.org; linux- > kernel(a)vger.kernel.org; linux-arm-msm(a)vger.kernel.org; > devicetree(a)vger.kernel.org; Jie Gan <jie.gan(a)oss.qualcomm.com> > Subject: [PATCH v13 7/8] coresight: tmc: integrate byte-cntr's sysfs_ops with > tmc sysfs file_ops > > Add code logic to invoke byte-cntr's tmc_sysfs_ops if the byte-cntr > is enabled. > > Signed-off-by: Jie Gan <jie.gan(a)oss.qualcomm.com> > --- > drivers/hwtracing/coresight/coresight-tmc-core.c | 53 > +++++++++++++++++++++++- > 1 file changed, 52 insertions(+), 1 deletion(-) > > diff --git a/drivers/hwtracing/coresight/coresight-tmc-core.c > b/drivers/hwtracing/coresight/coresight-tmc-core.c > index 32ca2ec994de..6486bdafdddc 100644 > --- a/drivers/hwtracing/coresight/coresight-tmc-core.c > +++ b/drivers/hwtracing/coresight/coresight-tmc-core.c > @@ -31,6 +31,7 @@ > > #include "coresight-priv.h" > #include "coresight-tmc.h" > +#include "coresight-ctcu.h" > > DEFINE_CORESIGHT_DEVLIST(etb_devs, "tmc_etb"); > DEFINE_CORESIGHT_DEVLIST(etf_devs, "tmc_etf"); > @@ -228,15 +229,47 @@ static int tmc_prepare_crashdata(struct > tmc_drvdata *drvdata) > return 0; > } > > +/* Return the byte-cntr's tmc_sysfs_ops if in using */ > +static const struct tmc_sysfs_ops *tmc_get_byte_cntr_sysfs_ops(struct > tmc_drvdata *drvdata) > +{ > + struct ctcu_byte_cntr *byte_cntr_data; > + struct ctcu_drvdata *ctcu_drvdata; > + struct coresight_device *ctcu; > + int port; > + > + ctcu = tmc_etr_get_ctcu_device(drvdata); > + if (!ctcu) > + return NULL; > + > + port = coresight_get_in_port(drvdata->csdev, ctcu); > + if (port < 0) > + return NULL; > + > + ctcu_drvdata = dev_get_drvdata(ctcu->dev.parent); > + byte_cntr_data = &ctcu_drvdata->byte_cntr_data[port]; > + if (byte_cntr_data && byte_cntr_data->thresh_val) > + return ctcu_drvdata->byte_cntr_sysfs_ops; > + > + return NULL; > +} > + Should be in a CTCU source file, not part of the common tmc code > static int tmc_read_prepare(struct tmc_drvdata *drvdata) > { > + const struct tmc_sysfs_ops *byte_cntr_sysfs_ops; > int ret = 0; > > + byte_cntr_sysfs_ops = tmc_get_byte_cntr_sysfs_ops(drvdata); > + if (byte_cntr_sysfs_ops) { > + ret = byte_cntr_sysfs_ops->read_prepare(drvdata); > + goto out; > + } > + > if (drvdata->sysfs_ops) > ret = drvdata->sysfs_ops->read_prepare(drvdata); > else > ret = -EINVAL; > I understand ctcu usage is per session & per device, but at the start of the session would it not be better to have a function in the ctcu code that takes the drvdata->sysfs_ops and substitutes the callback directly, restoring it at the end. > +out: > if (!ret) > dev_dbg(&drvdata->csdev->dev, "TMC read start\n"); > > @@ -245,13 +278,21 @@ static int tmc_read_prepare(struct tmc_drvdata > *drvdata) > > static int tmc_read_unprepare(struct tmc_drvdata *drvdata) > { > + const struct tmc_sysfs_ops *byte_cntr_sysfs_ops; > int ret = 0; > > + byte_cntr_sysfs_ops = tmc_get_byte_cntr_sysfs_ops(drvdata); > + if (byte_cntr_sysfs_ops) { > + ret = byte_cntr_sysfs_ops->read_unprepare(drvdata); > + goto out; > + } > + > if (drvdata->sysfs_ops) > ret = drvdata->sysfs_ops->read_unprepare(drvdata); > else > ret = -EINVAL; > Again override / restore over the session. Regards Mike > +out: > if (!ret) > dev_dbg(&drvdata->csdev->dev, "TMC read end\n"); > > @@ -277,6 +318,12 @@ static int tmc_open(struct inode *inode, struct file > *file) > static ssize_t tmc_get_sysfs_trace(struct tmc_drvdata *drvdata, loff_t pos, > size_t len, > char **bufpp) > { > + const struct tmc_sysfs_ops *byte_cntr_sysfs_ops; > + > + byte_cntr_sysfs_ops = tmc_get_byte_cntr_sysfs_ops(drvdata); > + if (byte_cntr_sysfs_ops) > + return byte_cntr_sysfs_ops->get_trace_data(drvdata, pos, > len, bufpp); > + > return drvdata->sysfs_ops->get_trace_data(drvdata, pos, len, bufpp); > } > > @@ -297,7 +344,11 @@ static ssize_t tmc_read(struct file *file, char __user > *data, size_t len, > return -EFAULT; > } > > - *ppos += actual; > + if (drvdata->reading_node) > + drvdata->reading_node->pos += actual; > + else > + *ppos += actual; > + > dev_dbg(&drvdata->csdev->dev, "%zu bytes copied\n", actual); > > return actual; > > -- > 2.34.1

3 months, 1 week

[PATCH v2 0/8] coresight: cti: Miscellaneous fixes and CPU PM cleanup

by Leo Yan

The CPU power management issue in the CTI driver was first observed in series [1]; this series resolves that issue. It fixes bugs and removes CPU PM operations from the CoreSight CTI driver, the goal is to use the CoreSight core layer as the central place for CPU power management. Removing CPU PM from CTI driver can avoid conflicts with the core layer. This series can be divided into: Patches 01 ~ 02: Fix spinlock with irqsave and register read with CS lock. Patches 03 ~ 08: Access ASICCTL condintioanlly, remove CPU PM code, and refactor register access in sysfs knob. This series is based on coresight-next branch and has been validated on Juno r2 platforms, pass normal sysfs and perf test, as well as CPU PM stress testing. [1] https://lore.kernel.org/all/20250915-arm_coresight_power_management_fix-v3-… Signed-off-by: Leo Yan <leo.yan(a)arm.com> --- Changes in v2: - Rebased on coresight-next branch (v7.1). - Kept read/write cache value in sysfs knob (Mike). - Link to v1: https://lore.kernel.org/r/20260209-arm_coresight_cti_refactor_v1-v1-0-db71a… --- Leo Yan (8): coresight: cti: Make spinlock usage consistent coresight: cti: Fix register reads coresight: cti: Access ASICCTL only when implemented coresight: cti: Remove CPU power management code coresight: cti: Rename cti_active() to cti_is_active() coresight: cti: Remove hw_powered flag coresight: cti: Remove hw_enabled flag coresight: cti: Properly handle negative offsets in cti_reg32_{show|store}() drivers/hwtracing/coresight/coresight-cti-core.c | 278 ++++------------------ drivers/hwtracing/coresight/coresight-cti-sysfs.c | 171 ++++++------- drivers/hwtracing/coresight/coresight-cti.h | 13 +- 3 files changed, 137 insertions(+), 325 deletions(-) --- base-commit: eef33a7cce239783d0422526a4d786289a936f1b change-id: 20251223-arm_coresight_cti_refactor_v1-76e1bda8b716 Best regards, -- Leo Yan <leo.yan(a)arm.com>

3 months, 2 weeks

Re: [PATCH] drivers/hwtracing/coresight: remove unneeded variable in tmc_crashdata_release()

by Suzuki K Poulose

On Sat, 28 Feb 2026 18:23:44 -0400, Elsanti wrote: > The variable 'ret' is initialized to 0, never modified, and returned > directly. Remove it and return 0 explicitly. > > Applied, thanks! [1/1] drivers/hwtracing/coresight: remove unneeded variable in tmc_crashdata_release() https://git.kernel.org/coresight/c/061c39a17136 Best regards, -- Suzuki K Poulose <suzuki.poulose(a)arm.com>

3 months, 2 weeks

Re: [PATCH] drivers/hwtracing/coresight: remove unneeded variable in tmc_crashdata_release()

by Leo Yan

On Sat, Feb 28, 2026 at 06:23:44PM -0400, Elsanti wrote: > The variable 'ret' is initialized to 0, never modified, and returned > directly. Remove it and return 0 explicitly. > > Signed-off-by: Elsanti <santiagojoseleal27(a)gmail.com> Reviewed-by: Leo Yan <leo.yan(a)arm.com> > --- > drivers/hwtracing/coresight/coresight-tmc-core.c | 3 +-- > 1 file changed, 1 insertion(+), 2 deletions(-) > > diff --git a/drivers/hwtracing/coresight/coresight-tmc-core.c b/drivers/hwtracing/coresight/coresight-tmc-core.c > index 36599c431be6..e29012c451c5 100644 > --- a/drivers/hwtracing/coresight/coresight-tmc-core.c > +++ b/drivers/hwtracing/coresight/coresight-tmc-core.c > @@ -401,7 +401,6 @@ static ssize_t tmc_crashdata_read(struct file *file, char __user *data, > > static int tmc_crashdata_release(struct inode *inode, struct file *file) > { > - int ret = 0; > unsigned long flags; > struct tmc_resrv_buf *rbuf; > struct tmc_drvdata *drvdata = container_of(file->private_data, > @@ -414,7 +413,7 @@ static int tmc_crashdata_release(struct inode *inode, struct file *file) > raw_spin_unlock_irqrestore(&drvdata->spinlock, flags); > > dev_dbg(&drvdata->csdev->dev, "%s: released\n", __func__); > - return ret; > + return 0; > } > > static const struct file_operations tmc_crashdata_fops = { > -- > 2.53.0 > >

3 months, 2 weeks

Re: [PATCH v3 0/3] Enable CTCU and ETR devices for multiple QCOM platforms

by Suzuki K Poulose

Hello, On 04/02/2026 02:22, Jie Gan wrote: > The DT‑binding patch adds platform‑specific compatibles for the > CTCU device, and the following Qualcomm platforms are included: > Kaanapali > Pakala(sm8750) > Hamoa(x1e80100) > Glymur Given this is predominantly DTS changes, and there is very low chances of a conflict with the binding yaml change, I would recommend this to go via soc or the qcom platform tree. For the series: Acked-by: Suzuki K Poulose <suzuki.poulose(a)arm.com> > > Since the base Coresight DT patches for the Kaanapali and Glymur > platforms have not yet been applied, I created DT patches only > for the Pakala and Hamoa platforms. I will submit the Kaanapali > and Glymur patches once their corresponding base Coresight DT patches > are merged. > > The Hamoa‑related patches were posted in a separate email, and I > have included them in the current patch series. > > Link to the previous Hamoa patch series: > https://lore.kernel.org/all/20251106-enable-etr-and-ctcu-for-hamoa-v2-0-cdb… > > Signed-off-by: Jie Gan <jie.gan(a)oss.qualcomm.com> > --- > Changes in v3: > - change back to the numeric compatible from hamoa to x1e80100. > - Link to v2: https://lore.kernel.org/r/20260203-enable-ctcu-and-etr-v2-0-aacc7bd7eccb@os… > > Changes in v2: > - change back to the numeric compatible from pakala to sm8750. > - Link to v1: https://lore.kernel.org/r/20260203-enable-ctcu-and-etr-v1-0-a5371a2ec2b8@os… > > --- > Jie Gan (3): > dt-binding: document QCOM platforms for CTCU device > arm64: dts: qcom: hamoa: enable ETR and CTCU devices > arm64: dts: qcom: sm8750: enable ETR and CTCU devices > > .../bindings/arm/qcom,coresight-ctcu.yaml | 4 + > arch/arm64/boot/dts/qcom/hamoa.dtsi | 160 ++++++++++++++++++- > arch/arm64/boot/dts/qcom/sm8750.dtsi | 177 +++++++++++++++++++++ > 3 files changed, 340 insertions(+), 1 deletion(-) > --- > base-commit: 193579fe01389bc21aff0051d13f24e8ea95b47d > change-id: 20260203-enable-ctcu-and-etr-31f9e9d1088d > > Best regards,

3 months, 2 weeks

[PATCH v2] MAINTAINERS: Change e-mail address for reviewer

by Mike Leach

From: Mike Leach <mike.leach(a)linaro.org> My e-mail address for linux work is changing to mike.leach(a)arm.com from 1st Jan 2026. Update MAINTAINERS file accordingly Updated .mailmap file accordingly. Signed-off-by: Mike Leach <mike.leach(a)linaro.org> Signed-off-by: Mike Leach <mike.leach(a)arm.com> --- Changes since v1: Add sign off in new email & change .mailmap (Suzuki) --- .mailmap | 1 + MAINTAINERS | 4 ++-- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/.mailmap b/.mailmap index c124a1306d26..064c00568d20 100644 --- a/.mailmap +++ b/.mailmap @@ -566,6 +566,7 @@ Michel Lespinasse <michel(a)lespinasse.org> <walken(a)google.com> Michel Lespinasse <michel(a)lespinasse.org> <walken(a)zoy.org> Mickaël Salaün <mic(a)digikod.net> <mic(a)linux.microsoft.com> Miguel Ojeda <ojeda(a)kernel.org> <miguel.ojeda.sandonis(a)gmail.com> +Mike Leach <mike.leach(a)arm.com> <mike.leach(a)linaro.org> Mike Rapoport <rppt(a)kernel.org> <mike(a)compulab.co.il> Mike Rapoport <rppt(a)kernel.org> <mike.rapoport(a)gmail.com> Mike Rapoport <rppt(a)kernel.org> <rppt(a)linux.ibm.com> diff --git a/MAINTAINERS b/MAINTAINERS index 4d879f6a7b51..257d2fcb9651 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2719,7 +2719,7 @@ N: digicolor ARM/CORESIGHT FRAMEWORK AND DRIVERS M: Suzuki K Poulose <suzuki.poulose(a)arm.com> -R: Mike Leach <mike.leach(a)linaro.org> +R: Mike Leach <mike.leach(a)arm.com> R: James Clark <james.clark(a)linaro.org> L: coresight(a)lists.linaro.org (moderated for non-subscribers) L: linux-arm-kernel(a)lists.infradead.org (moderated for non-subscribers) @@ -20725,7 +20725,7 @@ PERFORMANCE EVENTS TOOLING ARM64 R: John Garry <john.g.garry(a)oracle.com> R: Will Deacon <will(a)kernel.org> R: James Clark <james.clark(a)linaro.org> -R: Mike Leach <mike.leach(a)linaro.org> +R: Mike Leach <mike.leach(a)arm.com> R: Leo Yan <leo.yan(a)linux.dev> L: linux-arm-kernel(a)lists.infradead.org (moderated for non-subscribers) S: Supported -- 2.43.0

3 months, 2 weeks

Re: [PATCH v6 01/12] dt-bindings: document access-controllers property for coresight peripherals

by Suzuki K Poulose

On 26/02/2026 10:54, Gatien CHEVALLIER wrote: > > > On 2/26/26 11:46, Suzuki K Poulose wrote: >> Hi >> >> On 26/02/2026 10:30, Gatien Chevallier wrote: >>> Document the access-controllers for coresight peripherals in case some >>> access checks need to be performed to use them. >>> >>> Signed-off-by: Gatien Chevallier <gatien.chevallier(a)foss.st.com> >>> Reviewed-by: Rob Herring (Arm) <robh(a)kernel.org> >>> --- >>> Documentation/devicetree/bindings/arm/arm,coresight- >>> cti.yaml | 3 +++ >>> .../devicetree/bindings/arm/arm,coresight-dynamic- >>> funnel.yaml | 3 +++ >>> Documentation/devicetree/bindings/arm/arm,coresight- >>> etm.yaml | 3 +++ >>> Documentation/devicetree/bindings/arm/arm,coresight- >>> stm.yaml | 3 +++ >>> Documentation/devicetree/bindings/arm/arm,coresight- >>> tmc.yaml | 3 +++ >>> Documentation/devicetree/bindings/arm/arm,coresight- >>> tpiu.yaml | 3 +++ >> >> Are you sure, you are not missing "replicator" in the list ? >> >> Otherwise, looks good to me. >> >> Acked-by: Suzuki K Poulose <suzuki.poulose(a)arm.com> >> > > The replicator is not present on the Linux side on stm32mp1x platforms > (Only present for the Cortex M4 co-processor on stm32mp15x platforms). > On stm32mp2x platforms, it will be necessary so it will be added in the > related P-R because we'll need the same debug access check mechanism. Fair enough. It looked a bit odd to me with TMC and TPIU both in the list without a Replicator. Acked-by: Suzuki K Poulose <suzuki.poulose(a)arm.com> > >> >> >>> 6 files changed, 18 insertions(+) >>> >>> diff --git a/Documentation/devicetree/bindings/arm/arm,coresight- >>> cti.yaml b/Documentation/devicetree/bindings/arm/arm,coresight-cti.yaml >>> index 2a91670ccb8c..949444aba1f8 100644 >>> --- a/Documentation/devicetree/bindings/arm/arm,coresight-cti.yaml >>> +++ b/Documentation/devicetree/bindings/arm/arm,coresight-cti.yaml >>> @@ -128,6 +128,9 @@ properties: >>> "#address-cells": >>> const: 1 >>> + access-controllers: >>> + maxItems: 1 >>> + >>> patternProperties: >>> '^trig-conns@([0-9]+)$': >>> type: object >>> diff --git a/Documentation/devicetree/bindings/arm/arm,coresight- >>> dynamic-funnel.yaml b/Documentation/devicetree/bindings/arm/ >>> arm,coresight-dynamic-funnel.yaml >>> index b74db15e5f8a..b0693cd46d27 100644 >>> --- a/Documentation/devicetree/bindings/arm/arm,coresight-dynamic- >>> funnel.yaml >>> +++ b/Documentation/devicetree/bindings/arm/arm,coresight-dynamic- >>> funnel.yaml >>> @@ -78,6 +78,9 @@ properties: >>> description: Output connection to CoreSight Trace bus >>> $ref: /schemas/graph.yaml#/properties/port >>> + access-controllers: >>> + maxItems: 1 >>> + >>> required: >>> - compatible >>> - reg >>> diff --git a/Documentation/devicetree/bindings/arm/arm,coresight- >>> etm.yaml b/Documentation/devicetree/bindings/arm/arm,coresight-etm.yaml >>> index 71f2e1ed27e5..10ebbbeadf93 100644 >>> --- a/Documentation/devicetree/bindings/arm/arm,coresight-etm.yaml >>> +++ b/Documentation/devicetree/bindings/arm/arm,coresight-etm.yaml >>> @@ -118,6 +118,9 @@ properties: >>> description: Output connection from the ETM to CoreSight >>> Trace bus. >>> $ref: /schemas/graph.yaml#/properties/port >>> + access-controllers: >>> + maxItems: 1 >>> + >>> required: >>> - compatible >>> - clocks >>> diff --git a/Documentation/devicetree/bindings/arm/arm,coresight- >>> stm.yaml b/Documentation/devicetree/bindings/arm/arm,coresight-stm.yaml >>> index 378380c3f5aa..f243e76f597f 100644 >>> --- a/Documentation/devicetree/bindings/arm/arm,coresight-stm.yaml >>> +++ b/Documentation/devicetree/bindings/arm/arm,coresight-stm.yaml >>> @@ -73,6 +73,9 @@ properties: >>> description: Output connection to the CoreSight Trace bus. >>> $ref: /schemas/graph.yaml#/properties/port >>> + access-controllers: >>> + maxItems: 1 >>> + >>> required: >>> - compatible >>> - reg >>> diff --git a/Documentation/devicetree/bindings/arm/arm,coresight- >>> tmc.yaml b/Documentation/devicetree/bindings/arm/arm,coresight-tmc.yaml >>> index 96dd5b5f771a..9dc096698c65 100644 >>> --- a/Documentation/devicetree/bindings/arm/arm,coresight-tmc.yaml >>> +++ b/Documentation/devicetree/bindings/arm/arm,coresight-tmc.yaml >>> @@ -128,6 +128,9 @@ properties: >>> - const: tracedata >>> - const: metadata >>> + access-controllers: >>> + maxItems: 1 >>> + >>> required: >>> - compatible >>> - reg >>> diff --git a/Documentation/devicetree/bindings/arm/arm,coresight- >>> tpiu.yaml b/Documentation/devicetree/bindings/arm/arm,coresight- >>> tpiu.yaml >>> index a207f6899e67..29bbc3961fdf 100644 >>> --- a/Documentation/devicetree/bindings/arm/arm,coresight-tpiu.yaml >>> +++ b/Documentation/devicetree/bindings/arm/arm,coresight-tpiu.yaml >>> @@ -70,6 +70,9 @@ properties: >>> description: Input connection from the CoreSight Trace bus. >>> $ref: /schemas/graph.yaml#/properties/port >>> + access-controllers: >>> + maxItems: 1 >>> + >>> required: >>> - compatible >>> - reg >>> >> >

3 months, 2 weeks

Re: [PATCH v6 01/12] dt-bindings: document access-controllers property for coresight peripherals

by Suzuki K Poulose

Hi On 26/02/2026 10:30, Gatien Chevallier wrote: > Document the access-controllers for coresight peripherals in case some > access checks need to be performed to use them. > > Signed-off-by: Gatien Chevallier <gatien.chevallier(a)foss.st.com> > Reviewed-by: Rob Herring (Arm) <robh(a)kernel.org> > --- > Documentation/devicetree/bindings/arm/arm,coresight-cti.yaml | 3 +++ > .../devicetree/bindings/arm/arm,coresight-dynamic-funnel.yaml | 3 +++ > Documentation/devicetree/bindings/arm/arm,coresight-etm.yaml | 3 +++ > Documentation/devicetree/bindings/arm/arm,coresight-stm.yaml | 3 +++ > Documentation/devicetree/bindings/arm/arm,coresight-tmc.yaml | 3 +++ > Documentation/devicetree/bindings/arm/arm,coresight-tpiu.yaml | 3 +++ Are you sure, you are not missing "replicator" in the list ? Otherwise, looks good to me. Acked-by: Suzuki K Poulose <suzuki.poulose(a)arm.com> > 6 files changed, 18 insertions(+) > > diff --git a/Documentation/devicetree/bindings/arm/arm,coresight-cti.yaml b/Documentation/devicetree/bindings/arm/arm,coresight-cti.yaml > index 2a91670ccb8c..949444aba1f8 100644 > --- a/Documentation/devicetree/bindings/arm/arm,coresight-cti.yaml > +++ b/Documentation/devicetree/bindings/arm/arm,coresight-cti.yaml > @@ -128,6 +128,9 @@ properties: > "#address-cells": > const: 1 > > + access-controllers: > + maxItems: 1 > + > patternProperties: > '^trig-conns@([0-9]+)$': > type: object > diff --git a/Documentation/devicetree/bindings/arm/arm,coresight-dynamic-funnel.yaml b/Documentation/devicetree/bindings/arm/arm,coresight-dynamic-funnel.yaml > index b74db15e5f8a..b0693cd46d27 100644 > --- a/Documentation/devicetree/bindings/arm/arm,coresight-dynamic-funnel.yaml > +++ b/Documentation/devicetree/bindings/arm/arm,coresight-dynamic-funnel.yaml > @@ -78,6 +78,9 @@ properties: > description: Output connection to CoreSight Trace bus > $ref: /schemas/graph.yaml#/properties/port > > + access-controllers: > + maxItems: 1 > + > required: > - compatible > - reg > diff --git a/Documentation/devicetree/bindings/arm/arm,coresight-etm.yaml b/Documentation/devicetree/bindings/arm/arm,coresight-etm.yaml > index 71f2e1ed27e5..10ebbbeadf93 100644 > --- a/Documentation/devicetree/bindings/arm/arm,coresight-etm.yaml > +++ b/Documentation/devicetree/bindings/arm/arm,coresight-etm.yaml > @@ -118,6 +118,9 @@ properties: > description: Output connection from the ETM to CoreSight Trace bus. > $ref: /schemas/graph.yaml#/properties/port > > + access-controllers: > + maxItems: 1 > + > required: > - compatible > - clocks > diff --git a/Documentation/devicetree/bindings/arm/arm,coresight-stm.yaml b/Documentation/devicetree/bindings/arm/arm,coresight-stm.yaml > index 378380c3f5aa..f243e76f597f 100644 > --- a/Documentation/devicetree/bindings/arm/arm,coresight-stm.yaml > +++ b/Documentation/devicetree/bindings/arm/arm,coresight-stm.yaml > @@ -73,6 +73,9 @@ properties: > description: Output connection to the CoreSight Trace bus. > $ref: /schemas/graph.yaml#/properties/port > > + access-controllers: > + maxItems: 1 > + > required: > - compatible > - reg > diff --git a/Documentation/devicetree/bindings/arm/arm,coresight-tmc.yaml b/Documentation/devicetree/bindings/arm/arm,coresight-tmc.yaml > index 96dd5b5f771a..9dc096698c65 100644 > --- a/Documentation/devicetree/bindings/arm/arm,coresight-tmc.yaml > +++ b/Documentation/devicetree/bindings/arm/arm,coresight-tmc.yaml > @@ -128,6 +128,9 @@ properties: > - const: tracedata > - const: metadata > > + access-controllers: > + maxItems: 1 > + > required: > - compatible > - reg > diff --git a/Documentation/devicetree/bindings/arm/arm,coresight-tpiu.yaml b/Documentation/devicetree/bindings/arm/arm,coresight-tpiu.yaml > index a207f6899e67..29bbc3961fdf 100644 > --- a/Documentation/devicetree/bindings/arm/arm,coresight-tpiu.yaml > +++ b/Documentation/devicetree/bindings/arm/arm,coresight-tpiu.yaml > @@ -70,6 +70,9 @@ properties: > description: Input connection from the CoreSight Trace bus. > $ref: /schemas/graph.yaml#/properties/port > > + access-controllers: > + maxItems: 1 > + > required: > - compatible > - reg >

3 months, 2 weeks

Re: [PATCH] coresight: ctcu: fix the spin_bug

by Suzuki K Poulose

On Thu, 19 Feb 2026 22:46:57 +0800, Jie Gan wrote: > Acquiring an uninitialized raw_spin_lock is invalid and may trigger > unexpected behavior or spin_bug. > > Applied, thanks! [1/1] coresight: ctcu: fix the spin_bug https://git.kernel.org/coresight/c/36ffbbc2b387 Best regards, -- Suzuki K Poulose <suzuki.poulose(a)arm.com>

3 months, 2 weeks

[PATCH 0/8] coresight: cti: Miscellaneous fixes and CPU PM cleanup

by Leo Yan

The CPU power management issue in the CTI driver was first observed in series [1]; this series resolves that issue. It fixes bugs and removes CPU PM operations from the CoreSight CTI driver, the goal is to use the CoreSight core layer as the central place for CPU power management. Removing CPU PM from CTI driver can avoid conflicts with the core layer. Based on review of the Arm ARM, ASICCTL is the only CTI register that could potentially reside in the CPU power domain. However, this is considered highly unlikely for the following reasons: - Standard Arm CTIs place the ASICCTL register in the debug power domain; - ASICCTL is implemented only when CTIDEVID.EXTMUXNUM is non-zero, which is rare for CPU CTIs. As a result, it is safe to remove the CPU PM code as done in this series. In addition, avoiding support local CPU access (via SMP calls) to ASICCTL significantly reduces driver complexity. If a future hardware implements ASICCTL in the CPU power domain, we can consider adding a property to describe that characteristic. That said, from a software point of view, keeping all CTI registers in the same power domain is preferable, as it makes the driver implementation much simpler. This series can be divided into: Patches 01 ~ 02: Fix spinlock with irqsave and register read with CS lock. Patches 03 ~ 08: Access ASICCTL condintioanlly, remove CPU PM code, and refactor register access in sysfs knob. This series is based on coresight-next branch and has been validated on Juno r1 and r2 platforms, pass normal sysfs and perf test, as well as CPU PM stress testing. [1] https://lore.kernel.org/all/20250915-arm_coresight_power_management_fix-v3-… Signed-off-by: Leo Yan <leo.yan(a)arm.com> --- Leo Yan (8): coresight: cti: Make spinlock usage consistent coresight: cti: Fix register reads coresight: cti: Access ASICCTL only when implemented coresight: cti: Remove CPU power management code coresight: cti: Rename cti_active() to cti_is_active() coresight: cti: Remove hw_powered flag coresight: cti: Remove hw_enabled flag coresight: cti: Refactor cti_reg32_{show|store}() drivers/hwtracing/coresight/coresight-cti-core.c | 278 ++++------------------ drivers/hwtracing/coresight/coresight-cti-sysfs.c | 168 ++++++------- drivers/hwtracing/coresight/coresight-cti.h | 13 +- 3 files changed, 134 insertions(+), 325 deletions(-) --- base-commit: eebe8dbd8630f51cf70b1f68a440cd3d7f7a914d change-id: 20251223-arm_coresight_cti_refactor_v1-76e1bda8b716 Best regards, -- Leo Yan <leo.yan(a)arm.com>

3 months, 3 weeks

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