On 03/03/2025 03:29, Jie Gan wrote:
> The trace_id will be stored in coresight_path instead of being declared
> everywhere and allocated after building the path.
>
> Co-developed-by: James Clark <james.clark(a)linaro.org>
> Signed-off-by: James Clark <james.clark(a)linaro.org>
> Signed-off-by: Jie Gan <quic_jiegan(a)quicinc.com>
> ---
> drivers/hwtracing/coresight/coresight-core.c | 44 +++++++++++++++++++
> .../hwtracing/coresight/coresight-etm-perf.c | 5 +--
> drivers/hwtracing/coresight/coresight-priv.h | 2 +
> drivers/hwtracing/coresight/coresight-sysfs.c | 4 ++
> 4 files changed, 52 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/hwtracing/coresight/coresight-core.c b/drivers/hwtracing/coresight/coresight-core.c
> index ed0e9368324d..6adc06995d76 100644
> --- a/drivers/hwtracing/coresight/coresight-core.c
> +++ b/drivers/hwtracing/coresight/coresight-core.c
> @@ -655,6 +655,50 @@ static void coresight_drop_device(struct coresight_device *csdev)
> }
> }
>
> +/*
> + * coresight device will read their existing or alloc a trace ID, if their trace_id
> + * callback is set.
> + *
> + * Return 0 if the trace_id callback is not set.
> + * Return the result of the trace_id callback if it is set. The return value
> + * will be the trace_id if successful, and an error number if it fails.
> + */
> +static int coresight_get_trace_id(struct coresight_device *csdev,
> + enum cs_mode mode,
> + struct coresight_device *sink)
> +{
> + if (coresight_ops(csdev)->trace_id)
> + return coresight_ops(csdev)->trace_id(csdev, mode, sink);
> +
> + return 0;
> +}
> +
> +/*
> + * Call this after creating the path and before enabling it. This leaves
> + * the trace ID set on the path, or it remains 0 if it couldn't be assigned.
> + */
> +void coresight_path_assign_trace_id(struct coresight_path *path,
> + enum cs_mode mode)
> +{
> + struct coresight_device *sink = coresight_get_sink(&path->path_list);
> + struct coresight_node *nd;
> + int trace_id;
> +
> + list_for_each_entry(nd, &path->path_list, link) {
> + /* Assign a trace ID to the path for the first device that wants to do it */
> + trace_id = coresight_get_trace_id(nd->csdev, mode, sink);
> +
> + /*
> + * 0 in this context is that it didn't want to assign so keep searching.
> + * Non 0 is either success or fail.
> + */
checkpatch complains:
WARNING: Block comments should align the * on each line
#65: FILE: drivers/hwtracing/coresight/coresight-core.c:694:
+ * Non 0 is either success or fail.
+ */
Please make sure to run the checkpatch on individual patches before
submitting in the future. I will fix this up locally for now.
Kind regards
Suzuki
> + if (trace_id != 0) {
> + path->trace_id = trace_id;
> + return;
> + }
> + }
> +}
> +
> /**
> * _coresight_build_path - recursively build a path from a @csdev to a sink.
> * @csdev: The device to start from.
> diff --git a/drivers/hwtracing/coresight/coresight-etm-perf.c b/drivers/hwtracing/coresight/coresight-etm-perf.c
> index b0426792f08a..134290ab622e 100644
> --- a/drivers/hwtracing/coresight/coresight-etm-perf.c
> +++ b/drivers/hwtracing/coresight/coresight-etm-perf.c
> @@ -319,7 +319,6 @@ static void *etm_setup_aux(struct perf_event *event, void **pages,
> {
> u32 id, cfg_hash;
> int cpu = event->cpu;
> - int trace_id;
> cpumask_t *mask;
> struct coresight_device *sink = NULL;
> struct coresight_device *user_sink = NULL, *last_sink = NULL;
> @@ -409,8 +408,8 @@ static void *etm_setup_aux(struct perf_event *event, void **pages,
> }
>
> /* ensure we can allocate a trace ID for this CPU */
> - trace_id = coresight_trace_id_get_cpu_id_map(cpu, &sink->perf_sink_id_map);
> - if (!IS_VALID_CS_TRACE_ID(trace_id)) {
> + coresight_path_assign_trace_id(path, CS_MODE_PERF);
> + if (!IS_VALID_CS_TRACE_ID(path->trace_id)) {
> cpumask_clear_cpu(cpu, mask);
> coresight_release_path(path);
> continue;
> diff --git a/drivers/hwtracing/coresight/coresight-priv.h b/drivers/hwtracing/coresight/coresight-priv.h
> index 27b7dc348d4a..2bea35bae0d4 100644
> --- a/drivers/hwtracing/coresight/coresight-priv.h
> +++ b/drivers/hwtracing/coresight/coresight-priv.h
> @@ -152,6 +152,8 @@ int coresight_make_links(struct coresight_device *orig,
> void coresight_remove_links(struct coresight_device *orig,
> struct coresight_connection *conn);
> u32 coresight_get_sink_id(struct coresight_device *csdev);
> +void coresight_path_assign_trace_id(struct coresight_path *path,
> + enum cs_mode mode);
>
> #if IS_ENABLED(CONFIG_CORESIGHT_SOURCE_ETM3X)
> extern int etm_readl_cp14(u32 off, unsigned int *val);
> diff --git a/drivers/hwtracing/coresight/coresight-sysfs.c b/drivers/hwtracing/coresight/coresight-sysfs.c
> index cb4c39732d26..d03751bf3d8a 100644
> --- a/drivers/hwtracing/coresight/coresight-sysfs.c
> +++ b/drivers/hwtracing/coresight/coresight-sysfs.c
> @@ -209,6 +209,10 @@ int coresight_enable_sysfs(struct coresight_device *csdev)
> goto out;
> }
>
> + coresight_path_assign_trace_id(path, CS_MODE_SYSFS);
> + if (!IS_VALID_CS_TRACE_ID(path->trace_id))
> + goto err_path;
> +
> ret = coresight_enable_path(&path->path_list, CS_MODE_SYSFS, NULL);
> if (ret)
> goto err_path;
On 2/26/2025 7:07 PM, Krzysztof Kozlowski wrote:
> On 26/02/2025 11:52, Yuanfang Zhang wrote:
>>
>>
>> On 2/22/2025 6:47 PM, Krzysztof Kozlowski wrote:
>>> On 21/02/2025 08:40, Yuanfang Zhang wrote:
>>>> Adds new coresight-tnoc.yaml file describing the bindings required
>>>> to define Trace NOC in the device trees.
>>>>
>>>> Signed-off-by: Yuanfang Zhang <quic_yuanfang(a)quicinc.com>
>>>
>>>
>>> So you just sent the same v1, ignoring previous review. That's not how
>>> it works.
>>>
>> sorry for this incorrect process. because i just update --to-cc list and no other
>> change, i forced the version to V1, hoped it would work like resend,
>> but the result was not as expected.
>
>
> But you got feedback, so why resending without implementing it? That's
> the problem, not you labeled/not-labeled it as resend.
>
got it, will implement it in next patch.
> Best regards,
> Krzysztof
Version 1.5.6 is now release.
Contains build fixes and documentation upates
Mike
--
Mike Leach
Principal Engineer, ARM Ltd.
Manchester Design Centre. UK
With current design, the name of the non-cpu bounded coresight
component is the device type with the number. And with 'ls' command
we can get the register address of the component. But from these
information, we can't know what the HW or system the component belongs
to. Add label in DT and show the hw information by reading label sysfs
node.
cti_sys0 -> ../../../devices/platform/soc(a)0/138f0000.cti/cti_sys0
cti_sys1 -> ../../../devices/platform/soc(a)0/13900000.cti/cti_sys1
tpdm0 -> ../../../devices/platform/soc(a)0/10b0d000.tpdm/tpdm0
tpdm1 -> ../../../devices/platform/soc(a)0/10c28000.tpdm/tpdm1
tpdm2 -> ../../../devices/platform/soc(a)0/10c29000.tpdm/tpdm2
/sys/bus/coresight/devices # cat cti*/label
cti_dlct_0
cti_dlct_1
cti_apss_0
cti_apss_1
cti_apss_2
Change since V6:
1. Update the date and verison in ABI file.
Change since V5:
1. Update the kernel version of ABI files.
2. Add link of different patch versions.
V5 link: https://patchwork.kernel.org/project/linux-arm-msm/cover/20241210122253.319…
Change since V4:
1. Add label in DT and add label sysfs node for each coresight device.
V4 link: https://patchwork.kernel.org/project/linux-arm-msm/cover/20240703122340.268…
Change since V3:
1. Change device-name to arm,cs-dev-name.
2. Add arm,cs-dev-name to only CTI and sources' dt-binding.
V3 link: https://patchwork.kernel.org/project/linux-arm-msm/cover/20240131082628.628…
Change since V2:
1. Fix the error in coresight core.
drivers/hwtracing/coresight/coresight-core.c:1775:7: error: assigning to 'char *' from 'const char *' discards qualifiers
2. Fix the warning when run dtbinding check.
Documentation/devicetree/bindings/arm/arm,coresight-cpu-debug.yaml: device-name: missing type definition
V2 link: https://patchwork.kernel.org/project/linux-arm-msm/cover/20240115164252.265…
Change since V1:
1. Change coresight-name to device name.
2. Add the device-name in coresight dt bindings.
V1 link: https://patchwork.kernel.org/project/linux-arm-kernel/patch/20230208110716.…
Mao Jinlong (2):
dt-bindings: arm: Add label in the coresight components
coresight: Add label sysfs node support
.../testing/sysfs-bus-coresight-devices-cti | 6 ++++
.../sysfs-bus-coresight-devices-funnel | 6 ++++
.../testing/sysfs-bus-coresight-devices-tpdm | 6 ++++
.../bindings/arm/arm,coresight-cti.yaml | 6 ++++
.../arm/arm,coresight-dummy-sink.yaml | 6 ++++
.../arm/arm,coresight-dummy-source.yaml | 6 ++++
.../arm/arm,coresight-dynamic-funnel.yaml | 6 ++++
.../arm/arm,coresight-dynamic-replicator.yaml | 6 ++++
.../arm/arm,coresight-static-funnel.yaml | 6 ++++
.../arm/arm,coresight-static-replicator.yaml | 6 ++++
.../bindings/arm/arm,coresight-tmc.yaml | 6 ++++
.../bindings/arm/qcom,coresight-tpda.yaml | 6 ++++
.../bindings/arm/qcom,coresight-tpdm.yaml | 6 ++++
drivers/hwtracing/coresight/coresight-sysfs.c | 32 +++++++++++++++++++
14 files changed, 110 insertions(+)
--
2.25.1
On Wed, 26 Feb 2025 12:29:13 +0100, Krzysztof Kozlowski wrote:
> Binding listed variable number of IO addresses without defining them,
> however example DTS code, all in-tree DTS and Linux kernel driver
> mention only one address space, so drop the second to make binding
> precise and correctly describe the hardware.
>
>
Applied, thanks!
[1/2] dt-bindings: coresight: qcom,coresight-tpda: Fix too many 'reg'
https://git.kernel.org/coresight/c/d72deaf0
[2/2] dt-bindings: coresight: qcom,coresight-tpdm: Fix too many 'reg'
https://git.kernel.org/coresight/c/1e4e4542
Best regards,
--
Suzuki K Poulose <suzuki.poulose(a)arm.com>
Introduction of TPDM MCMB(Multi-lane Continuous Multi Bit) subunit
MCMB (Multi-lane CMB) is a special form of CMB dataset type. MCMB
subunit has the same number and usage of registers as CMB subunit.
Just like the CMB subunit, the MCMB subunit must be configured prior
to enablement. This series adds support for TPDM to configure the
MCMB subunit.
Once this series patches are applied properly, the new tpdm nodes for
should be observed at the tpdm path /sys/bus/coresight/devices/tpdm*
which supports MCMB subunit. All sysfs files of CMB subunit TPDM are
included in MCMB subunit TPDM. On this basis, MCMB subunit TPDM will
have new sysfs files to select and enable the lane.
Changes in V4:
1. Update the date and kernel verison in ABI file.
2. Update the year of copyright.
Changes in V3:
1. Update the date in ABI file.
2. Remove the unrelated change.
3. Correct typo.
4. Move the CMB_CR related definitions together.
Changes in V2:
1. Use tdpm_data->cmb instead of (tpdm_has_cmb_dataset(tpdm_data) ||
tpdm_has_mcmb_dataset(tpdm_data)) for cmb dataset support.
2. Embed mcmb_dataset struct into cmb struct.
3. Update the date and version in sysfs-bus-coresight-devices-tpdm
Link: https://patchwork.kernel.org/project/linux-arm-msm/patch/20241105123940.396…
Mao Jinlong (1):
coresight-tpdm: Add MCMB dataset support
Tao Zhang (2):
coresight-tpdm: Add support to select lane
coresight-tpdm: Add support to enable the lane for MCMB TPDM
.../testing/sysfs-bus-coresight-devices-tpdm | 15 +++
drivers/hwtracing/coresight/coresight-tpda.c | 7 +-
drivers/hwtracing/coresight/coresight-tpdm.c | 120 +++++++++++++++++-
drivers/hwtracing/coresight/coresight-tpdm.h | 33 +++--
4 files changed, 155 insertions(+), 20 deletions(-)
--
2.17.1
On 2/26/2025 7:09 PM, Krzysztof Kozlowski wrote:
> On 26/02/2025 12:05, Yuanfang Zhang wrote:
>> +
>> + compatible:
>> + items:
>> + - const: qcom,coresight-tnoc
>> + - const: arm,primecell
>> +
>> + reg:
>> + minItems: 1
>> + maxItems: 2
>> + description:
>> + Physical address space of the device.
> Not much improved - still items are not listed. Which binding did you
> choose as an example as I asked to? (so I can fix it)
>
qcom,coresight-tpda.yaml
> Best regards,
> Krzysztof