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Re: [PATCH v3 1/7] dt-bindings: arm: Add support for Coresight TGU trace

by Mike Leach

Hi, On Tue, 4 Mar 2025 at 08:05, Krzysztof Kozlowski <krzk(a)kernel.org> wrote: > > On Thu, Feb 27, 2025 at 05:26:34PM +0800, songchai wrote: > > From: Songwei Chai <quic_songchai(a)quicinc.com> > > > > The Trigger Generation Unit (TGU) is designed to detect patterns or > > sequences within a specific region of the System on Chip (SoC). Once > > configured and activated, it monitors sense inputs and can detect a > > pre-programmed state or sequence across clock cycles, subsequently > > producing a trigger. > > > > TGU configuration space > > offset table > > x-------------------------x > > | | > > | | > > | | Step configuration > > | | space layout > > | coresight management | x-------------x > > | registers | |---> | | > > | | | | reserve | > > | | | | | > > |-------------------------| | |-------------| > > | | | | priority[3] | > > | step[7] |<-- | |-------------| > > |-------------------------| | | | priority[2] | > > | | | | |-------------| > > | ... | |Steps region | | priority[1] | > > | | | | |-------------| > > |-------------------------| | | | priority[0] | > > | |<-- | |-------------| > > | step[0] |--------------------> | | > > |-------------------------| | condition | > > | | | | > > | control and status | x-------------x > > | space | | | > > x-------------------------x |Timer/Counter| > > | | > > x-------------x > > TGU Configuration in Hardware > > > > The TGU provides a step region for user configuration, similar > > to a flow chart. Each step region consists of three register clusters: > > > > 1.Priority Region: Sets the required signals with priority. > > 2.Condition Region: Defines specific requirements (e.g., signal A > > reaches three times) and the subsequent action once the requirement is > > met. > > 3.Timer/Counter (Optional): Provides timing or counting functionality. > > > > Add a new coresight-tgu.yaml file to describe the bindings required to > > define the TGU in the device trees. > > > > Signed-off-by: Songwei Chai <quic_songchai(a)quicinc.com> > > Signed-off-by: songchai <quic_songchai(a)quicinc.com> > > Don't duplicate yourself. > > Anyway, this is marked as v3, I cannot find previous versions, no > changelog, no references. > > What happened here in this binding? > > > --- > > .../bindings/arm/qcom,coresight-tgu.yaml | 135 ++++++++++++++++++ > > 1 file changed, 135 insertions(+) > > create mode 100644 Documentation/devicetree/bindings/arm/qcom,coresight-tgu.yaml > > > > diff --git a/Documentation/devicetree/bindings/arm/qcom,coresight-tgu.yaml b/Documentation/devicetree/bindings/arm/qcom,coresight-tgu.yaml > > new file mode 100644 > > index 000000000000..a41ac68a4fe7 > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/arm/qcom,coresight-tgu.yaml > > @@ -0,0 +1,135 @@ > > +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause > > +# Copyright (c) 2023-2025 Qualcomm Innovation Center, Inc. All rights reserved. > > 2023 and 2024? Where was it published in these years? > > > +%YAML 1.2 > > +--- > > +$id: http://devicetree.org/schemas/arm/qcom,coresight-tgu.yaml# > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > + > > +title: Trigger Generation Unit - TGU > > + > > +description: | > > + The Trigger Generation Unit (TGU) is a Data Engine which can be utilized > > + to sense a plurality of signals and create a trigger into the CTI or > > + generate interrupts to processors. The TGU is like the trigger circuit > > + of a Logic Analyzer. The corresponding trigger logic can be realized by > > + configuring the conditions for each step after sensing the signal. > > + Once setup and enabled, it will observe sense inputs and based upon > > + the activity of those inputs, even over clock cycles, may detect a > > + preprogrammed state/sequence and then produce a trigger or interrupt. > > + > > + The primary use case of the TGU is to detect patterns or sequences on a > > + given set of signals within some region of the SoC. > > + > > +maintainers: > > + - Mao Jinlong <quic_jinlmao(a)quicinc.com> > > + - Sam Chai <quic_songchai(a)quicinc.com> > > + > > +# Need a custom select here or 'arm,primecell' will match on lots of nodes > > +select: > > + properties: > > + compatible: > > + contains: > > + enum: > > + - qcom,coresight-tgu > > + required: > > + - compatible > > + > > +properties: > > + compatible: > > + items: > > + - const: qcom,coresight-tgu > > + - const: arm,primecell > > + > > + reg: > > + maxItems: 1 > > + > > + clocks: > > + maxItems: 1 > > + > > + clock-names: > > + items: > > + - const: apb_pclk > > + > > + qcom,tgu-steps: > > + description: > > + The trigger logic is realized by configuring each step after sensing > > + the signal. The parameter here is used to describe the maximum of steps > > + that could be configured in the current TGU. > > + $ref: /schemas/types.yaml#/definitions/uint32 > > + minimum: 1 > > + maximum: 8 > > + Hardware features are usually defined by ID registers in coresight devices. e.g. ETM has a number of ID registers that describe the number of comparators / counters etc. Does this device not have similar registers? Is there not a unique ID for each hardware variant - hardware discoverablility is an architecture requirement for coresight devices? > > + qcom,tgu-regs: > > + description: > > + There are some "groups" register clusters in each step, which are used to > > + configure the signal that we want to detect. Meanwhile, each group has its > > + own priority, and the priority increases with number of groups. For example, > > + group3 has a higher priority than group2, the signal configured in group3 > > + will be sensed more preferentially than the signal which is configured in group2. > > + The parameter here is used to describe the signal number that each group > > + could be configured. > > And all groups are indexed by number? Or do they have names? > > > + $ref: /schemas/types.yaml#/definitions/uint32 > > + minimum: 1 > > + maximum: 18 > > + > > + qcom,tgu-conditions: > > + description: > > + A condition sets a specific requirement for a step and defines the subsequent > > + action once the requirement is met. For example, in step two, if signal A is > > + detected three times, the process jumps back to step one. The parameter describes > > + the register number for each functionality, whether it is setting a specific > > + requirement or defining a subsequent action. > > + $ref: /schemas/types.yaml#/definitions/uint32 > > + minimum: 1 > > + maximum: 4 > > + > > + qcom,tgu-timer-counters: > > + description: > > + TGU has timer and counter which are used to set some requirement on each step. > > Wrap according to Linux coding style, so at 80. > > > + For example, we could use counter to create a trigger into CTI once TGU senses > > + the target signal three times.This parameter is used to describe the number of > > + Timers/Counters in TGU. > > + $ref: /schemas/types.yaml#/definitions/uint32 > > + minimum: 0 > > Drop > > > + maximum: 2 > > + > > + in-ports: > > + $ref: /schemas/graph.yaml#/properties/ports > > + additionalProperties: false > > + > > + properties: > > + port: > > + description: AXI Slave connected to another Coresight component > > So this TGU can be connected to anything in coresight graph, no > restrictions? > Coresight uses APB for register access and ATB for moving trace from source to sink. The only use of AXI is on the ETR/CATU output saving trace data into system memory. > > + $ref: /schemas/graph.yaml#/properties/port > > + > > +required: > > + - compatible > > + - reg > > + - clocks > > + - clock-names > > Most likely you miss also: in-ports > > > Best regards, > Krzysztof > Regards Mike -- Mike Leach Principal Engineer, ARM Ltd. Manchester Design Centre. UK

4 months, 1 week

Re: [PATCH v3 0/7] Provides support for Trigger Generation Unit

by Mike Leach

Hi, On Thu, 27 Feb 2025 at 09:27, songchai <quic_songchai(a)quicinc.com> wrote: > > Provide support for the TGU (Trigger Generation Unit), which can be > utilized to sense a plurality of signals and create a trigger into > the CTI or generate interrupts to processors once the input signal > meets the conditions. We can treat the TGU’s workflow as a flowsheet, > it has some “steps” regions for customization. In each step region, > we can set the signals that we want with priority in priority_group, set > the conditions in each step via condition_decode, and set the resultant > action by condition_select. Meanwhile, some TGUs (not all) also provide > timer/counter functionality. Based on the characteristics described > above, we consider the TGU as a helper in the CoreSight subsystem. > Its master device is the TPDM, which can transmit signals from other > subsystems, and we reuse the existing ports mechanism to link the TPDM to > the connected TGU. > I do not believe that his component is part of the Coresight subsystem. 1) It inputs multiple signals from the SoC to process and create an trigger event - however, it can do this irrespective of CoreSight trace being operational, especially where generating interrupts for processors, or triggers for other non-coresight components. It would appear that the TPDM can send output to more than just the TDPA which generates coresight trace packets - a previously undisclosed feature. 2) The ports mechanism is a generic device tree mechanism, not something unique to the Coresight subsystem. 3) The CTI trigger connection will be defined in devicetree under the CTI component, as this is the interface between this component and coresight. As such this seems more like a general performance and debug component, with optional inputs to the coresight trigger mechanisms, rather than being a coresight component itself. Other SoCs have non-coresight component inputs to CTIs. For example the PL011 serial device on Juno has a signal into one of the system CTIs. > Here is a detailed example to explain how to use the TGU: > > In this example, the TGU is configured to use 2 conditions, 2 steps, and > the timer. The goal is to look for one of two patterns which are generated > from TPDM, giving priority to one, and then generate a trigger once the > timer reaches a certain value. In other words, two conditions are used > for the first step to look for the two patterns, where the one with the > highest priority is used in the first condition. Then, in the second step, > the timer is enabled and set to be compared to the given value at each > clock cycle. These steps are better shown below. > > > |-----------------| > | | > | TPDM | > | | > |-----------------| > | > | > --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- ------ > | | | > | | |--------------------| | > | |---- ---> | | Go to next steps | | > | | | |--- ---> | Enable timer | | > | | v | | | | > | | |-----------------| | |--------------------| | > | | | | Yes | | | > | | | inputs==0xB | ----->| | <-------- | > | | | | | | No | | > | No | |-----------------| | v | | > | | | | |-----------------| | | > | | | | | | | | > | | | | | timer>=3 |-- | > | | v | | | | > | | |-----------------| | |-----------------| | > | | | | Yes | | | > | |--- | inputs==0xA | ----->| | Yes | > | | | | | > | |-----------------| v | > | |-----------------| | > | | | | > | | Trigger | | > | | | | > | |-----------------| | > | TGU | | > |--- --- --- --- --- --- --- --- --- --- --- --- --- --- |--- --- -- | > | > v > |-----------------| > |The controllers | > |which will use | > |triggers further | > |-----------------| > > steps: > 1. Reset TGU /*it will disable tgu and reset dataset*/ > - echo 1 > /sys/bus/coresight/devices/<tgu-name>/reset_tgu > > 2. Set the pattern match for priority0 to 0xA = 0b1010 and for > priority 1 to 0xB = 0b1011. > - echo 0x11113232 > /sys/bus/coresight/devices/<tgu-name>/step0_priority0/reg0 > - echo 0x11113233 > /sys/bus/coresight/devices/<tgu-name>/step0_priority1/reg0 > > Note: > Bit distribution diagram for each priority register > |-------------------------------------------------------------------| > | Bits | Field Nam | Description | > |-------------------------------------------------------------------| > | | | 00 = bypass for OR output | > | 29:28 | SEL_BIT7_TYPE2 | 01 = bypass for AND output | > | | | 10 = sense input '0' is true| > | | | 11 = sense input '1' is true| > |-------------------------------------------------------------------| > | | | 00 = bypass for OR output | > | 25:24 | SEL_BIT6_TYPE2 | 01 = bypass for AND output | > | | | 10 = sense input '0' is true| > | | | 11 = sense input '1' is true| > |-------------------------------------------------------------------| > | | | 00 = bypass for OR output | > | 21:20 | SEL_BIT5_TYPE2 | 01 = bypass for AND output | > | | | 10 = sense input '0' is true| > | | | 11 = sense input '1' is true| > |-------------------------------------------------------------------| > | | | 00 = bypass for OR output | > | 17:16 | SEL_BIT4_TYPE2 | 01 = bypass for AND output | > | | | 10 = sense input '0' is true| > | | | 11 = sense input '1' is true| > |-------------------------------------------------------------------| > | | | 00 = bypass for OR output | > | 13:12 | SEL_BIT3_TYPE2 | 01 = bypass for AND output | > | | | 10 = sense input '0' is true| > | | | 11 = sense input '1' is true| > |-------------------------------------------------------------------| > | | | 00 = bypass for OR output | > | 9:8 | SEL_BIT2_TYPE2 | 01 = bypass for AND output | > | | | 10 = sense input '0' is true| > | | | 11 = sense input '1' is true| > |-------------------------------------------------------------------| > | | | 00 = bypass for OR output | > | 5:4 | SEL_BIT1_TYPE2 | 01 = bypass for AND output | > | | | 10 = sense input '0' is true| > | | | 11 = sense input '1' is true| > |-------------------------------------------------------------------| > | | | 00 = bypass for OR output | > | 1:0 | SEL_BIT0_TYPE2 | 01 = bypass for AND output | > | | | 10 = sense input '0' is true| > | | | 11 = sense input '1' is true| > |-------------------------------------------------------------------| > These bits are used to identify the signals we want to sense, with > a maximum signal number of 140. For example, to sense the signal > 0xA (binary 1010), we set the value of bits 0 to 13 to 3232, which > represents 1010. The remaining bits are set to 1, as we want to use > AND gate to summarize all the signals we want to sense here. For > rising or falling edge detection of any input to the priority, set > the remaining bits to 0 to use an OR gate. > > 3. look for the pattern for priority_i i=0,1. > - echo 0x3 > /sys/bus/coresight/devices/<tgu-name>/step0_condition_decode/reg0 > - echo 0x30 > /sys/bus/coresight/devices/<tgu-name>/step0_condition_decode/reg1 > > |-------------------------------------------------------------------------------| > | Bits | Field Nam | Description | > |-------------------------------------------------------------------------------| > | | |For each decoded condition, this | > | 24 | NOT |inverts the output. If the condition | > | | |decodes to true, and the NOT field | > | | |is '1', then the output is NOT true. | > |-------------------------------------------------------------------------------| > | | |When '1' the output from the associated| > | 21 | BC0_COMP_ACTIVE |comparator will be actively included in| > | | |the decoding of this particular | > | | |condition. | > |-------------------------------------------------------------------------------| > | | |When '1' the output from the associated| > | | |comparator will need to be 1 to affect | > | 20 | BC0_COMP_HIGH |the decoding of this condition. | > | | |Conversely, a '0' here requires a '0' | > | | |from the comparator | > |-------------------------------------------------------------------------------| > | | |When '1' the output from the associated| > | 17 | |comparator will be actively included in| > | | TC0_COMP_ACTIVE |the decoding of this particular | > | | |condition. | > |-------------------------------------------------------------------------------| > | | |When '1' the output from the associated| > | | |comparator will need to be 1 to affect | > | 16 | TC0_COMP_HIGH |the decoding of this particular | > | | |condition.Conversely, a 0 here | > | | |requires a '0' from the comparator | > |-------------------------------------------------------------------------------| > | | |When '1' the output from Priority_n | > | | |OR logic will be actively | > | 4n+3 | Priority_n_OR_ACTIVE|included in the decoding of | > | | (n=0,1,2,3) |this particular condition. | > | | | | > |-------------------------------------------------------------------------------| > | | |When '1' the output from Priority_n | > | | |will need to be '1' to affect the | > | 4n+2 | Priority_n_OR_HIGH |decoding of this particular | > | | (n=0,1,2,3) |condition. Conversely, a '0' here | > | | |requires a '0' from Priority_n OR logic| > |-------------------------------------------------------------------------------| > | | |When '1' the output from Priority_n | > | | |AND logic will be actively | > | 4n+1 |Priority_n_AND_ACTIVE|included in the decoding of this | > | | (n=0,1,2,3) |particular condition. | > | | | | > |-------------------------------------------------------------------------------| > | | |When '1' the output from Priority_n | > | | |AND logic will need to be '1' to | > | 4n | Priority_n_AND_HIGH |affect the decoding of this | > | | (n=0,1,2,3) |particular condition. Conversely, | > | | |a '0' here requires a '0' from | > | | |Priority_n AND logic. | > |-------------------------------------------------------------------------------| > Since we use `priority_0` and `priority_1` with an AND output in step 2, we set `0x3` > and `0x30` here to activate them. > > 4. Set NEXT_STEP = 1 and TC0_ENABLE = 1 so that when the conditions > are met then the next step will be step 1 and the timer will be enabled. > - echo 0x20008 > /sys/bus/coresight/devices/<tgu-name>/step0_condition_select/reg0 > - echo 0x20008 > /sys/bus/coresight/devices/<tgu-name>/step0_condition_select/reg1 > > |-----------------------------------------------------------------------------| > | Bits | Field Nam | Description | > |-----------------------------------------------------------------------------| > | | |This field defines the next step the | > | 18:17 | NEXT_STEP |TGU will 'goto' for the associated | > | | |Condition and Step. | > |-----------------------------------------------------------------------------| > | | |For each possible output trigger | > | 13 | TRIGGER |available, set a '1' if you want | > | | |the trigger to go active for the | > | | |associated condition and Step. | > |-----------------------------------------------------------------------------| > | | |This will cause BC0 to increment if the| > | 9 | BC0_INC |associated Condition is decoded for | > | | |this step. | > |-----------------------------------------------------------------------------| > | | |This will cause BC0 to decrement if the| > | 8 | BC0_DEC |associated Condition is decoded for | > | | |this step. | > |-----------------------------------------------------------------------------| > | | |This will clear BC0 count value to 0 if| > | 7 | BC0_CLEAR |the associated Condition is decoded | > | | |for this step. | > |-----------------------------------------------------------------------------| > | | |This will cause TC0 to increment until | > | 3 | TC0_ENABLE |paused or cleared if the associated | > | | |Condition is decoded for this step. | > |-----------------------------------------------------------------------------| > | | |This will cause TC0 to pause until | > | 2 | TC0_PAUSE |enabled if the associated Condition | > | | |is decoded for this step. | > |-----------------------------------------------------------------------------| > | | |This will clear TC0 count value to 0 | > | 1 | TC0_CLEAR |if the associated Condition is | > | | |decoded for this step. | > |-----------------------------------------------------------------------------| > | | |This will set the done signal to the | > | 0 | DONE |TGU FSM if the associated Condition | > | | |is decoded for this step. | > |-----------------------------------------------------------------------------| > Based on the distribution diagram, we set `0x20008` for `priority0` and `priority1` to > achieve "jump to step 1 and enable TC0" once the signal is sensed. > > 5. activate the timer comparison for this step. > - echo 0x30000 > /sys/bus/coresight/devices/<tgu-name>/step1_condition_decode/reg0 > > |-------------------------------------------------------------------------------| > | | |When '1' the output from the associated| > | 17 | |comparator will be actively included in| > | | TC0_COMP_ACTIVE |the decoding of this particular | > | | |condition. | > |-------------------------------------------------------------------------------| > | | |When '1' the output from the associated| > | | |comparator will need to be 1 to affect | > | 16 | TC0_COMP_HIGH |the decoding of this particular | > | | |condition.Conversely, a 0 here | > | | |requires a '0' from the comparator | > |-------------------------------------------------------------------------------| > Accroding to the decode distribution diagram , we give 0x30000 here to set 16th&17th bit > to enable timer comparison. > > 6. Set the NEXT_STEP = 0 and TC0_PAUSE = 1 and TC0_CLEAR = 1 once the timer > has reached the given value. > - echo 0x6 > /sys/bus/coresight/devices/<tgu-name>/step1_condition_select/reg0 > > 7. Enable Trigger 0 for TGU when the condition 0 is met in step1, > i.e. when the timer reaches 3. > - echo 0x2000 > /sys/bus/coresight/devices/<tgu-name>/step1_condition_select/default > > Note: > 1. 'default' register allows for establishing the resultant action for > the default condition > > 2. Trigger:For each possible output trigger available from > the Design document, there are three triggers: interrupts, CTI, > and Cross-TGU mapping.All three triggers can occur, but > the choice of which trigger to use depends on the user's > needs. > > 8. Compare the timer to 3 in step 1. > - echo 0x3 > /sys/bus/coresight/devices/<tgu-name>/step1_timer/reg0 > > 9. enale tgu > - echo 1 > /sys/bus/coresight/devices/<tgu-name>/enable_tgu > If this is version 3 - where is the list of differences from versions 1 - 2? > Songwei Chai (7): > dt-bindings: arm: Add support for Coresight TGU trace > coresight: Add coresight TGU driver > coresight-tgu: Add signal priority support > coresight-tgu: Add TGU decode support > coresight-tgu: add support to configure next action > coresight-tgu: add timer/counter functionality for TGU > coresight-tgu: add reset node to initialize > > .../testing/sysfs-bus-coresight-devices-tgu | 51 ++ > .../bindings/arm/qcom,coresight-tgu.yaml | 135 ++++ > drivers/hwtracing/coresight/Kconfig | 11 + > drivers/hwtracing/coresight/Makefile | 1 + > drivers/hwtracing/coresight/coresight-tgu.c | 669 ++++++++++++++++++ > drivers/hwtracing/coresight/coresight-tgu.h | 242 +++++++ > 6 files changed, 1109 insertions(+) > create mode 100644 Documentation/ABI/testing/sysfs-bus-coresight-devices-tgu > create mode 100644 Documentation/devicetree/bindings/arm/qcom,coresight-tgu.yaml > create mode 100644 drivers/hwtracing/coresight/coresight-tgu.c > create mode 100644 drivers/hwtracing/coresight/coresight-tgu.h > Regards Mike -- Mike Leach Principal Engineer, ARM Ltd. Manchester Design Centre. UK

4 months, 2 weeks

Re: [PATCH v3 2/7] coresight: Add coresight TGU driver

by Mike Leach

Hi, On Thu, 27 Feb 2025 at 09:27, songchai <quic_songchai(a)quicinc.com> wrote: > > From: Songwei Chai <quic_songchai(a)quicinc.com> > > Add driver to support Coresight device TGU (Trigger Generation Unit). > TGU is a Data Engine which can be utilized to sense a plurality of > signals and create a trigger into the CTI or generate interrupts to > processors. Add probe/enable/disable functions for tgu. > > Signed-off-by: Songwei Chai <quic_songchai(a)quicinc.com> > Signed-off-by: songchai <quic_songchai(a)quicinc.com> > --- > .../testing/sysfs-bus-coresight-devices-tgu | 9 + > drivers/hwtracing/coresight/Kconfig | 11 + > drivers/hwtracing/coresight/Makefile | 1 + > drivers/hwtracing/coresight/coresight-tgu.c | 218 ++++++++++++++++++ > drivers/hwtracing/coresight/coresight-tgu.h | 36 +++ > 5 files changed, 275 insertions(+) > create mode 100644 Documentation/ABI/testing/sysfs-bus-coresight-devices-tgu > create mode 100644 drivers/hwtracing/coresight/coresight-tgu.c > create mode 100644 drivers/hwtracing/coresight/coresight-tgu.h > > diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tgu b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tgu > new file mode 100644 > index 000000000000..741bc9fd9df5 > --- /dev/null > +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tgu > @@ -0,0 +1,9 @@ > +What: /sys/bus/coresight/devices/<tgu-name>/enable_tgu > +Date: February 2025 > +KernelVersion 6.15 > +Contact: Jinlong Mao (QUIC) <quic_jinlmao(a)quicinc.com>, Sam Chai (QUIC) <quic_songchai(a)quicinc.com> > +Description: > + (RW) Set/Get the enable/disable status of TGU > + Accepts only one of the 2 values - 0 or 1. > + 0 : disable TGU. > + 1 : enable TGU. > diff --git a/drivers/hwtracing/coresight/Kconfig b/drivers/hwtracing/coresight/Kconfig > index 06f0a7594169..3fe59c745dd4 100644 > --- a/drivers/hwtracing/coresight/Kconfig > +++ b/drivers/hwtracing/coresight/Kconfig > @@ -247,4 +247,15 @@ config CORESIGHT_DUMMY > > To compile this driver as a module, choose M here: the module will be > called coresight-dummy. > + > +config CORESIGHT_TGU > + tristate "CoreSight Trigger Generation Unit driver" > + help > + This driver provides support for Trigger Generation Unit that is > + used to detect patterns or sequences on a given set of signals. > + TGU is used to monitor a particular bus within a given region to > + detect illegal transaction sequences or slave responses. It is also > + used to monitor a data stream to detect protocol violations and to > + provide a trigger point for centering data around a specific event > + within the trace data buffer. > endif > diff --git a/drivers/hwtracing/coresight/Makefile b/drivers/hwtracing/coresight/Makefile > index 4ba478211b31..7c2b9e9cf1cd 100644 > --- a/drivers/hwtracing/coresight/Makefile > +++ b/drivers/hwtracing/coresight/Makefile > @@ -51,3 +51,4 @@ coresight-cti-y := coresight-cti-core.o coresight-cti-platform.o \ > coresight-cti-sysfs.o > obj-$(CONFIG_ULTRASOC_SMB) += ultrasoc-smb.o > obj-$(CONFIG_CORESIGHT_DUMMY) += coresight-dummy.o > +obj-$(CONFIG_CORESIGHT_TGU) += coresight-tgu.o > diff --git a/drivers/hwtracing/coresight/coresight-tgu.c b/drivers/hwtracing/coresight/coresight-tgu.c > new file mode 100644 > index 000000000000..da4c04ac1097 > --- /dev/null > +++ b/drivers/hwtracing/coresight/coresight-tgu.c > @@ -0,0 +1,218 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights reserved. > + */ > + > +#include <linux/amba/bus.h> > +#include <linux/coresight.h> > +#include <linux/device.h> > +#include <linux/err.h> > +#include <linux/io.h> > +#include <linux/kernel.h> > +#include <linux/module.h> > +#include <linux/of.h> > + > +#include "coresight-priv.h" > +#include "coresight-tgu.h" > + > +DEFINE_CORESIGHT_DEVLIST(tgu_devs, "tgu"); > + > +static void tgu_write_all_hw_regs(struct tgu_drvdata *drvdata) > +{ > + CS_UNLOCK(drvdata->base); > + /* Enable TGU to program the triggers */ > + tgu_writel(drvdata, 1, TGU_CONTROL); > + CS_LOCK(drvdata->base); > +} > + > +static int tgu_enable(struct coresight_device *csdev, enum cs_mode mode, > + void *data) > +{ > + struct tgu_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); > + > + spin_lock(&drvdata->spinlock); > + > + if (drvdata->enable) { > + spin_unlock(&drvdata->spinlock); > + return -EBUSY; > + } > + tgu_write_all_hw_regs(drvdata); > + drvdata->enable = true; > + > + spin_unlock(&drvdata->spinlock); > + return 0; > +} > + > +static int tgu_disable(struct coresight_device *csdev, void *data) > +{ > + struct tgu_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); > + > + spin_lock(&drvdata->spinlock); > + > + if (!drvdata->enable) { Could simplify by changing logic here - if (enable) { do disable stuff } and have a single return point > + spin_unlock(&drvdata->spinlock); > + return 0; > + } > + > + CS_UNLOCK(drvdata->base); > + tgu_writel(drvdata, 0, TGU_CONTROL); > + CS_LOCK(drvdata->base); > + > + drvdata->enable = false; > + spin_unlock(&drvdata->spinlock); > + return 0; > +} > + > +static ssize_t enable_tgu_show(struct device *dev, > + struct device_attribute *attr, char *buf) > +{ > + bool enabled; > + > + struct tgu_drvdata *drvdata = dev_get_drvdata(dev->parent); > + > + spin_lock(&drvdata->spinlock); > + enabled = drvdata->enable; > + spin_unlock(&drvdata->spinlock); > + > + return sprintf(buf, "%d\n", enabled); sysfs_emit() should be used here. > +} > + > +/* enable_tgu_store - Configure Trace and Gating Unit (TGU) triggers. */ > +static ssize_t enable_tgu_store(struct device *dev, > + struct device_attribute *attr, const char *buf, > + size_t size) > +{ > + int ret = 0; > + unsigned long val; > + struct tgu_drvdata *drvdata = dev_get_drvdata(dev->parent); > + > + ret = kstrtoul(buf, 0, &val); > + if (ret) > + return ret; > + > + if (val) { > + ret = pm_runtime_resume_and_get(dev->parent); > + if (ret) > + return ret; > + ret = tgu_enable(drvdata->csdev, CS_MODE_SYSFS, NULL); > + if (ret) > + pm_runtime_put(dev->parent); > + } else { > + ret = tgu_disable(drvdata->csdev, NULL); > + if (!ret) redundant - tgu_disable always returns 0. > + pm_runtime_put(dev->parent); > + } > + > + if (ret) > + return ret; > + return size; > +} > +static DEVICE_ATTR_RW(enable_tgu); > + > +static const struct coresight_ops_helper tgu_helper_ops = { > + .enable = tgu_enable, > + .disable = tgu_disable, > +}; > + > +static const struct coresight_ops tgu_ops = { > + .helper_ops = &tgu_helper_ops, > +}; > + > +static struct attribute *tgu_common_attrs[] = { > + &dev_attr_enable_tgu.attr, > + NULL, > +}; > + > +static const struct attribute_group tgu_common_grp = { > + .attrs = tgu_common_attrs, > + NULL, > +}; > + > +static const struct attribute_group *tgu_attr_groups[] = { > + &tgu_common_grp, > + NULL, > +}; > + > +static int tgu_probe(struct amba_device *adev, const struct amba_id *id) > +{ > + int ret = 0; > + struct device *dev = &adev->dev; > + struct coresight_desc desc = { 0 }; > + struct coresight_platform_data *pdata; > + struct tgu_drvdata *drvdata; > + > + desc.name = coresight_alloc_device_name(&tgu_devs, dev); > + if (!desc.name) > + return -ENOMEM; > + > + pdata = coresight_get_platform_data(dev); > + if (IS_ERR(pdata)) > + return PTR_ERR(pdata); > + > + adev->dev.platform_data = pdata; > + > + drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL); > + if (!drvdata) > + return -ENOMEM; > + > + drvdata->dev = &adev->dev; > + dev_set_drvdata(dev, drvdata); > + > + drvdata->base = devm_ioremap_resource(dev, &adev->res); > + if (!drvdata->base) > + return -ENOMEM; > + > + spin_lock_init(&drvdata->spinlock); > + > + drvdata->enable = false; > + desc.type = CORESIGHT_DEV_TYPE_HELPER; > + desc.pdata = adev->dev.platform_data; > + desc.dev = &adev->dev; > + desc.ops = &tgu_ops; > + desc.groups = tgu_attr_groups; > + > + drvdata->csdev = coresight_register(&desc); > + if (IS_ERR(drvdata->csdev)) { > + ret = PTR_ERR(drvdata->csdev); > + goto err; > + } > + > + pm_runtime_put(&adev->dev); > + return 0; > +err: > + pm_runtime_put(&adev->dev); > + return ret; > +} > + > +static void tgu_remove(struct amba_device *adev) > +{ > + struct tgu_drvdata *drvdata = dev_get_drvdata(&adev->dev); > + > + coresight_unregister(drvdata->csdev); > +} > + > +static const struct amba_id tgu_ids[] = { > + { > + .id = 0x000f0e00, > + .mask = 0x000fffff, > + .data = "TGU", > + }, > + { 0, 0, NULL }, > +}; > + > +MODULE_DEVICE_TABLE(amba, tgu_ids); > + > +static struct amba_driver tgu_driver = { > + .drv = { > + .name = "coresight-tgu", > + .suppress_bind_attrs = true, > + }, > + .probe = tgu_probe, > + .remove = tgu_remove, > + .id_table = tgu_ids, > +}; > + > +module_amba_driver(tgu_driver); > + > +MODULE_LICENSE("GPL"); > +MODULE_DESCRIPTION("CoreSight TGU driver"); > diff --git a/drivers/hwtracing/coresight/coresight-tgu.h b/drivers/hwtracing/coresight/coresight-tgu.h > new file mode 100644 > index 000000000000..380686f94130 > --- /dev/null > +++ b/drivers/hwtracing/coresight/coresight-tgu.h > @@ -0,0 +1,36 @@ > +/* SPDX-License-Identifier: GPL-2.0 */ > +/* > + * Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights reserved. > + */ > + > +#ifndef _CORESIGHT_TGU_H > +#define _CORESIGHT_TGU_H > + > +/* Register addresses */ > +#define TGU_CONTROL 0x0000 > + > +/* Register read/write */ > +#define tgu_writel(drvdata, val, off) __raw_writel((val), drvdata->base + off) > +#define tgu_readl(drvdata, off) __raw_readl(drvdata->base + off) > + > +/** > + * struct tgu_drvdata - Data structure for a TGU (Trigger Generator Unit) device > + * @base: Memory-mapped base address of the TGU device > + * @dev: Pointer to the associated device structure > + * @csdev: Pointer to the associated coresight device > + * @spinlock: Spinlock for handling concurrent access > + * @enable: Flag indicating whether the TGU device is enabled > + * > + * This structure defines the data associated with a TGU device, including its base > + * address, device pointers, clock, spinlock for synchronization, trigger data pointers, I don't see any trigger data pointers or limits here. Comment on what is there, if more is added later, expand the comment later. > + * maximum limits for various trigger-related parameters, and enable status. > + */ > +struct tgu_drvdata { > + void __iomem *base; > + struct device *dev; > + struct coresight_device *csdev; > + spinlock_t spinlock; > + bool enable; > +}; > + > +#endif > Regards Mike -- Mike Leach Principal Engineer, ARM Ltd. Manchester Design Centre. UK

4 months, 2 weeks

Re: [PATCH v6 2/9] coresight-etm4x: change etmv4_drvdata spinlock type to raw_spinlock_t

by Suzuki K Poulose

Hi Levi On 06/03/2025 12:11, Yeoreum Yun wrote: > In coresight-etm4x drivers, etmv4_drvdata->spinlock can be held during > __schedule() by perf_event_task_sched_out()/in(). > > Since etmv4_drvdata->spinlock type is spinlock_t and > perf_event_task_sched_out()/in() is called after acquiring rq_lock, > which is raw_spinlock_t (an unsleepable lock), > this poses an issue in PREEMPT_RT kernel where spinlock_t is sleepable. > > To address this, change type etmv4_drvdata->spinlock > in coresight-etm4x drivers, which can be called > by perf_event_task_sched_out()/in(), from spinlock_t to raw_spinlock_t. > > Signed-off-by: Yeoreum Yun <yeoreum.yun(a)arm.com> > Reviewed-by: James Clark <james.clark(a)linaro.org> > --- > .../hwtracing/coresight/coresight-config.c | 8 +- > .../hwtracing/coresight/coresight-config.h | 2 +- > .../coresight/coresight-etm4x-core.c | 18 +- > .../coresight/coresight-etm4x-sysfs.c | 250 +++++++++--------- > drivers/hwtracing/coresight/coresight-etm4x.h | 2 +- > 5 files changed, 140 insertions(+), 140 deletions(-) > > diff --git a/drivers/hwtracing/coresight/coresight-config.c b/drivers/hwtracing/coresight/coresight-config.c > index 4723bf7402a2..4f72ae71b696 100644 > --- a/drivers/hwtracing/coresight/coresight-config.c > +++ b/drivers/hwtracing/coresight/coresight-config.c > @@ -76,10 +76,10 @@ static int cscfg_set_on_enable(struct cscfg_feature_csdev *feat_csdev) > unsigned long flags; > int i; > > - spin_lock_irqsave(feat_csdev->drv_spinlock, flags); > + raw_spin_lock_irqsave(feat_csdev->drv_spinlock, flags); > for (i = 0; i < feat_csdev->nr_regs; i++) > cscfg_set_reg(&feat_csdev->regs_csdev[i]); > - spin_unlock_irqrestore(feat_csdev->drv_spinlock, flags); > + raw_spin_unlock_irqrestore(feat_csdev->drv_spinlock, flags); > dev_dbg(&feat_csdev->csdev->dev, "Feature %s: %s", > feat_csdev->feat_desc->name, "set on enable"); > return 0; > @@ -91,10 +91,10 @@ static void cscfg_save_on_disable(struct cscfg_feature_csdev *feat_csdev) > unsigned long flags; > int i; > > - spin_lock_irqsave(feat_csdev->drv_spinlock, flags); > + raw_spin_lock_irqsave(feat_csdev->drv_spinlock, flags); > for (i = 0; i < feat_csdev->nr_regs; i++) > cscfg_save_reg(&feat_csdev->regs_csdev[i]); > - spin_unlock_irqrestore(feat_csdev->drv_spinlock, flags); > + raw_spin_unlock_irqrestore(feat_csdev->drv_spinlock, flags); > dev_dbg(&feat_csdev->csdev->dev, "Feature %s: %s", > feat_csdev->feat_desc->name, "save on disable"); > } > diff --git a/drivers/hwtracing/coresight/coresight-config.h b/drivers/hwtracing/coresight/coresight-config.h > index 6ba013975741..b9ebc9fcfb7f 100644 > --- a/drivers/hwtracing/coresight/coresight-config.h > +++ b/drivers/hwtracing/coresight/coresight-config.h > @@ -206,7 +206,7 @@ struct cscfg_feature_csdev { > const struct cscfg_feature_desc *feat_desc; > struct coresight_device *csdev; > struct list_head node; > - spinlock_t *drv_spinlock; > + raw_spinlock_t *drv_spinlock; > int nr_params; > struct cscfg_parameter_csdev *params_csdev; > int nr_regs; The changes above seems to be unrelated etm4x and not called for in the patch description. Is there any reason why this cannot be separated from etm4x changes ? Suzuki > diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c > index bb1e80df2914..e5972f16abff 100644 > --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c > +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c > @@ -830,7 +830,7 @@ static int etm4_enable_sysfs(struct coresight_device *csdev, struct coresight_pa > return ret; > } > > - spin_lock(&drvdata->spinlock); > + raw_spin_lock(&drvdata->spinlock); > > drvdata->trcid = path->trace_id; > > @@ -849,7 +849,7 @@ static int etm4_enable_sysfs(struct coresight_device *csdev, struct coresight_pa > if (ret) > etm4_release_trace_id(drvdata); > > - spin_unlock(&drvdata->spinlock); > + raw_spin_unlock(&drvdata->spinlock); > > if (!ret) > dev_dbg(&csdev->dev, "ETM tracing enabled\n"); > @@ -1011,7 +1011,7 @@ static void etm4_disable_sysfs(struct coresight_device *csdev) > * DYING hotplug callback is serviced by the ETM driver. > */ > cpus_read_lock(); > - spin_lock(&drvdata->spinlock); > + raw_spin_lock(&drvdata->spinlock); > > /* > * Executing etm4_disable_hw on the cpu whose ETM is being disabled > @@ -1019,7 +1019,7 @@ static void etm4_disable_sysfs(struct coresight_device *csdev) > */ > smp_call_function_single(drvdata->cpu, etm4_disable_hw, drvdata, 1); > > - spin_unlock(&drvdata->spinlock); > + raw_spin_unlock(&drvdata->spinlock); > cpus_read_unlock(); > > /* > @@ -1698,13 +1698,13 @@ static int etm4_starting_cpu(unsigned int cpu) > if (!etmdrvdata[cpu]) > return 0; > > - spin_lock(&etmdrvdata[cpu]->spinlock); > + raw_spin_lock(&etmdrvdata[cpu]->spinlock); > if (!etmdrvdata[cpu]->os_unlock) > etm4_os_unlock(etmdrvdata[cpu]); > > if (coresight_get_mode(etmdrvdata[cpu]->csdev)) > etm4_enable_hw(etmdrvdata[cpu]); > - spin_unlock(&etmdrvdata[cpu]->spinlock); > + raw_spin_unlock(&etmdrvdata[cpu]->spinlock); > return 0; > } > > @@ -1713,10 +1713,10 @@ static int etm4_dying_cpu(unsigned int cpu) > if (!etmdrvdata[cpu]) > return 0; > > - spin_lock(&etmdrvdata[cpu]->spinlock); > + raw_spin_lock(&etmdrvdata[cpu]->spinlock); > if (coresight_get_mode(etmdrvdata[cpu]->csdev)) > etm4_disable_hw(etmdrvdata[cpu]); > - spin_unlock(&etmdrvdata[cpu]->spinlock); > + raw_spin_unlock(&etmdrvdata[cpu]->spinlock); > return 0; > } > > @@ -2160,7 +2160,7 @@ static int etm4_probe(struct device *dev) > return -ENOMEM; > } > > - spin_lock_init(&drvdata->spinlock); > + raw_spin_lock_init(&drvdata->spinlock); > > drvdata->cpu = coresight_get_cpu(dev); > if (drvdata->cpu < 0) > diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c > index e5216c0f60da..fdd0956fecb3 100644 > --- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c > +++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c > @@ -175,7 +175,7 @@ static ssize_t reset_store(struct device *dev, > if (kstrtoul(buf, 16, &val)) > return -EINVAL; > > - spin_lock(&drvdata->spinlock); > + raw_spin_lock(&drvdata->spinlock); > if (val) > config->mode = 0x0; > > @@ -267,7 +267,7 @@ static ssize_t reset_store(struct device *dev, > config->vmid_mask0 = 0x0; > config->vmid_mask1 = 0x0; > > - spin_unlock(&drvdata->spinlock); > + raw_spin_unlock(&drvdata->spinlock); > > /* for sysfs - only release trace id when resetting */ > etm4_release_trace_id(drvdata); > @@ -301,7 +301,7 @@ static ssize_t mode_store(struct device *dev, > if (kstrtoul(buf, 16, &val)) > return -EINVAL; > > - spin_lock(&drvdata->spinlock); > + raw_spin_lock(&drvdata->spinlock); > config->mode = val & ETMv4_MODE_ALL; > > if (drvdata->instrp0 == true) { > @@ -438,7 +438,7 @@ static ssize_t mode_store(struct device *dev, > if (config->mode & (ETM_MODE_EXCL_KERN | ETM_MODE_EXCL_USER)) > etm4_config_trace_mode(config); > > - spin_unlock(&drvdata->spinlock); > + raw_spin_unlock(&drvdata->spinlock); > > return size; > } > @@ -467,14 +467,14 @@ static ssize_t pe_store(struct device *dev, > if (kstrtoul(buf, 16, &val)) > return -EINVAL; > > - spin_lock(&drvdata->spinlock); > + raw_spin_lock(&drvdata->spinlock); > if (val > drvdata->nr_pe) { > - spin_unlock(&drvdata->spinlock); > + raw_spin_unlock(&drvdata->spinlock); > return -EINVAL; > } > > config->pe_sel = val; > - spin_unlock(&drvdata->spinlock); > + raw_spin_unlock(&drvdata->spinlock); > return size; > } > static DEVICE_ATTR_RW(pe); > @@ -502,7 +502,7 @@ static ssize_t event_store(struct device *dev, > if (kstrtoul(buf, 16, &val)) > return -EINVAL; > > - spin_lock(&drvdata->spinlock); > + raw_spin_lock(&drvdata->spinlock); > switch (drvdata->nr_event) { > case 0x0: > /* EVENT0, bits[7:0] */ > @@ -523,7 +523,7 @@ static ssize_t event_store(struct device *dev, > default: > break; > } > - spin_unlock(&drvdata->spinlock); > + raw_spin_unlock(&drvdata->spinlock); > return size; > } > static DEVICE_ATTR_RW(event); > @@ -551,7 +551,7 @@ static ssize_t event_instren_store(struct device *dev, > if (kstrtoul(buf, 16, &val)) > return -EINVAL; > > - spin_lock(&drvdata->spinlock); > + raw_spin_lock(&drvdata->spinlock); > /* start by clearing all instruction event enable bits */ > config->eventctrl1 &= ~TRCEVENTCTL1R_INSTEN_MASK; > switch (drvdata->nr_event) { > @@ -579,7 +579,7 @@ static ssize_t event_instren_store(struct device *dev, > default: > break; > } > - spin_unlock(&drvdata->spinlock); > + raw_spin_unlock(&drvdata->spinlock); > return size; > } > static DEVICE_ATTR_RW(event_instren); > @@ -740,11 +740,11 @@ static ssize_t event_vinst_store(struct device *dev, > if (kstrtoul(buf, 16, &val)) > return -EINVAL; > > - spin_lock(&drvdata->spinlock); > + raw_spin_lock(&drvdata->spinlock); > val &= TRCVICTLR_EVENT_MASK >> __bf_shf(TRCVICTLR_EVENT_MASK); > config->vinst_ctrl &= ~TRCVICTLR_EVENT_MASK; > config->vinst_ctrl |= FIELD_PREP(TRCVICTLR_EVENT_MASK, val); > - spin_unlock(&drvdata->spinlock); > + raw_spin_unlock(&drvdata->spinlock); > return size; > } > static DEVICE_ATTR_RW(event_vinst); > @@ -772,13 +772,13 @@ static ssize_t s_exlevel_vinst_store(struct device *dev, > if (kstrtoul(buf, 16, &val)) > return -EINVAL; > > - spin_lock(&drvdata->spinlock); > + raw_spin_lock(&drvdata->spinlock); > /* clear all EXLEVEL_S bits */ > config->vinst_ctrl &= ~TRCVICTLR_EXLEVEL_S_MASK; > /* enable instruction tracing for corresponding exception level */ > val &= drvdata->s_ex_level; > config->vinst_ctrl |= val << __bf_shf(TRCVICTLR_EXLEVEL_S_MASK); > - spin_unlock(&drvdata->spinlock); > + raw_spin_unlock(&drvdata->spinlock); > return size; > } > static DEVICE_ATTR_RW(s_exlevel_vinst); > @@ -807,13 +807,13 @@ static ssize_t ns_exlevel_vinst_store(struct device *dev, > if (kstrtoul(buf, 16, &val)) > return -EINVAL; > > - spin_lock(&drvdata->spinlock); > + raw_spin_lock(&drvdata->spinlock); > /* clear EXLEVEL_NS bits */ > config->vinst_ctrl &= ~TRCVICTLR_EXLEVEL_NS_MASK; > /* enable instruction tracing for corresponding exception level */ > val &= drvdata->ns_ex_level; > config->vinst_ctrl |= val << __bf_shf(TRCVICTLR_EXLEVEL_NS_MASK); > - spin_unlock(&drvdata->spinlock); > + raw_spin_unlock(&drvdata->spinlock); > return size; > } > static DEVICE_ATTR_RW(ns_exlevel_vinst); > @@ -847,9 +847,9 @@ static ssize_t addr_idx_store(struct device *dev, > * Use spinlock to ensure index doesn't change while it gets > * dereferenced multiple times within a spinlock block elsewhere. > */ > - spin_lock(&drvdata->spinlock); > + raw_spin_lock(&drvdata->spinlock); > config->addr_idx = val; > - spin_unlock(&drvdata->spinlock); > + raw_spin_unlock(&drvdata->spinlock); > return size; > } > static DEVICE_ATTR_RW(addr_idx); > @@ -863,7 +863,7 @@ static ssize_t addr_instdatatype_show(struct device *dev, > struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); > struct etmv4_config *config = &drvdata->config; > > - spin_lock(&drvdata->spinlock); > + raw_spin_lock(&drvdata->spinlock); > idx = config->addr_idx; > val = FIELD_GET(TRCACATRn_TYPE_MASK, config->addr_acc[idx]); > len = scnprintf(buf, PAGE_SIZE, "%s\n", > @@ -871,7 +871,7 @@ static ssize_t addr_instdatatype_show(struct device *dev, > (val == TRCACATRn_TYPE_DATA_LOAD_ADDR ? "data_load" : > (val == TRCACATRn_TYPE_DATA_STORE_ADDR ? "data_store" : > "data_load_store"))); > - spin_unlock(&drvdata->spinlock); > + raw_spin_unlock(&drvdata->spinlock); > return len; > } > > @@ -889,13 +889,13 @@ static ssize_t addr_instdatatype_store(struct device *dev, > if (sscanf(buf, "%s", str) != 1) > return -EINVAL; > > - spin_lock(&drvdata->spinlock); > + raw_spin_lock(&drvdata->spinlock); > idx = config->addr_idx; > if (!strcmp(str, "instr")) > /* TYPE, bits[1:0] */ > config->addr_acc[idx] &= ~TRCACATRn_TYPE_MASK; > > - spin_unlock(&drvdata->spinlock); > + raw_spin_unlock(&drvdata->spinlock); > return size; > } > static DEVICE_ATTR_RW(addr_instdatatype); > @@ -910,14 +910,14 @@ static ssize_t addr_single_show(struct device *dev, > struct etmv4_config *config = &drvdata->config; > > idx = config->addr_idx; > - spin_lock(&drvdata->spinlock); > + raw_spin_lock(&drvdata->spinlock); > if (!(config->addr_type[idx] == ETM_ADDR_TYPE_NONE || > config->addr_type[idx] == ETM_ADDR_TYPE_SINGLE)) { > - spin_unlock(&drvdata->spinlock); > + raw_spin_unlock(&drvdata->spinlock); > return -EPERM; > } > val = (unsigned long)config->addr_val[idx]; > - spin_unlock(&drvdata->spinlock); > + raw_spin_unlock(&drvdata->spinlock); > return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); > } > > @@ -933,17 +933,17 @@ static ssize_t addr_single_store(struct device *dev, > if (kstrtoul(buf, 16, &val)) > return -EINVAL; > > - spin_lock(&drvdata->spinlock); > + raw_spin_lock(&drvdata->spinlock); > idx = config->addr_idx; > if (!(config->addr_type[idx] == ETM_ADDR_TYPE_NONE || > config->addr_type[idx] == ETM_ADDR_TYPE_SINGLE)) { > - spin_unlock(&drvdata->spinlock); > + raw_spin_unlock(&drvdata->spinlock); > return -EPERM; > } > > config->addr_val[idx] = (u64)val; > config->addr_type[idx] = ETM_ADDR_TYPE_SINGLE; > - spin_unlock(&drvdata->spinlock); > + raw_spin_unlock(&drvdata->spinlock); > return size; > } > static DEVICE_ATTR_RW(addr_single); > @@ -957,23 +957,23 @@ static ssize_t addr_range_show(struct device *dev, > struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); > struct etmv4_config *config = &drvdata->config; > > - spin_lock(&drvdata->spinlock); > + raw_spin_lock(&drvdata->spinlock); > idx = config->addr_idx; > if (idx % 2 != 0) { > - spin_unlock(&drvdata->spinlock); > + raw_spin_unlock(&drvdata->spinlock); > return -EPERM; > } > if (!((config->addr_type[idx] == ETM_ADDR_TYPE_NONE && > config->addr_type[idx + 1] == ETM_ADDR_TYPE_NONE) || > (config->addr_type[idx] == ETM_ADDR_TYPE_RANGE && > config->addr_type[idx + 1] == ETM_ADDR_TYPE_RANGE))) { > - spin_unlock(&drvdata->spinlock); > + raw_spin_unlock(&drvdata->spinlock); > return -EPERM; > } > > val1 = (unsigned long)config->addr_val[idx]; > val2 = (unsigned long)config->addr_val[idx + 1]; > - spin_unlock(&drvdata->spinlock); > + raw_spin_unlock(&drvdata->spinlock); > return scnprintf(buf, PAGE_SIZE, "%#lx %#lx\n", val1, val2); > } > > @@ -996,10 +996,10 @@ static ssize_t addr_range_store(struct device *dev, > if (val1 > val2) > return -EINVAL; > > - spin_lock(&drvdata->spinlock); > + raw_spin_lock(&drvdata->spinlock); > idx = config->addr_idx; > if (idx % 2 != 0) { > - spin_unlock(&drvdata->spinlock); > + raw_spin_unlock(&drvdata->spinlock); > return -EPERM; > } > > @@ -1007,7 +1007,7 @@ static ssize_t addr_range_store(struct device *dev, > config->addr_type[idx + 1] == ETM_ADDR_TYPE_NONE) || > (config->addr_type[idx] == ETM_ADDR_TYPE_RANGE && > config->addr_type[idx + 1] == ETM_ADDR_TYPE_RANGE))) { > - spin_unlock(&drvdata->spinlock); > + raw_spin_unlock(&drvdata->spinlock); > return -EPERM; > } > > @@ -1024,7 +1024,7 @@ static ssize_t addr_range_store(struct device *dev, > exclude = config->mode & ETM_MODE_EXCLUDE; > etm4_set_mode_exclude(drvdata, exclude ? true : false); > > - spin_unlock(&drvdata->spinlock); > + raw_spin_unlock(&drvdata->spinlock); > return size; > } > static DEVICE_ATTR_RW(addr_range); > @@ -1038,17 +1038,17 @@ static ssize_t addr_start_show(struct device *dev, > struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); > struct etmv4_config *config = &drvdata->config; > > - spin_lock(&drvdata->spinlock); > + raw_spin_lock(&drvdata->spinlock); > idx = config->addr_idx; > > if (!(config->addr_type[idx] == ETM_ADDR_TYPE_NONE || > config->addr_type[idx] == ETM_ADDR_TYPE_START)) { > - spin_unlock(&drvdata->spinlock); > + raw_spin_unlock(&drvdata->spinlock); > return -EPERM; > } > > val = (unsigned long)config->addr_val[idx]; > - spin_unlock(&drvdata->spinlock); > + raw_spin_unlock(&drvdata->spinlock); > return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); > } > > @@ -1064,22 +1064,22 @@ static ssize_t addr_start_store(struct device *dev, > if (kstrtoul(buf, 16, &val)) > return -EINVAL; > > - spin_lock(&drvdata->spinlock); > + raw_spin_lock(&drvdata->spinlock); > idx = config->addr_idx; > if (!drvdata->nr_addr_cmp) { > - spin_unlock(&drvdata->spinlock); > + raw_spin_unlock(&drvdata->spinlock); > return -EINVAL; > } > if (!(config->addr_type[idx] == ETM_ADDR_TYPE_NONE || > config->addr_type[idx] == ETM_ADDR_TYPE_START)) { > - spin_unlock(&drvdata->spinlock); > + raw_spin_unlock(&drvdata->spinlock); > return -EPERM; > } > > config->addr_val[idx] = (u64)val; > config->addr_type[idx] = ETM_ADDR_TYPE_START; > config->vissctlr |= BIT(idx); > - spin_unlock(&drvdata->spinlock); > + raw_spin_unlock(&drvdata->spinlock); > return size; > } > static DEVICE_ATTR_RW(addr_start); > @@ -1093,17 +1093,17 @@ static ssize_t addr_stop_show(struct device *dev, > struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); > struct etmv4_config *config = &drvdata->config; > > - spin_lock(&drvdata->spinlock); > + raw_spin_lock(&drvdata->spinlock); > idx = config->addr_idx; > > if (!(config->addr_type[idx] == ETM_ADDR_TYPE_NONE || > config->addr_type[idx] == ETM_ADDR_TYPE_STOP)) { > - spin_unlock(&drvdata->spinlock); > + raw_spin_unlock(&drvdata->spinlock); > return -EPERM; > } > > val = (unsigned long)config->addr_val[idx]; > - spin_unlock(&drvdata->spinlock); > + raw_spin_unlock(&drvdata->spinlock); > return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); > } > > @@ -1119,22 +1119,22 @@ static ssize_t addr_stop_store(struct device *dev, > if (kstrtoul(buf, 16, &val)) > return -EINVAL; > > - spin_lock(&drvdata->spinlock); > + raw_spin_lock(&drvdata->spinlock); > idx = config->addr_idx; > if (!drvdata->nr_addr_cmp) { > - spin_unlock(&drvdata->spinlock); > + raw_spin_unlock(&drvdata->spinlock); > return -EINVAL; > } > if (!(config->addr_type[idx] == ETM_ADDR_TYPE_NONE || > config->addr_type[idx] == ETM_ADDR_TYPE_STOP)) { > - spin_unlock(&drvdata->spinlock); > + raw_spin_unlock(&drvdata->spinlock); > return -EPERM; > } > > config->addr_val[idx] = (u64)val; > config->addr_type[idx] = ETM_ADDR_TYPE_STOP; > config->vissctlr |= BIT(idx + 16); > - spin_unlock(&drvdata->spinlock); > + raw_spin_unlock(&drvdata->spinlock); > return size; > } > static DEVICE_ATTR_RW(addr_stop); > @@ -1148,14 +1148,14 @@ static ssize_t addr_ctxtype_show(struct device *dev, > struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); > struct etmv4_config *config = &drvdata->config; > > - spin_lock(&drvdata->spinlock); > + raw_spin_lock(&drvdata->spinlock); > idx = config->addr_idx; > /* CONTEXTTYPE, bits[3:2] */ > val = FIELD_GET(TRCACATRn_CONTEXTTYPE_MASK, config->addr_acc[idx]); > len = scnprintf(buf, PAGE_SIZE, "%s\n", val == ETM_CTX_NONE ? "none" : > (val == ETM_CTX_CTXID ? "ctxid" : > (val == ETM_CTX_VMID ? "vmid" : "all"))); > - spin_unlock(&drvdata->spinlock); > + raw_spin_unlock(&drvdata->spinlock); > return len; > } > > @@ -1173,7 +1173,7 @@ static ssize_t addr_ctxtype_store(struct device *dev, > if (sscanf(buf, "%s", str) != 1) > return -EINVAL; > > - spin_lock(&drvdata->spinlock); > + raw_spin_lock(&drvdata->spinlock); > idx = config->addr_idx; > if (!strcmp(str, "none")) > /* start by clearing context type bits */ > @@ -1200,7 +1200,7 @@ static ssize_t addr_ctxtype_store(struct device *dev, > if (drvdata->numvmidc) > config->addr_acc[idx] |= TRCACATRn_CONTEXTTYPE_VMID; > } > - spin_unlock(&drvdata->spinlock); > + raw_spin_unlock(&drvdata->spinlock); > return size; > } > static DEVICE_ATTR_RW(addr_ctxtype); > @@ -1214,11 +1214,11 @@ static ssize_t addr_context_show(struct device *dev, > struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); > struct etmv4_config *config = &drvdata->config; > > - spin_lock(&drvdata->spinlock); > + raw_spin_lock(&drvdata->spinlock); > idx = config->addr_idx; > /* context ID comparator bits[6:4] */ > val = FIELD_GET(TRCACATRn_CONTEXT_MASK, config->addr_acc[idx]); > - spin_unlock(&drvdata->spinlock); > + raw_spin_unlock(&drvdata->spinlock); > return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); > } > > @@ -1239,12 +1239,12 @@ static ssize_t addr_context_store(struct device *dev, > drvdata->numcidc : drvdata->numvmidc)) > return -EINVAL; > > - spin_lock(&drvdata->spinlock); > + raw_spin_lock(&drvdata->spinlock); > idx = config->addr_idx; > /* clear context ID comparator bits[6:4] */ > config->addr_acc[idx] &= ~TRCACATRn_CONTEXT_MASK; > config->addr_acc[idx] |= val << __bf_shf(TRCACATRn_CONTEXT_MASK); > - spin_unlock(&drvdata->spinlock); > + raw_spin_unlock(&drvdata->spinlock); > return size; > } > static DEVICE_ATTR_RW(addr_context); > @@ -1258,10 +1258,10 @@ static ssize_t addr_exlevel_s_ns_show(struct device *dev, > struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); > struct etmv4_config *config = &drvdata->config; > > - spin_lock(&drvdata->spinlock); > + raw_spin_lock(&drvdata->spinlock); > idx = config->addr_idx; > val = FIELD_GET(TRCACATRn_EXLEVEL_MASK, config->addr_acc[idx]); > - spin_unlock(&drvdata->spinlock); > + raw_spin_unlock(&drvdata->spinlock); > return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); > } > > @@ -1280,12 +1280,12 @@ static ssize_t addr_exlevel_s_ns_store(struct device *dev, > if (val & ~(TRCACATRn_EXLEVEL_MASK >> __bf_shf(TRCACATRn_EXLEVEL_MASK))) > return -EINVAL; > > - spin_lock(&drvdata->spinlock); > + raw_spin_lock(&drvdata->spinlock); > idx = config->addr_idx; > /* clear Exlevel_ns & Exlevel_s bits[14:12, 11:8], bit[15] is res0 */ > config->addr_acc[idx] &= ~TRCACATRn_EXLEVEL_MASK; > config->addr_acc[idx] |= val << __bf_shf(TRCACATRn_EXLEVEL_MASK); > - spin_unlock(&drvdata->spinlock); > + raw_spin_unlock(&drvdata->spinlock); > return size; > } > static DEVICE_ATTR_RW(addr_exlevel_s_ns); > @@ -1308,7 +1308,7 @@ static ssize_t addr_cmp_view_show(struct device *dev, > int size = 0; > bool exclude = false; > > - spin_lock(&drvdata->spinlock); > + raw_spin_lock(&drvdata->spinlock); > idx = config->addr_idx; > addr_v = config->addr_val[idx]; > addr_ctrl = config->addr_acc[idx]; > @@ -1323,7 +1323,7 @@ static ssize_t addr_cmp_view_show(struct device *dev, > } > exclude = config->viiectlr & BIT(idx / 2 + 16); > } > - spin_unlock(&drvdata->spinlock); > + raw_spin_unlock(&drvdata->spinlock); > if (addr_type) { > size = scnprintf(buf, PAGE_SIZE, "addr_cmp[%i] %s %#lx", idx, > addr_type_names[addr_type], addr_v); > @@ -1367,9 +1367,9 @@ static ssize_t vinst_pe_cmp_start_stop_store(struct device *dev, > if (!drvdata->nr_pe_cmp) > return -EINVAL; > > - spin_lock(&drvdata->spinlock); > + raw_spin_lock(&drvdata->spinlock); > config->vipcssctlr = val; > - spin_unlock(&drvdata->spinlock); > + raw_spin_unlock(&drvdata->spinlock); > return size; > } > static DEVICE_ATTR_RW(vinst_pe_cmp_start_stop); > @@ -1403,9 +1403,9 @@ static ssize_t seq_idx_store(struct device *dev, > * Use spinlock to ensure index doesn't change while it gets > * dereferenced multiple times within a spinlock block elsewhere. > */ > - spin_lock(&drvdata->spinlock); > + raw_spin_lock(&drvdata->spinlock); > config->seq_idx = val; > - spin_unlock(&drvdata->spinlock); > + raw_spin_unlock(&drvdata->spinlock); > return size; > } > static DEVICE_ATTR_RW(seq_idx); > @@ -1449,10 +1449,10 @@ static ssize_t seq_event_show(struct device *dev, > struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); > struct etmv4_config *config = &drvdata->config; > > - spin_lock(&drvdata->spinlock); > + raw_spin_lock(&drvdata->spinlock); > idx = config->seq_idx; > val = config->seq_ctrl[idx]; > - spin_unlock(&drvdata->spinlock); > + raw_spin_unlock(&drvdata->spinlock); > return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); > } > > @@ -1468,11 +1468,11 @@ static ssize_t seq_event_store(struct device *dev, > if (kstrtoul(buf, 16, &val)) > return -EINVAL; > > - spin_lock(&drvdata->spinlock); > + raw_spin_lock(&drvdata->spinlock); > idx = config->seq_idx; > /* Seq control has two masks B[15:8] F[7:0] */ > config->seq_ctrl[idx] = val & 0xFFFF; > - spin_unlock(&drvdata->spinlock); > + raw_spin_unlock(&drvdata->spinlock); > return size; > } > static DEVICE_ATTR_RW(seq_event); > @@ -1536,9 +1536,9 @@ static ssize_t cntr_idx_store(struct device *dev, > * Use spinlock to ensure index doesn't change while it gets > * dereferenced multiple times within a spinlock block elsewhere. > */ > - spin_lock(&drvdata->spinlock); > + raw_spin_lock(&drvdata->spinlock); > config->cntr_idx = val; > - spin_unlock(&drvdata->spinlock); > + raw_spin_unlock(&drvdata->spinlock); > return size; > } > static DEVICE_ATTR_RW(cntr_idx); > @@ -1552,10 +1552,10 @@ static ssize_t cntrldvr_show(struct device *dev, > struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); > struct etmv4_config *config = &drvdata->config; > > - spin_lock(&drvdata->spinlock); > + raw_spin_lock(&drvdata->spinlock); > idx = config->cntr_idx; > val = config->cntrldvr[idx]; > - spin_unlock(&drvdata->spinlock); > + raw_spin_unlock(&drvdata->spinlock); > return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); > } > > @@ -1573,10 +1573,10 @@ static ssize_t cntrldvr_store(struct device *dev, > if (val > ETM_CNTR_MAX_VAL) > return -EINVAL; > > - spin_lock(&drvdata->spinlock); > + raw_spin_lock(&drvdata->spinlock); > idx = config->cntr_idx; > config->cntrldvr[idx] = val; > - spin_unlock(&drvdata->spinlock); > + raw_spin_unlock(&drvdata->spinlock); > return size; > } > static DEVICE_ATTR_RW(cntrldvr); > @@ -1590,10 +1590,10 @@ static ssize_t cntr_val_show(struct device *dev, > struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); > struct etmv4_config *config = &drvdata->config; > > - spin_lock(&drvdata->spinlock); > + raw_spin_lock(&drvdata->spinlock); > idx = config->cntr_idx; > val = config->cntr_val[idx]; > - spin_unlock(&drvdata->spinlock); > + raw_spin_unlock(&drvdata->spinlock); > return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); > } > > @@ -1611,10 +1611,10 @@ static ssize_t cntr_val_store(struct device *dev, > if (val > ETM_CNTR_MAX_VAL) > return -EINVAL; > > - spin_lock(&drvdata->spinlock); > + raw_spin_lock(&drvdata->spinlock); > idx = config->cntr_idx; > config->cntr_val[idx] = val; > - spin_unlock(&drvdata->spinlock); > + raw_spin_unlock(&drvdata->spinlock); > return size; > } > static DEVICE_ATTR_RW(cntr_val); > @@ -1628,10 +1628,10 @@ static ssize_t cntr_ctrl_show(struct device *dev, > struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); > struct etmv4_config *config = &drvdata->config; > > - spin_lock(&drvdata->spinlock); > + raw_spin_lock(&drvdata->spinlock); > idx = config->cntr_idx; > val = config->cntr_ctrl[idx]; > - spin_unlock(&drvdata->spinlock); > + raw_spin_unlock(&drvdata->spinlock); > return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); > } > > @@ -1647,10 +1647,10 @@ static ssize_t cntr_ctrl_store(struct device *dev, > if (kstrtoul(buf, 16, &val)) > return -EINVAL; > > - spin_lock(&drvdata->spinlock); > + raw_spin_lock(&drvdata->spinlock); > idx = config->cntr_idx; > config->cntr_ctrl[idx] = val; > - spin_unlock(&drvdata->spinlock); > + raw_spin_unlock(&drvdata->spinlock); > return size; > } > static DEVICE_ATTR_RW(cntr_ctrl); > @@ -1688,9 +1688,9 @@ static ssize_t res_idx_store(struct device *dev, > * Use spinlock to ensure index doesn't change while it gets > * dereferenced multiple times within a spinlock block elsewhere. > */ > - spin_lock(&drvdata->spinlock); > + raw_spin_lock(&drvdata->spinlock); > config->res_idx = val; > - spin_unlock(&drvdata->spinlock); > + raw_spin_unlock(&drvdata->spinlock); > return size; > } > static DEVICE_ATTR_RW(res_idx); > @@ -1704,10 +1704,10 @@ static ssize_t res_ctrl_show(struct device *dev, > struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); > struct etmv4_config *config = &drvdata->config; > > - spin_lock(&drvdata->spinlock); > + raw_spin_lock(&drvdata->spinlock); > idx = config->res_idx; > val = config->res_ctrl[idx]; > - spin_unlock(&drvdata->spinlock); > + raw_spin_unlock(&drvdata->spinlock); > return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); > } > > @@ -1723,7 +1723,7 @@ static ssize_t res_ctrl_store(struct device *dev, > if (kstrtoul(buf, 16, &val)) > return -EINVAL; > > - spin_lock(&drvdata->spinlock); > + raw_spin_lock(&drvdata->spinlock); > idx = config->res_idx; > /* For odd idx pair inversal bit is RES0 */ > if (idx % 2 != 0) > @@ -1733,7 +1733,7 @@ static ssize_t res_ctrl_store(struct device *dev, > TRCRSCTLRn_INV | > TRCRSCTLRn_GROUP_MASK | > TRCRSCTLRn_SELECT_MASK); > - spin_unlock(&drvdata->spinlock); > + raw_spin_unlock(&drvdata->spinlock); > return size; > } > static DEVICE_ATTR_RW(res_ctrl); > @@ -1762,9 +1762,9 @@ static ssize_t sshot_idx_store(struct device *dev, > if (val >= drvdata->nr_ss_cmp) > return -EINVAL; > > - spin_lock(&drvdata->spinlock); > + raw_spin_lock(&drvdata->spinlock); > config->ss_idx = val; > - spin_unlock(&drvdata->spinlock); > + raw_spin_unlock(&drvdata->spinlock); > return size; > } > static DEVICE_ATTR_RW(sshot_idx); > @@ -1777,9 +1777,9 @@ static ssize_t sshot_ctrl_show(struct device *dev, > struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); > struct etmv4_config *config = &drvdata->config; > > - spin_lock(&drvdata->spinlock); > + raw_spin_lock(&drvdata->spinlock); > val = config->ss_ctrl[config->ss_idx]; > - spin_unlock(&drvdata->spinlock); > + raw_spin_unlock(&drvdata->spinlock); > return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); > } > > @@ -1795,12 +1795,12 @@ static ssize_t sshot_ctrl_store(struct device *dev, > if (kstrtoul(buf, 16, &val)) > return -EINVAL; > > - spin_lock(&drvdata->spinlock); > + raw_spin_lock(&drvdata->spinlock); > idx = config->ss_idx; > config->ss_ctrl[idx] = FIELD_PREP(TRCSSCCRn_SAC_ARC_RST_MASK, val); > /* must clear bit 31 in related status register on programming */ > config->ss_status[idx] &= ~TRCSSCSRn_STATUS; > - spin_unlock(&drvdata->spinlock); > + raw_spin_unlock(&drvdata->spinlock); > return size; > } > static DEVICE_ATTR_RW(sshot_ctrl); > @@ -1812,9 +1812,9 @@ static ssize_t sshot_status_show(struct device *dev, > struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); > struct etmv4_config *config = &drvdata->config; > > - spin_lock(&drvdata->spinlock); > + raw_spin_lock(&drvdata->spinlock); > val = config->ss_status[config->ss_idx]; > - spin_unlock(&drvdata->spinlock); > + raw_spin_unlock(&drvdata->spinlock); > return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); > } > static DEVICE_ATTR_RO(sshot_status); > @@ -1827,9 +1827,9 @@ static ssize_t sshot_pe_ctrl_show(struct device *dev, > struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); > struct etmv4_config *config = &drvdata->config; > > - spin_lock(&drvdata->spinlock); > + raw_spin_lock(&drvdata->spinlock); > val = config->ss_pe_cmp[config->ss_idx]; > - spin_unlock(&drvdata->spinlock); > + raw_spin_unlock(&drvdata->spinlock); > return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); > } > > @@ -1845,12 +1845,12 @@ static ssize_t sshot_pe_ctrl_store(struct device *dev, > if (kstrtoul(buf, 16, &val)) > return -EINVAL; > > - spin_lock(&drvdata->spinlock); > + raw_spin_lock(&drvdata->spinlock); > idx = config->ss_idx; > config->ss_pe_cmp[idx] = FIELD_PREP(TRCSSPCICRn_PC_MASK, val); > /* must clear bit 31 in related status register on programming */ > config->ss_status[idx] &= ~TRCSSCSRn_STATUS; > - spin_unlock(&drvdata->spinlock); > + raw_spin_unlock(&drvdata->spinlock); > return size; > } > static DEVICE_ATTR_RW(sshot_pe_ctrl); > @@ -1884,9 +1884,9 @@ static ssize_t ctxid_idx_store(struct device *dev, > * Use spinlock to ensure index doesn't change while it gets > * dereferenced multiple times within a spinlock block elsewhere. > */ > - spin_lock(&drvdata->spinlock); > + raw_spin_lock(&drvdata->spinlock); > config->ctxid_idx = val; > - spin_unlock(&drvdata->spinlock); > + raw_spin_unlock(&drvdata->spinlock); > return size; > } > static DEVICE_ATTR_RW(ctxid_idx); > @@ -1907,10 +1907,10 @@ static ssize_t ctxid_pid_show(struct device *dev, > if (task_active_pid_ns(current) != &init_pid_ns) > return -EINVAL; > > - spin_lock(&drvdata->spinlock); > + raw_spin_lock(&drvdata->spinlock); > idx = config->ctxid_idx; > val = (unsigned long)config->ctxid_pid[idx]; > - spin_unlock(&drvdata->spinlock); > + raw_spin_unlock(&drvdata->spinlock); > return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); > } > > @@ -1945,10 +1945,10 @@ static ssize_t ctxid_pid_store(struct device *dev, > if (kstrtoul(buf, 16, &pid)) > return -EINVAL; > > - spin_lock(&drvdata->spinlock); > + raw_spin_lock(&drvdata->spinlock); > idx = config->ctxid_idx; > config->ctxid_pid[idx] = (u64)pid; > - spin_unlock(&drvdata->spinlock); > + raw_spin_unlock(&drvdata->spinlock); > return size; > } > static DEVICE_ATTR_RW(ctxid_pid); > @@ -1968,10 +1968,10 @@ static ssize_t ctxid_masks_show(struct device *dev, > if (task_active_pid_ns(current) != &init_pid_ns) > return -EINVAL; > > - spin_lock(&drvdata->spinlock); > + raw_spin_lock(&drvdata->spinlock); > val1 = config->ctxid_mask0; > val2 = config->ctxid_mask1; > - spin_unlock(&drvdata->spinlock); > + raw_spin_unlock(&drvdata->spinlock); > return scnprintf(buf, PAGE_SIZE, "%#lx %#lx\n", val1, val2); > } > > @@ -2004,7 +2004,7 @@ static ssize_t ctxid_masks_store(struct device *dev, > if ((drvdata->numcidc > 4) && (nr_inputs != 2)) > return -EINVAL; > > - spin_lock(&drvdata->spinlock); > + raw_spin_lock(&drvdata->spinlock); > /* > * each byte[0..3] controls mask value applied to ctxid > * comparator[0..3] > @@ -2076,7 +2076,7 @@ static ssize_t ctxid_masks_store(struct device *dev, > mask >>= 0x8; > } > > - spin_unlock(&drvdata->spinlock); > + raw_spin_unlock(&drvdata->spinlock); > return size; > } > static DEVICE_ATTR_RW(ctxid_masks); > @@ -2110,9 +2110,9 @@ static ssize_t vmid_idx_store(struct device *dev, > * Use spinlock to ensure index doesn't change while it gets > * dereferenced multiple times within a spinlock block elsewhere. > */ > - spin_lock(&drvdata->spinlock); > + raw_spin_lock(&drvdata->spinlock); > config->vmid_idx = val; > - spin_unlock(&drvdata->spinlock); > + raw_spin_unlock(&drvdata->spinlock); > return size; > } > static DEVICE_ATTR_RW(vmid_idx); > @@ -2132,9 +2132,9 @@ static ssize_t vmid_val_show(struct device *dev, > if (!task_is_in_init_pid_ns(current)) > return -EINVAL; > > - spin_lock(&drvdata->spinlock); > + raw_spin_lock(&drvdata->spinlock); > val = (unsigned long)config->vmid_val[config->vmid_idx]; > - spin_unlock(&drvdata->spinlock); > + raw_spin_unlock(&drvdata->spinlock); > return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); > } > > @@ -2162,9 +2162,9 @@ static ssize_t vmid_val_store(struct device *dev, > if (kstrtoul(buf, 16, &val)) > return -EINVAL; > > - spin_lock(&drvdata->spinlock); > + raw_spin_lock(&drvdata->spinlock); > config->vmid_val[config->vmid_idx] = (u64)val; > - spin_unlock(&drvdata->spinlock); > + raw_spin_unlock(&drvdata->spinlock); > return size; > } > static DEVICE_ATTR_RW(vmid_val); > @@ -2183,10 +2183,10 @@ static ssize_t vmid_masks_show(struct device *dev, > if (!task_is_in_init_pid_ns(current)) > return -EINVAL; > > - spin_lock(&drvdata->spinlock); > + raw_spin_lock(&drvdata->spinlock); > val1 = config->vmid_mask0; > val2 = config->vmid_mask1; > - spin_unlock(&drvdata->spinlock); > + raw_spin_unlock(&drvdata->spinlock); > return scnprintf(buf, PAGE_SIZE, "%#lx %#lx\n", val1, val2); > } > > @@ -2218,7 +2218,7 @@ static ssize_t vmid_masks_store(struct device *dev, > if ((drvdata->numvmidc > 4) && (nr_inputs != 2)) > return -EINVAL; > > - spin_lock(&drvdata->spinlock); > + raw_spin_lock(&drvdata->spinlock); > > /* > * each byte[0..3] controls mask value applied to vmid > @@ -2291,7 +2291,7 @@ static ssize_t vmid_masks_store(struct device *dev, > else > mask >>= 0x8; > } > - spin_unlock(&drvdata->spinlock); > + raw_spin_unlock(&drvdata->spinlock); > return size; > } > static DEVICE_ATTR_RW(vmid_masks); > diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h > index 2b92de17b5a2..bd7db36ba197 100644 > --- a/drivers/hwtracing/coresight/coresight-etm4x.h > +++ b/drivers/hwtracing/coresight/coresight-etm4x.h > @@ -989,7 +989,7 @@ struct etmv4_drvdata { > struct clk *pclk; > void __iomem *base; > struct coresight_device *csdev; > - spinlock_t spinlock; > + raw_spinlock_t spinlock; > int cpu; > u8 arch; > u8 nr_pe;

4 months, 2 weeks

Re: [PATCH v5 8/9] coresight-tmc: change tmc_drvdata spinlock's type to raw_spinlock_t

by Suzuki K Poulose

Hi Levi, On 06/03/2025 09:47, Yeoreum Yun wrote: > In coresight-tmc drivers, tmc_drvdata->spinlock can be held > during __schedule() by perf_event_task_sched_out()/in(). > > Since tmc_drvdata->spinlock type is spinlock_t and > perf_event_task_sched_out()/in() is called after acquiring rq_lock, > which is raw_spinlock_t (an unsleepable lock), > this poses an issue in PREEMPT_RT kernel where spinlock_t is sleepable. > > To address this, change type tmc_drvdata->spinlock in coresight-tmc drivers, > which can be called by perf_event_task_sched_out()/in(), > from spinlock_t to raw_spinlock_t. > > Reviewed-by: James Clark <james.clark(a)linaro.org> > Reviewed-by: Mike Leach <mike.leach(a)linaro.org> > Signed-off-by: Yeoreum Yun <yeoreum.yun(a)arm.com> Unfortunately, this still doesn't cover the current coresight next branch. I get build errors as below : "[PATCH] coresight-tmc: change tmc_drvdata spinlock's type to" has style problems, please review. This is because, we merged the coresight panic trace support in the coresight next, on 21st Feb. NOTE: If any of the errors are false positives, please report them to the maintainer, see CHECKPATCH in MAINTAINERS. CALL scripts/checksyscalls.sh CC [M] drivers/hwtracing/coresight/coresight-tmc-core.o CC [M] drivers/hwtracing/coresight/coresight-tmc-etf.o CC [M] drivers/hwtracing/coresight/coresight-tmc-etr.o CC [M] drivers/hwtracing/coresight/coresight-catu.o In file included from ./include/linux/mmzone.h:8, from ./include/linux/gfp.h:7, from ./include/linux/slab.h:16, from ./include/linux/resource_ext.h:11, from ./include/linux/acpi.h:13, from drivers/hwtracing/coresight/coresight-tmc-core.c:7: drivers/hwtracing/coresight/coresight-tmc-core.c: In function ‘tmc_crashdata_open’: drivers/hwtracing/coresight/coresight-tmc-core.c:361:20: error: passing argument 1 of ‘spinlock_check’ from incompatible pointer type [-Werror=incompatible-pointer-types] 361 | spin_lock_irqsave(&drvdata->spinlock, flags); | ^~~~~~~~~~~~~~~~~~ | | | raw_spinlock_t * {aka struct raw_spinlock *} ./include/linux/spinlock.h:244:34: note: in definition of macro ‘raw_spin_lock_irqsave’ 244 | flags = _raw_spin_lock_irqsave(lock); \ | ^~~~ drivers/hwtracing/coresight/coresight-tmc-core.c:361:2: note: in expansion of macro ‘spin_lock_irqsave’ 361 | spin_lock_irqsave(&drvdata->spinlock, flags); | ^~~~~~~~~~~~~~~~~ In file included from ./include/linux/mmzone.h:8, from ./include/linux/gfp.h:7, from ./include/linux/slab.h:16, from ./include/linux/resource_ext.h:11, from ./include/linux/acpi.h:13, from drivers/hwtracing/coresight/coresight-tmc-core.c:7: ./include/linux/spinlock.h:324:67: note: expected ‘spinlock_t *’ {aka ‘struct spinlock *’} but argument is of type ‘raw_spinlock_t *’ {aka ‘struct raw_spinlock *’} 324 | static __always_inline raw_spinlock_t *spinlock_check(spinlock_t *lock) Cheers Suzuki

4 months, 2 weeks

Re: [PATCH v15 02/10] Coresight: Add trace_id function to retrieving the trace ID

by Mike Leach

Hi Jie On Wed, 5 Mar 2025 at 13:27, Jie Gan <quic_jiegan(a)quicinc.com> wrote: > > > > On 3/5/2025 7:07 PM, Mike Leach wrote: > > Hi, > > > > On Mon, 3 Mar 2025 at 03:30, Jie Gan <quic_jiegan(a)quicinc.com> wrote: > >> > >> Add 'trace_id' function pointer in coresight_ops. It's responsible for retrieving > >> the device's trace ID. > >> > >> Co-developed-by: James Clark <james.clark(a)linaro.org> > >> Signed-off-by: James Clark <james.clark(a)linaro.org> > >> Reviewed-by: James Clark <james.clark(a)linaro.org> > >> Signed-off-by: Jie Gan <quic_jiegan(a)quicinc.com> > >> --- > >> drivers/hwtracing/coresight/coresight-core.c | 30 +++++++++++++++++++ > >> drivers/hwtracing/coresight/coresight-dummy.c | 13 +++++++- > >> .../coresight/coresight-etm3x-core.c | 1 + > >> .../coresight/coresight-etm4x-core.c | 1 + > >> drivers/hwtracing/coresight/coresight-stm.c | 11 +++++++ > >> drivers/hwtracing/coresight/coresight-tpda.c | 11 +++++++ > >> include/linux/coresight.h | 5 ++++ > >> 7 files changed, 71 insertions(+), 1 deletion(-) > >> > >> diff --git a/drivers/hwtracing/coresight/coresight-core.c b/drivers/hwtracing/coresight/coresight-core.c > >> index ab55e10d4b79..32aa07f4f8c1 100644 > >> --- a/drivers/hwtracing/coresight/coresight-core.c > >> +++ b/drivers/hwtracing/coresight/coresight-core.c > >> @@ -24,6 +24,7 @@ > >> #include "coresight-etm-perf.h" > >> #include "coresight-priv.h" > >> #include "coresight-syscfg.h" > >> +#include "coresight-trace-id.h" > >> > >> /* > >> * Mutex used to lock all sysfs enable and disable actions and loading and > >> @@ -1557,6 +1558,35 @@ void coresight_remove_driver(struct amba_driver *amba_drv, > >> } > >> EXPORT_SYMBOL_GPL(coresight_remove_driver); > >> > >> +int coresight_etm_get_trace_id(struct coresight_device *csdev, enum cs_mode mode, > >> + struct coresight_device *sink) > >> +{ > >> + int trace_id; > >> + int cpu = source_ops(csdev)->cpu_id(csdev); > >> + > > > > This is a global funciton so need to check that this csdev is a > > source,. and does provide a cpu function before calling it. > > > > Hi Mike, > > I put this function here because it's required by etm3x and etm4x. It's > intended to be called only by ETM devices, which are definitely source > devices and have a cpu function. > I fully understand the intent, but for a function that can be accessed from anywhere, it is safer to validate input rather than assume any caller will always respect the input conditions. Lots of other places in the coresight drivers check that these functions exist before calling them. Regards Mike > Jie > > >> + switch (mode) { > >> + case CS_MODE_SYSFS: > >> + trace_id = coresight_trace_id_get_cpu_id(cpu); > >> + break; > >> + case CS_MODE_PERF: > >> + if (WARN_ON(!sink)) > >> + return -EINVAL; > >> + > >> + trace_id = coresight_trace_id_get_cpu_id_map(cpu, &sink->perf_sink_id_map); > >> + break; > >> + default: > >> + trace_id = -EINVAL; > >> + break; > >> + } > >> + > >> + if (!IS_VALID_CS_TRACE_ID(trace_id)) > >> + dev_err(&csdev->dev, > >> + "Failed to allocate trace ID on CPU%d\n", cpu); > >> + > >> + return trace_id; > >> +} > >> +EXPORT_SYMBOL_GPL(coresight_etm_get_trace_id); > >> + > >> MODULE_LICENSE("GPL v2"); > >> MODULE_AUTHOR("Pratik Patel <pratikp(a)codeaurora.org>"); > >> MODULE_AUTHOR("Mathieu Poirier <mathieu.poirier(a)linaro.org>"); > >> diff --git a/drivers/hwtracing/coresight/coresight-dummy.c b/drivers/hwtracing/coresight/coresight-dummy.c > >> index 9be53be8964b..b5692ba358c1 100644 > >> --- a/drivers/hwtracing/coresight/coresight-dummy.c > >> +++ b/drivers/hwtracing/coresight/coresight-dummy.c > >> @@ -41,6 +41,16 @@ static void dummy_source_disable(struct coresight_device *csdev, > >> dev_dbg(csdev->dev.parent, "Dummy source disabled\n"); > >> } > >> > >> +static int dummy_source_trace_id(struct coresight_device *csdev, __maybe_unused enum cs_mode mode, > >> + __maybe_unused struct coresight_device *sink) > >> +{ > >> + struct dummy_drvdata *drvdata; > >> + > >> + drvdata = dev_get_drvdata(csdev->dev.parent); > >> + > >> + return drvdata->traceid; > >> +} > >> + > >> static int dummy_sink_enable(struct coresight_device *csdev, enum cs_mode mode, > >> void *data) > >> { > >> @@ -62,7 +72,8 @@ static const struct coresight_ops_source dummy_source_ops = { > >> }; > >> > >> static const struct coresight_ops dummy_source_cs_ops = { > >> - .source_ops = &dummy_source_ops, > >> + .trace_id = dummy_source_trace_id, > >> + .source_ops = &dummy_source_ops, > >> }; > >> > >> static const struct coresight_ops_sink dummy_sink_ops = { > >> diff --git a/drivers/hwtracing/coresight/coresight-etm3x-core.c b/drivers/hwtracing/coresight/coresight-etm3x-core.c > >> index c103f4c70f5d..c1dda4bc4a2f 100644 > >> --- a/drivers/hwtracing/coresight/coresight-etm3x-core.c > >> +++ b/drivers/hwtracing/coresight/coresight-etm3x-core.c > >> @@ -704,6 +704,7 @@ static const struct coresight_ops_source etm_source_ops = { > >> }; > >> > >> static const struct coresight_ops etm_cs_ops = { > >> + .trace_id = coresight_etm_get_trace_id, > >> .source_ops = &etm_source_ops, > >> }; > >> > >> diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c > >> index 2c1a60577728..cfd116b87460 100644 > >> --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c > >> +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c > >> @@ -1067,6 +1067,7 @@ static const struct coresight_ops_source etm4_source_ops = { > >> }; > >> > >> static const struct coresight_ops etm4_cs_ops = { > >> + .trace_id = coresight_etm_get_trace_id, > >> .source_ops = &etm4_source_ops, > >> }; > >> > >> diff --git a/drivers/hwtracing/coresight/coresight-stm.c b/drivers/hwtracing/coresight/coresight-stm.c > >> index b581a30a1cd9..aca25b5e3be2 100644 > >> --- a/drivers/hwtracing/coresight/coresight-stm.c > >> +++ b/drivers/hwtracing/coresight/coresight-stm.c > >> @@ -281,12 +281,23 @@ static void stm_disable(struct coresight_device *csdev, > >> } > >> } > >> > >> +static int stm_trace_id(struct coresight_device *csdev, __maybe_unused enum cs_mode mode, > >> + __maybe_unused struct coresight_device *sink) > >> +{ > >> + struct stm_drvdata *drvdata; > >> + > >> + drvdata = dev_get_drvdata(csdev->dev.parent); > >> + > >> + return drvdata->traceid; > >> +} > >> + > >> static const struct coresight_ops_source stm_source_ops = { > >> .enable = stm_enable, > >> .disable = stm_disable, > >> }; > >> > >> static const struct coresight_ops stm_cs_ops = { > >> + .trace_id = stm_trace_id, > >> .source_ops = &stm_source_ops, > >> }; > >> > >> diff --git a/drivers/hwtracing/coresight/coresight-tpda.c b/drivers/hwtracing/coresight/coresight-tpda.c > >> index 573da8427428..94c2201fc8d3 100644 > >> --- a/drivers/hwtracing/coresight/coresight-tpda.c > >> +++ b/drivers/hwtracing/coresight/coresight-tpda.c > >> @@ -241,12 +241,23 @@ static void tpda_disable(struct coresight_device *csdev, > >> dev_dbg(drvdata->dev, "TPDA inport %d disabled\n", in->dest_port); > >> } > >> > >> +static int tpda_trace_id(struct coresight_device *csdev, __maybe_unused enum cs_mode mode, > >> + __maybe_unused struct coresight_device *sink) > >> +{ > >> + struct tpda_drvdata *drvdata; > >> + > >> + drvdata = dev_get_drvdata(csdev->dev.parent); > >> + > >> + return drvdata->atid; > >> +} > >> + > >> static const struct coresight_ops_link tpda_link_ops = { > >> .enable = tpda_enable, > >> .disable = tpda_disable, > >> }; > >> > >> static const struct coresight_ops tpda_cs_ops = { > >> + .trace_id = tpda_trace_id, > >> .link_ops = &tpda_link_ops, > >> }; > >> > >> diff --git a/include/linux/coresight.h b/include/linux/coresight.h > >> index c7cd5886c908..ce9a5e71b261 100644 > >> --- a/include/linux/coresight.h > >> +++ b/include/linux/coresight.h > >> @@ -335,6 +335,7 @@ enum cs_mode { > >> CS_MODE_PERF, > >> }; > >> > >> +#define coresight_ops(csdev) csdev->ops > >> #define source_ops(csdev) csdev->ops->source_ops > >> #define sink_ops(csdev) csdev->ops->sink_ops > >> #define link_ops(csdev) csdev->ops->link_ops > >> @@ -421,6 +422,8 @@ struct coresight_ops_panic { > >> }; > >> > >> struct coresight_ops { > >> + int (*trace_id)(struct coresight_device *csdev, enum cs_mode mode, > >> + struct coresight_device *sink); > >> const struct coresight_ops_sink *sink_ops; > >> const struct coresight_ops_link *link_ops; > >> const struct coresight_ops_source *source_ops; > >> @@ -709,4 +712,6 @@ int coresight_init_driver(const char *drv, struct amba_driver *amba_drv, > >> > >> void coresight_remove_driver(struct amba_driver *amba_drv, > >> struct platform_driver *pdev_drv); > >> +int coresight_etm_get_trace_id(struct coresight_device *csdev, enum cs_mode mode, > >> + struct coresight_device *sink); > >> #endif /* _LINUX_COREISGHT_H */ > >> -- > >> 2.34.1 > >> > > > > > -- Mike Leach Principal Engineer, ARM Ltd. Manchester Design Centre. UK

4 months, 2 weeks

[PATCH] coresight: Add a KUnit test for coresight_find_default_sink()

by James Clark

Add a test to confirm that default sink selection skips over an ETF and returns an ETR even if it's further away. This also makes it easier to add new unit tests in the future. Signed-off-by: James Clark <james.clark(a)linaro.org> --- drivers/hwtracing/coresight/Kconfig | 9 ++ drivers/hwtracing/coresight/Makefile | 1 + drivers/hwtracing/coresight/coresight-core.c | 1 + .../coresight/coresight-kunit-tests.c | 90 +++++++++++++++++++ 4 files changed, 101 insertions(+) create mode 100644 drivers/hwtracing/coresight/coresight-kunit-tests.c diff --git a/drivers/hwtracing/coresight/Kconfig b/drivers/hwtracing/coresight/Kconfig index 06f0a7594169..056d04bc540a 100644 --- a/drivers/hwtracing/coresight/Kconfig +++ b/drivers/hwtracing/coresight/Kconfig @@ -247,4 +247,13 @@ config CORESIGHT_DUMMY To compile this driver as a module, choose M here: the module will be called coresight-dummy. + +config CORESIGHT_KUNIT_TESTS + tristate "Enable Coresight unit tests" + depends on KUNIT + default KUNIT_ALL_TESTS + help + Enable Coresight unit tests. Only useful for development and not + intended for production. + endif diff --git a/drivers/hwtracing/coresight/Makefile b/drivers/hwtracing/coresight/Makefile index 4ba478211b31..c170a41b3056 100644 --- a/drivers/hwtracing/coresight/Makefile +++ b/drivers/hwtracing/coresight/Makefile @@ -51,3 +51,4 @@ coresight-cti-y := coresight-cti-core.o coresight-cti-platform.o \ coresight-cti-sysfs.o obj-$(CONFIG_ULTRASOC_SMB) += ultrasoc-smb.o obj-$(CONFIG_CORESIGHT_DUMMY) += coresight-dummy.o +obj-$(CONFIG_CORESIGHT_KUNIT_TESTS) += coresight-kunit-tests.o diff --git a/drivers/hwtracing/coresight/coresight-core.c b/drivers/hwtracing/coresight/coresight-core.c index ea38ecf26fcb..ce63b68d5503 100644 --- a/drivers/hwtracing/coresight/coresight-core.c +++ b/drivers/hwtracing/coresight/coresight-core.c @@ -869,6 +869,7 @@ coresight_find_default_sink(struct coresight_device *csdev) } return csdev->def_sink; } +EXPORT_SYMBOL_GPL(coresight_find_default_sink); static int coresight_remove_sink_ref(struct device *dev, void *data) { diff --git a/drivers/hwtracing/coresight/coresight-kunit-tests.c b/drivers/hwtracing/coresight/coresight-kunit-tests.c new file mode 100644 index 000000000000..d022bacc8357 --- /dev/null +++ b/drivers/hwtracing/coresight/coresight-kunit-tests.c @@ -0,0 +1,90 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include <kunit/test.h> +#include <kunit/device.h> +#include <linux/coresight.h> + +#include "coresight-priv.h" + +static struct coresight_device *coresight_test_device(struct device *dev) +{ + struct coresight_device *csdev = devm_kcalloc(dev, 1, + sizeof(struct coresight_device), + GFP_KERNEL); + csdev->pdata = devm_kcalloc(dev, 1, + sizeof(struct coresight_platform_data), + GFP_KERNEL); + return csdev; +} + +static void coresight_free_test_device(struct device *dev, + struct coresight_device *csdev) +{ + devm_kfree(dev, csdev->pdata->out_conns); + devm_kfree(dev, csdev->pdata); + devm_kfree(dev, csdev); +} + +static int coresight_test_cpuid(struct coresight_device *csdev) +{ + return 0; +} + +static void test_default_sink(struct kunit *test) +{ + /* + * ETM -> ETF -> ETR -> CATU + * ^ + * | default + */ + struct device *dev = kunit_device_register(test, "coresight_kunit"); + struct coresight_device *etm = coresight_test_device(dev), + *etf = coresight_test_device(dev), + *etr = coresight_test_device(dev), + *catu = coresight_test_device(dev); + struct coresight_connection conn = {}; + struct coresight_ops_source src_ops = {.cpu_id = coresight_test_cpuid }; + struct coresight_ops etm_cs_ops = { .source_ops = &src_ops }; + + etm->type = CORESIGHT_DEV_TYPE_SOURCE; + etm->ops = &etm_cs_ops; + etf->type = CORESIGHT_DEV_TYPE_LINKSINK; + etf->subtype.sink_subtype = CORESIGHT_DEV_SUBTYPE_SINK_BUFFER; + etr->type = CORESIGHT_DEV_TYPE_SINK; + etr->subtype.sink_subtype = CORESIGHT_DEV_SUBTYPE_SINK_SYSMEM; + catu->type = CORESIGHT_DEV_TYPE_HELPER; + + conn.src_dev = etm; + conn.dest_dev = etf; + coresight_add_out_conn(dev, etm->pdata, &conn); + + conn.src_dev = etf; + conn.dest_dev = etr; + coresight_add_out_conn(dev, etf->pdata, &conn); + + conn.src_dev = etr; + conn.dest_dev = catu; + coresight_add_out_conn(dev, etr->pdata, &conn); + + KUNIT_ASSERT_PTR_EQ(test, coresight_find_default_sink(etm), etr); + + coresight_free_test_device(dev, etm); + coresight_free_test_device(dev, etf); + coresight_free_test_device(dev, etr); + coresight_free_test_device(dev, catu); +} + +static struct kunit_case coresight_testcases[] = { + KUNIT_CASE(test_default_sink), + {} +}; + +static struct kunit_suite coresight_test_suite = { + .name = "coresight_test_suite", + .test_cases = coresight_testcases, +}; + +kunit_test_suites(&coresight_test_suite); +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("James Clark <james.clark(a)linaro.org>"); +MODULE_DESCRIPTION("Arm CoreSight KUnit tests"); -- 2.34.1

4 months, 2 weeks

Re: [PATCH v15 02/10] Coresight: Add trace_id function to retrieving the trace ID

by Mike Leach

Hi, On Mon, 3 Mar 2025 at 03:30, Jie Gan <quic_jiegan(a)quicinc.com> wrote: > > Add 'trace_id' function pointer in coresight_ops. It's responsible for retrieving > the device's trace ID. > > Co-developed-by: James Clark <james.clark(a)linaro.org> > Signed-off-by: James Clark <james.clark(a)linaro.org> > Reviewed-by: James Clark <james.clark(a)linaro.org> > Signed-off-by: Jie Gan <quic_jiegan(a)quicinc.com> > --- > drivers/hwtracing/coresight/coresight-core.c | 30 +++++++++++++++++++ > drivers/hwtracing/coresight/coresight-dummy.c | 13 +++++++- > .../coresight/coresight-etm3x-core.c | 1 + > .../coresight/coresight-etm4x-core.c | 1 + > drivers/hwtracing/coresight/coresight-stm.c | 11 +++++++ > drivers/hwtracing/coresight/coresight-tpda.c | 11 +++++++ > include/linux/coresight.h | 5 ++++ > 7 files changed, 71 insertions(+), 1 deletion(-) > > diff --git a/drivers/hwtracing/coresight/coresight-core.c b/drivers/hwtracing/coresight/coresight-core.c > index ab55e10d4b79..32aa07f4f8c1 100644 > --- a/drivers/hwtracing/coresight/coresight-core.c > +++ b/drivers/hwtracing/coresight/coresight-core.c > @@ -24,6 +24,7 @@ > #include "coresight-etm-perf.h" > #include "coresight-priv.h" > #include "coresight-syscfg.h" > +#include "coresight-trace-id.h" > > /* > * Mutex used to lock all sysfs enable and disable actions and loading and > @@ -1557,6 +1558,35 @@ void coresight_remove_driver(struct amba_driver *amba_drv, > } > EXPORT_SYMBOL_GPL(coresight_remove_driver); > > +int coresight_etm_get_trace_id(struct coresight_device *csdev, enum cs_mode mode, > + struct coresight_device *sink) > +{ > + int trace_id; > + int cpu = source_ops(csdev)->cpu_id(csdev); > + This is a global funciton so need to check that this csdev is a source,. and does provide a cpu function before calling it. > + switch (mode) { > + case CS_MODE_SYSFS: > + trace_id = coresight_trace_id_get_cpu_id(cpu); > + break; > + case CS_MODE_PERF: > + if (WARN_ON(!sink)) > + return -EINVAL; > + > + trace_id = coresight_trace_id_get_cpu_id_map(cpu, &sink->perf_sink_id_map); > + break; > + default: > + trace_id = -EINVAL; > + break; > + } > + > + if (!IS_VALID_CS_TRACE_ID(trace_id)) > + dev_err(&csdev->dev, > + "Failed to allocate trace ID on CPU%d\n", cpu); > + > + return trace_id; > +} > +EXPORT_SYMBOL_GPL(coresight_etm_get_trace_id); > + > MODULE_LICENSE("GPL v2"); > MODULE_AUTHOR("Pratik Patel <pratikp(a)codeaurora.org>"); > MODULE_AUTHOR("Mathieu Poirier <mathieu.poirier(a)linaro.org>"); > diff --git a/drivers/hwtracing/coresight/coresight-dummy.c b/drivers/hwtracing/coresight/coresight-dummy.c > index 9be53be8964b..b5692ba358c1 100644 > --- a/drivers/hwtracing/coresight/coresight-dummy.c > +++ b/drivers/hwtracing/coresight/coresight-dummy.c > @@ -41,6 +41,16 @@ static void dummy_source_disable(struct coresight_device *csdev, > dev_dbg(csdev->dev.parent, "Dummy source disabled\n"); > } > > +static int dummy_source_trace_id(struct coresight_device *csdev, __maybe_unused enum cs_mode mode, > + __maybe_unused struct coresight_device *sink) > +{ > + struct dummy_drvdata *drvdata; > + > + drvdata = dev_get_drvdata(csdev->dev.parent); > + > + return drvdata->traceid; > +} > + > static int dummy_sink_enable(struct coresight_device *csdev, enum cs_mode mode, > void *data) > { > @@ -62,7 +72,8 @@ static const struct coresight_ops_source dummy_source_ops = { > }; > > static const struct coresight_ops dummy_source_cs_ops = { > - .source_ops = &dummy_source_ops, > + .trace_id = dummy_source_trace_id, > + .source_ops = &dummy_source_ops, > }; > > static const struct coresight_ops_sink dummy_sink_ops = { > diff --git a/drivers/hwtracing/coresight/coresight-etm3x-core.c b/drivers/hwtracing/coresight/coresight-etm3x-core.c > index c103f4c70f5d..c1dda4bc4a2f 100644 > --- a/drivers/hwtracing/coresight/coresight-etm3x-core.c > +++ b/drivers/hwtracing/coresight/coresight-etm3x-core.c > @@ -704,6 +704,7 @@ static const struct coresight_ops_source etm_source_ops = { > }; > > static const struct coresight_ops etm_cs_ops = { > + .trace_id = coresight_etm_get_trace_id, > .source_ops = &etm_source_ops, > }; > > diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c > index 2c1a60577728..cfd116b87460 100644 > --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c > +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c > @@ -1067,6 +1067,7 @@ static const struct coresight_ops_source etm4_source_ops = { > }; > > static const struct coresight_ops etm4_cs_ops = { > + .trace_id = coresight_etm_get_trace_id, > .source_ops = &etm4_source_ops, > }; > > diff --git a/drivers/hwtracing/coresight/coresight-stm.c b/drivers/hwtracing/coresight/coresight-stm.c > index b581a30a1cd9..aca25b5e3be2 100644 > --- a/drivers/hwtracing/coresight/coresight-stm.c > +++ b/drivers/hwtracing/coresight/coresight-stm.c > @@ -281,12 +281,23 @@ static void stm_disable(struct coresight_device *csdev, > } > } > > +static int stm_trace_id(struct coresight_device *csdev, __maybe_unused enum cs_mode mode, > + __maybe_unused struct coresight_device *sink) > +{ > + struct stm_drvdata *drvdata; > + > + drvdata = dev_get_drvdata(csdev->dev.parent); > + > + return drvdata->traceid; > +} > + > static const struct coresight_ops_source stm_source_ops = { > .enable = stm_enable, > .disable = stm_disable, > }; > > static const struct coresight_ops stm_cs_ops = { > + .trace_id = stm_trace_id, > .source_ops = &stm_source_ops, > }; > > diff --git a/drivers/hwtracing/coresight/coresight-tpda.c b/drivers/hwtracing/coresight/coresight-tpda.c > index 573da8427428..94c2201fc8d3 100644 > --- a/drivers/hwtracing/coresight/coresight-tpda.c > +++ b/drivers/hwtracing/coresight/coresight-tpda.c > @@ -241,12 +241,23 @@ static void tpda_disable(struct coresight_device *csdev, > dev_dbg(drvdata->dev, "TPDA inport %d disabled\n", in->dest_port); > } > > +static int tpda_trace_id(struct coresight_device *csdev, __maybe_unused enum cs_mode mode, > + __maybe_unused struct coresight_device *sink) > +{ > + struct tpda_drvdata *drvdata; > + > + drvdata = dev_get_drvdata(csdev->dev.parent); > + > + return drvdata->atid; > +} > + > static const struct coresight_ops_link tpda_link_ops = { > .enable = tpda_enable, > .disable = tpda_disable, > }; > > static const struct coresight_ops tpda_cs_ops = { > + .trace_id = tpda_trace_id, > .link_ops = &tpda_link_ops, > }; > > diff --git a/include/linux/coresight.h b/include/linux/coresight.h > index c7cd5886c908..ce9a5e71b261 100644 > --- a/include/linux/coresight.h > +++ b/include/linux/coresight.h > @@ -335,6 +335,7 @@ enum cs_mode { > CS_MODE_PERF, > }; > > +#define coresight_ops(csdev) csdev->ops > #define source_ops(csdev) csdev->ops->source_ops > #define sink_ops(csdev) csdev->ops->sink_ops > #define link_ops(csdev) csdev->ops->link_ops > @@ -421,6 +422,8 @@ struct coresight_ops_panic { > }; > > struct coresight_ops { > + int (*trace_id)(struct coresight_device *csdev, enum cs_mode mode, > + struct coresight_device *sink); > const struct coresight_ops_sink *sink_ops; > const struct coresight_ops_link *link_ops; > const struct coresight_ops_source *source_ops; > @@ -709,4 +712,6 @@ int coresight_init_driver(const char *drv, struct amba_driver *amba_drv, > > void coresight_remove_driver(struct amba_driver *amba_drv, > struct platform_driver *pdev_drv); > +int coresight_etm_get_trace_id(struct coresight_device *csdev, enum cs_mode mode, > + struct coresight_device *sink); > #endif /* _LINUX_COREISGHT_H */ > -- > 2.34.1 > -- Mike Leach Principal Engineer, ARM Ltd. Manchester Design Centre. UK

4 months, 2 weeks

Re: [PATCH v15 00/10] [subset] Coresight: Add Coresight TMC Control Unit driver

by Suzuki K Poulose

On Mon, 03 Mar 2025 11:29:21 +0800, Jie Gan wrote: > The Coresight TMC Control Unit(CTCU) device hosts miscellaneous configuration > registers to control various features related to TMC ETR device. > > The CTCU device works as a helper device physically connected to the TMC ETR device. > --------------------------------------------------------- > |ETR0| |ETR1| > . \ / . > . \ / . > . \ / . > . \ / . > --------------------------------------------------- > ETR0ATID0-ETR0ATID3 CTCU ETR1ATID0-ETR1ATID3 > --------------------------------------------------- > Each ETR has four ATID registers with 128 bits long in total. > e.g. ETR0ATID0-ETR0ATID3 registers are used by ETR0 device. > > [...] I have applied patches 1-9, leaving the DTS update for the platform. [01/10] Coresight: Add support for new APB clock name https://git.kernel.org/coresight/c/dc872c5f [02/10] Coresight: Add trace_id function to retrieving the trace ID https://git.kernel.org/coresight/c/c367a89d [03/10] Coresight: Use coresight_etm_get_trace_id() in traceid_show() https://git.kernel.org/coresight/c/182e8c70 [04/10] Coresight: Introduce a new struct coresight_path https://git.kernel.org/coresight/c/3c03c49b [05/10] Coresight: Allocate trace ID after building the path https://git.kernel.org/coresight/c/d87d76d8 [06/10] Coresight: Change to read the trace ID from coresight_path https://git.kernel.org/coresight/c/7b365f05 [07/10] Coresight: Change functions to accept the coresight_path https://git.kernel.org/coresight/c/080ee83c [08/10] dt-bindings: arm: Add Coresight TMC Control Unit hardware https://git.kernel.org/coresight/c/166df2a1 [09/10] Coresight: Add Coresight TMC Control Unit driver https://git.kernel.org/coresight/c/f78d206f Best regards, -- Suzuki K Poulose <suzuki.poulose(a)arm.com>

4 months, 2 weeks

Re: [PATCH v15 04/10] Coresight: Introduce a new struct coresight_path

by Suzuki K Poulose

On 03/03/2025 03:29, Jie Gan wrote: > Introduce a new strcuture, 'struct coresight_path', to store the data that > utilized by the devices in the path. The coresight_path will be built/released > by coresight_build_path/coresight_release_path functions. > > Signed-off-by: Jie Gan <quic_jiegan(a)quicinc.com> > --- > drivers/hwtracing/coresight/coresight-core.c | 16 +++++----- > .../hwtracing/coresight/coresight-etm-perf.c | 30 ++++++++++--------- > .../hwtracing/coresight/coresight-etm-perf.h | 2 +- > drivers/hwtracing/coresight/coresight-priv.h | 6 ++-- > drivers/hwtracing/coresight/coresight-sysfs.c | 12 ++++---- > include/linux/coresight.h | 10 +++++++ > 6 files changed, 44 insertions(+), 32 deletions(-) > ... > diff --git a/include/linux/coresight.h b/include/linux/coresight.h > index ce9a5e71b261..67cf8bdbe5c0 100644 > --- a/include/linux/coresight.h > +++ b/include/linux/coresight.h > @@ -329,6 +329,16 @@ static struct coresight_dev_list (var) = { \ > > #define to_coresight_device(d) container_of(d, struct coresight_device, dev) > > +/** > + * struct coresight_path - data needed by enable/disable path > + * @path: path from source to sink. This doesn't match the actual variable below. > + * @trace_id: trace_id of the whole path. > + */ > +struct coresight_path { > + struct list_head path_list; > + u8 trace_id; > +}; > + > enum cs_mode { > CS_MODE_DISABLED, > CS_MODE_SYSFS, Suzuki

4 months, 2 weeks

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