CoreSight

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2594 discussions

Re: [PATCH v2] coresight: fix indentation error in cscfg_remove_owned_csdev_configs()

by Suzuki K Poulose

On Wed, 11 Jun 2025 11:30:25 +0100, Yeoreum Yun wrote: > Fix wrong indentation in cscfg_remove_owned_csdev_configs() > > Applied, thanks! [1/1] coresight: fix indentation error in cscfg_remove_owned_csdev_configs() https://git.kernel.org/coresight/c/a80198ba650f Best regards, -- Suzuki K Poulose <suzuki.poulose(a)arm.com>

5 months, 1 week

Re: [PATCH v3 RESEND 04/10] coresight: ctcu: enable byte-cntr for TMC ETR devices

by Mike Leach

Hi, There are some parameters in the new structure that are unused in this patch. please only introduce fields when they start to be used to make review easier. Regards Mike On Mon, 14 Jul 2025 at 07:31, Jie Gan <jie.gan(a)oss.qualcomm.com> wrote: > > The byte-cntr function provided by the CTCU device is used to transfer data > from the ETR buffer to the userspace. An interrupt is triggered if the data > size exceeds the threshold set in the BYTECNTRVAL register. The interrupt > handler counts the number of triggered interruptions and the read function > will read the data from the ETR buffer. > > Signed-off-by: Jie Gan <jie.gan(a)oss.qualcomm.com> > --- > .../testing/sysfs-bus-coresight-devices-ctcu | 5 + > drivers/hwtracing/coresight/Makefile | 2 +- > .../coresight/coresight-ctcu-byte-cntr.c | 102 ++++++++++++++++++ > .../hwtracing/coresight/coresight-ctcu-core.c | 94 +++++++++++++++- > drivers/hwtracing/coresight/coresight-ctcu.h | 49 ++++++++- > 5 files changed, 246 insertions(+), 6 deletions(-) > create mode 100644 Documentation/ABI/testing/sysfs-bus-coresight-devices-ctcu > create mode 100644 drivers/hwtracing/coresight/coresight-ctcu-byte-cntr.c > > diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-ctcu b/Documentation/ABI/testing/sysfs-bus-coresight-devices-ctcu > new file mode 100644 > index 000000000000..e21f5bcb8097 > --- /dev/null > +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-ctcu > @@ -0,0 +1,5 @@ > +What: /sys/bus/coresight/devices/<ctcu-name>/irq_val > +Date: June 2025 > +KernelVersion: 6.16 > +Contact: Tingwei Zhang (QUIC) <quic_tingweiz(a)quicinc.com>; Jinlong Mao (QUIC) <quic_jinlmao(a)quicinc.com>; Jie Gan <jie.gan(a)oss.qualcomm.com> > +Description: (RW) Configure the IRQ value for byte-cntr register. > diff --git a/drivers/hwtracing/coresight/Makefile b/drivers/hwtracing/coresight/Makefile > index 4e7cc3c5bf99..3568d9768567 100644 > --- a/drivers/hwtracing/coresight/Makefile > +++ b/drivers/hwtracing/coresight/Makefile > @@ -54,5 +54,5 @@ coresight-cti-y := coresight-cti-core.o coresight-cti-platform.o \ > obj-$(CONFIG_ULTRASOC_SMB) += ultrasoc-smb.o > obj-$(CONFIG_CORESIGHT_DUMMY) += coresight-dummy.o > obj-$(CONFIG_CORESIGHT_CTCU) += coresight-ctcu.o > -coresight-ctcu-y := coresight-ctcu-core.o > +coresight-ctcu-y := coresight-ctcu-core.o coresight-ctcu-byte-cntr.o > obj-$(CONFIG_CORESIGHT_KUNIT_TESTS) += coresight-kunit-tests.o > diff --git a/drivers/hwtracing/coresight/coresight-ctcu-byte-cntr.c b/drivers/hwtracing/coresight/coresight-ctcu-byte-cntr.c > new file mode 100644 > index 000000000000..d3b6eb7a89fb > --- /dev/null > +++ b/drivers/hwtracing/coresight/coresight-ctcu-byte-cntr.c > @@ -0,0 +1,102 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved. > + */ > + > +#include <linux/coresight.h> > +#include <linux/device.h> > +#include <linux/fs.h> > +#include <linux/interrupt.h> > +#include <linux/of_irq.h> > +#include <linux/uaccess.h> > + > +#include "coresight-ctcu.h" > +#include "coresight-priv.h" > +#include "coresight-tmc.h" > + > +static irqreturn_t byte_cntr_handler(int irq, void *data) > +{ > + struct ctcu_byte_cntr *byte_cntr_data = (struct ctcu_byte_cntr *)data; > + > + atomic_inc(&byte_cntr_data->irq_cnt); > + wake_up(&byte_cntr_data->wq); > + > + byte_cntr_data->irq_num++; > + These two - irq_num & irq_cnt appear to count the same thing. Do not understand why one has to be atomic and the other does not. > + return IRQ_HANDLED; > +} > + > +/* Start the byte-cntr function when the path is enabled. */ > +void ctcu_byte_cntr_start(struct coresight_device *csdev, struct coresight_path *path) > +{ > + struct ctcu_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); > + struct coresight_device *sink = coresight_get_sink(path); > + struct ctcu_byte_cntr *byte_cntr_data; > + int port_num; > + > + if (!sink) > + return; > + > + port_num = coresight_get_port_helper(sink, csdev); > + if (port_num < 0) > + return; > + > + byte_cntr_data = &drvdata->byte_cntr_data[port_num]; > + /* Don't start byte-cntr function when threshold is not set. */ > + if (!byte_cntr_data->thresh_val || byte_cntr_data->enable) > + return; > + > + guard(raw_spinlock_irqsave)(&byte_cntr_data->spin_lock); > + byte_cntr_data->enable = true; > + byte_cntr_data->reading_buf = false; > +} > + > +/* Stop the byte-cntr function when the path is disabled. */ > +void ctcu_byte_cntr_stop(struct coresight_device *csdev, struct coresight_path *path) > +{ > + struct ctcu_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); > + struct coresight_device *sink = coresight_get_sink(path); > + struct ctcu_byte_cntr *byte_cntr_data; > + int port_num; > + > + if (!sink || coresight_get_mode(sink) == CS_MODE_SYSFS) > + return; > + > + port_num = coresight_get_port_helper(sink, csdev); > + if (port_num < 0) > + return; > + > + byte_cntr_data = &drvdata->byte_cntr_data[port_num]; > + guard(raw_spinlock_irqsave)(&byte_cntr_data->spin_lock); > + byte_cntr_data->enable = false; > +} > + > +void ctcu_byte_cntr_init(struct device *dev, struct ctcu_drvdata *drvdata, int etr_num) > +{ > + struct ctcu_byte_cntr *byte_cntr_data; > + struct device_node *nd = dev->of_node; > + int byte_cntr_irq, ret, i; > + > + for (i = 0; i < etr_num; i++) { > + byte_cntr_data = &drvdata->byte_cntr_data[i]; > + byte_cntr_irq = of_irq_get_byname(nd, byte_cntr_data->irq_name); > + if (byte_cntr_irq < 0) { > + dev_err(dev, "Failed to get IRQ from DT for %s\n", > + byte_cntr_data->irq_name); > + continue; > + } > + > + ret = devm_request_irq(dev, byte_cntr_irq, byte_cntr_handler, > + IRQF_TRIGGER_RISING | IRQF_SHARED, > + dev_name(dev), byte_cntr_data); > + if (ret) { > + dev_err(dev, "Failed to register IRQ for %s\n", > + byte_cntr_data->irq_name); > + continue; > + } > + > + byte_cntr_data->byte_cntr_irq = byte_cntr_irq; > + disable_irq(byte_cntr_data->byte_cntr_irq); > + init_waitqueue_head(&byte_cntr_data->wq); > + } > +} > diff --git a/drivers/hwtracing/coresight/coresight-ctcu-core.c b/drivers/hwtracing/coresight/coresight-ctcu-core.c > index 28ea4a216345..721836d42523 100644 > --- a/drivers/hwtracing/coresight/coresight-ctcu-core.c > +++ b/drivers/hwtracing/coresight/coresight-ctcu-core.c > @@ -15,6 +15,7 @@ > #include <linux/platform_device.h> > #include <linux/pm_runtime.h> > #include <linux/slab.h> > +#include <linux/sizes.h> > > #include "coresight-ctcu.h" > #include "coresight-priv.h" > @@ -45,17 +46,23 @@ DEFINE_CORESIGHT_DEVLIST(ctcu_devs, "ctcu"); > > #define CTCU_ATID_REG_BIT(traceid) (traceid % 32) > #define CTCU_ATID_REG_SIZE 0x10 > +#define CTCU_ETR0_IRQCTRL 0x6c > +#define CTCU_ETR1_IRQCTRL 0x70 > #define CTCU_ETR0_ATID0 0xf8 > #define CTCU_ETR1_ATID0 0x108 > > static const struct ctcu_etr_config sa8775p_etr_cfgs[] = { > { > - .atid_offset = CTCU_ETR0_ATID0, > - .port_num = 0, > + .atid_offset = CTCU_ETR0_ATID0, > + .irq_ctrl_offset = CTCU_ETR0_IRQCTRL, > + .irq_name = "etr0", > + .port_num = 0, > }, > { > - .atid_offset = CTCU_ETR1_ATID0, > - .port_num = 1, > + .atid_offset = CTCU_ETR1_ATID0, > + .irq_ctrl_offset = CTCU_ETR1_IRQCTRL, > + .irq_name = "etr1", > + .port_num = 1, > }, > }; > > @@ -64,6 +71,76 @@ static const struct ctcu_config sa8775p_cfgs = { > .num_etr_config = ARRAY_SIZE(sa8775p_etr_cfgs), > }; > > +static void ctcu_program_register(struct ctcu_drvdata *drvdata, u32 val, u32 offset) > +{ > + CS_UNLOCK(drvdata->base); > + ctcu_writel(drvdata, val, offset); > + CS_LOCK(drvdata->base); > +} > + > +static ssize_t irq_val_show(struct device *dev, struct device_attribute *attr, > + char *buf) > +{ > + struct ctcu_drvdata *drvdata = dev_get_drvdata(dev->parent); > + int i, len = 0; > + > + for (i = 0; i < ETR_MAX_NUM; i++) { > + if (drvdata->byte_cntr_data[i].irq_ctrl_offset) > + len += scnprintf(buf + len, PAGE_SIZE - len, "%u ", > + drvdata->byte_cntr_data[i].thresh_val); > + } > + > + len += scnprintf(buf + len, PAGE_SIZE - len, "\n"); > + > + return len; > +} > + > +/* Program a valid value into IRQCTRL register will enable byte-cntr interrupt */ > +static ssize_t irq_val_store(struct device *dev, struct device_attribute *attr, > + const char *buf, size_t size) > +{ > + struct ctcu_drvdata *drvdata = dev_get_drvdata(dev->parent); > + u32 thresh_vals[ETR_MAX_NUM] = { 0 }; > + u32 irq_ctrl_offset; > + int num, i; > + > + num = sscanf(buf, "%i %i", &thresh_vals[0], &thresh_vals[1]); > + if (num <= 0 || num > ETR_MAX_NUM) > + return -EINVAL; > + > + /* Threshold 0 disables the interruption. */ > + guard(raw_spinlock_irqsave)(&drvdata->spin_lock); > + for (i = 0; i < num; i++) { > + /* A small threshold will result in a large number of interruptions */ > + if (thresh_vals[i] && thresh_vals[i] < SZ_4K) > + return -EINVAL; > + > + if (drvdata->byte_cntr_data[i].irq_ctrl_offset) { > + drvdata->byte_cntr_data[i].thresh_val = thresh_vals[i]; > + irq_ctrl_offset = drvdata->byte_cntr_data[i].irq_ctrl_offset; > + /* A one value for IRQCTRL register represents 8 bytes */ > + ctcu_program_register(drvdata, thresh_vals[i] / 8, irq_ctrl_offset); > + } > + } > + > + return size; > +} > +static DEVICE_ATTR_RW(irq_val); > + I think it may make more sense to call this something with "threshold" - as it is thresholds that are being set. > +static struct attribute *ctcu_attrs[] = { > + &dev_attr_irq_val.attr, > + NULL, > +}; > + > +static struct attribute_group ctcu_attr_grp = { > + .attrs = ctcu_attrs, > +}; > + > +static const struct attribute_group *ctcu_attr_grps[] = { > + &ctcu_attr_grp, > + NULL, > +}; > + > static void ctcu_program_atid_register(struct ctcu_drvdata *drvdata, u32 reg_offset, > u8 bit, bool enable) > { > @@ -143,6 +220,8 @@ static int ctcu_enable(struct coresight_device *csdev, enum cs_mode mode, void * > { > struct coresight_path *path = (struct coresight_path *)data; > > + ctcu_byte_cntr_start(csdev, path); > + > return ctcu_set_etr_traceid(csdev, path, true); > } > > @@ -150,6 +229,8 @@ static int ctcu_disable(struct coresight_device *csdev, void *data) > { > struct coresight_path *path = (struct coresight_path *)data; > > + ctcu_byte_cntr_stop(csdev, path); > + > return ctcu_set_etr_traceid(csdev, path, false); > } > > @@ -200,7 +281,11 @@ static int ctcu_probe(struct platform_device *pdev) > for (i = 0; i < cfgs->num_etr_config; i++) { > etr_cfg = &cfgs->etr_cfgs[i]; > drvdata->atid_offset[i] = etr_cfg->atid_offset; > + drvdata->byte_cntr_data[i].irq_name = etr_cfg->irq_name; > + drvdata->byte_cntr_data[i].irq_ctrl_offset = > + etr_cfg->irq_ctrl_offset; > } > + ctcu_byte_cntr_init(dev, drvdata, cfgs->num_etr_config); > } > } > > @@ -212,6 +297,7 @@ static int ctcu_probe(struct platform_device *pdev) > desc.subtype.helper_subtype = CORESIGHT_DEV_SUBTYPE_HELPER_CTCU; > desc.pdata = pdata; > desc.dev = dev; > + desc.groups = ctcu_attr_grps; > desc.ops = &ctcu_ops; > desc.access = CSDEV_ACCESS_IOMEM(base); > > diff --git a/drivers/hwtracing/coresight/coresight-ctcu.h b/drivers/hwtracing/coresight/coresight-ctcu.h > index e9594c38dd91..71266371591b 100644 > --- a/drivers/hwtracing/coresight/coresight-ctcu.h > +++ b/drivers/hwtracing/coresight/coresight-ctcu.h > @@ -5,19 +5,27 @@ > > #ifndef _CORESIGHT_CTCU_H > #define _CORESIGHT_CTCU_H > + > +#include <linux/time.h> > #include "coresight-trace-id.h" > > /* Maximum number of supported ETR devices for a single CTCU. */ > #define ETR_MAX_NUM 2 > > +#define BYTE_CNTR_TIMEOUT (5 * HZ) > + > /** > * struct ctcu_etr_config > * @atid_offset: offset to the ATID0 Register. > - * @port_num: in-port number of CTCU device that connected to ETR. > + * @port_num: in-port number of the CTCU device that connected to ETR. > + * @irq_ctrl_offset: offset to the BYTECNTRVAL register. > + * @irq_name: IRQ name in dt node. > */ > struct ctcu_etr_config { > const u32 atid_offset; > const u32 port_num; > + const u32 irq_ctrl_offset; > + const char *irq_name; > }; > > struct ctcu_config { > @@ -25,15 +33,54 @@ struct ctcu_config { > int num_etr_config; > }; > > +/** > + * struct ctcu_byte_cntr > + * @enable: indicates that byte_cntr function is enabled or not. > + * @reading: indicates that its byte-cntr reading. > + * @reading_buf: indicates that byte-cntr is reading buffer. > + * @thresh_val: threshold to trigger a interruption. > + * @total_size: total size of transferred data. > + * @byte_cntr_irq: IRQ number. > + * @irq_cnt: IRQ count. > + * @irq_num: number of the byte_cntr IRQ for one session. the difference between byte_cntr_irg and irq_cnt is not clear. > + * @wq: workqueue of reading ETR data. > + * @read_work: work of reading ETR data. > + * @spin_lock: spinlock of byte cntr data. > + * the byte cntr is stopped. > + * @irq_ctrl_offset: offset to the BYTECNTVAL Register. > + * @irq_name: IRQ name in DT. > + */ > +struct ctcu_byte_cntr { > + bool enable; > + bool reading; This parameter is unused in this patch > + bool reading_buf; > + u32 thresh_val; > + u64 total_size; parameter unused in this patch > + int byte_cntr_irq; > + atomic_t irq_cnt; > + int irq_num; > + wait_queue_head_t wq; > + struct work_struct read_work; > + raw_spinlock_t spin_lock; > + u32 irq_ctrl_offset; > + const char *irq_name; > +}; > + > struct ctcu_drvdata { > void __iomem *base; > struct clk *apb_clk; > struct device *dev; > struct coresight_device *csdev; > + struct ctcu_byte_cntr byte_cntr_data[ETR_MAX_NUM]; > raw_spinlock_t spin_lock; > u32 atid_offset[ETR_MAX_NUM]; > /* refcnt for each traceid of each sink */ > u8 traceid_refcnt[ETR_MAX_NUM][CORESIGHT_TRACE_ID_RES_TOP]; > }; > > +/* Byte-cntr functions */ > +void ctcu_byte_cntr_start(struct coresight_device *csdev, struct coresight_path *path); > +void ctcu_byte_cntr_stop(struct coresight_device *csdev, struct coresight_path *path); > +void ctcu_byte_cntr_init(struct device *dev, struct ctcu_drvdata *drvdata, int port_num); > + > #endif > -- > 2.34.1 > -- Mike Leach Principal Engineer, ARM Ltd. Manchester Design Centre. UK

5 months, 1 week

Re: [PATCH v3 RESEND 00/10] coresight: ctcu: Enable byte-cntr function for TMC ETR

by Mike Leach

Hi I have had a look at a few of the patches. The buffer swap mechanism appears to be good. However there is a lot of byte-ctr code in the "core" tmc / etr source files. As much of this code as possible needs to be moved to the byte-cntr specifc source. I suggest having a helper function such as qcom_byte_ctr_in_use() to call from the core code, and if true then call back into the byte-cntr specific code to do the specialist functionality. One other possibility is to have a flag / enum in the tmc->drvdata structure to indicate a variant. - e.g. TMC_STD, TMC_QCOM_BYTE_CTR, set at initialisation stage to remove the need for checking the device tree every call. Regards Mike On Mon, 14 Jul 2025 at 07:31, Jie Gan <jie.gan(a)oss.qualcomm.com> wrote: > > The byte-cntr function provided by the CTCU device is used to count the > trace data entering the ETR. An interrupt is triggered if the data size > exceeds the threshold set in the BYTECNTRVAL register. The interrupt > handler counts the number of triggered interruptions. > > Based on this concept, the irq_cnt can be used to determine whether > the etr_buf is full. The ETR device will be disabled when the active > etr_buf is nearly full or a timeout occurs. The nearly full buffer will > be switched to background after synced. A new buffer will be picked from > the etr_buf_list, then restart the ETR device. > > The byte-cntr reading functions can access data from the synced and > deactivated buffer, transferring trace data from the etr_buf to userspace > without stopping the ETR device. > > The byte-cntr read operation has integrated with the file node tmc_etr, > for example: > /dev/tmc_etr0 > /dev/tmc_etr1 > > There are two scenarios for the tmc_etr file node with byte-cntr function: > 1. BYTECNTRVAL register is configured and byte-cntr is enabled -> byte-cntr read > 2. BYTECNTRVAL register is reset or byte-cntr is disabled -> original behavior > > Shell commands to enable byte-cntr reading for etr0: > echo 0x10000 > /sys/bus/coresight/devices/ctcu0/irq_val > echo 1 > /sys/bus/coresight/devices/tmc_etr0/enable_sink > echo 1 > /sys/bus/coresight/devices/etm0/enable_source > cat /dev/tmc_etr0 > > Reset the BYTECNTR register for etr0: > echo 0 > /sys/bus/coresight/devices/ctcu0/irq_val > > Changes in V3 resend: > 1. rebased on next-20250711. > Link to V3 - https://lore.kernel.org/all/20250624060438.7469-1-jie.gan@oss.qualcomm.com/ > > Changes in V3: > 1. The previous solution has been deprecated. > 2. Add a etr_buf_list to manage allcated etr buffers. > 3. Add a logic to switch buffer for ETR. > 4. Add read functions to read trace data from synced etr buffer. > Link to V2 - https://lore.kernel.org/all/20250410013330.3609482-1-jie.gan@oss.qualcomm.c… > > Changes in V2: > 1. Removed the independent file node /dev/byte_cntr. > 2. Integrated the byte-cntr's file operations with current ETR file > node. > 3. Optimized the driver code of the CTCU that associated with byte-cntr. > 4. Add kernel document for the export API tmc_etr_get_rwp_offset. > 5. Optimized the way to read the rwp_offset according to Mike's > suggestion. > 6. Removed the dependency of the dts patch. > Link to V1 - https://lore.kernel.org/all/20250310090407.2069489-1-quic_jiegan@quicinc.co… > > Jie Gan (10): > coresight: core: Refactoring ctcu_get_active_port and make it generic > coresight: core: add a new API to retrieve the helper device > dt-bindings: arm: add an interrupt property for Coresight CTCU > coresight: ctcu: enable byte-cntr for TMC ETR devices > coresight: tmc: add etr_buf_list to store allocated etr_buf > coresight: tmc: add create/delete functions for etr_buf_node > coresight: tmc: add prepare/unprepare functions for byte-cntr > coresight: tmc: add a switch buffer function for byte-cntr > coresight: tmc: add read function for byte-cntr > arm64: dts: qcom: sa8775p: Add interrupts to CTCU device > > .../testing/sysfs-bus-coresight-devices-ctcu | 5 + > .../bindings/arm/qcom,coresight-ctcu.yaml | 17 ++ > arch/arm64/boot/dts/qcom/sa8775p.dtsi | 5 + > drivers/hwtracing/coresight/Makefile | 2 +- > drivers/hwtracing/coresight/coresight-core.c | 54 ++++ > .../coresight/coresight-ctcu-byte-cntr.c | 102 +++++++ > .../hwtracing/coresight/coresight-ctcu-core.c | 113 ++++++-- > drivers/hwtracing/coresight/coresight-ctcu.h | 49 +++- > drivers/hwtracing/coresight/coresight-priv.h | 4 + > .../hwtracing/coresight/coresight-tmc-core.c | 70 ++++- > .../hwtracing/coresight/coresight-tmc-etr.c | 270 ++++++++++++++++++ > drivers/hwtracing/coresight/coresight-tmc.h | 29 ++ > 12 files changed, 688 insertions(+), 32 deletions(-) > create mode 100644 Documentation/ABI/testing/sysfs-bus-coresight-devices-ctcu > create mode 100644 drivers/hwtracing/coresight/coresight-ctcu-byte-cntr.c > > -- > 2.34.1 > -- Mike Leach Principal Engineer, ARM Ltd. Manchester Design Centre. UK

5 months, 1 week

Re: [PATCH v3 RESEND 09/10] coresight: tmc: add read function for byte-cntr

by Mike Leach

Hi, On Mon, 14 Jul 2025 at 07:32, Jie Gan <jie.gan(a)oss.qualcomm.com> wrote: > > The byte-cntr read function always reads trace data from the deactivated > and filled buffer which is already synced. The read function will fail > when the ETR cannot find a available buffer to receive trace data. > > The read function terminates when the path is disabled or interrupted by a > signal. > > Signed-off-by: Jie Gan <jie.gan(a)oss.qualcomm.com> > --- > .../hwtracing/coresight/coresight-tmc-core.c | 31 ++++++- > .../hwtracing/coresight/coresight-tmc-etr.c | 90 +++++++++++++++++++ > drivers/hwtracing/coresight/coresight-tmc.h | 3 + > 3 files changed, 120 insertions(+), 4 deletions(-) > > diff --git a/drivers/hwtracing/coresight/coresight-tmc-core.c b/drivers/hwtracing/coresight/coresight-tmc-core.c > index 354faeeddbb2..3ab25adc4e4d 100644 > --- a/drivers/hwtracing/coresight/coresight-tmc-core.c > +++ b/drivers/hwtracing/coresight/coresight-tmc-core.c > @@ -318,14 +318,18 @@ static int tmc_open(struct inode *inode, struct file *file) > return 0; > } > > -static ssize_t tmc_get_sysfs_trace(struct tmc_drvdata *drvdata, loff_t pos, size_t len, > - char **bufpp) > +static ssize_t tmc_get_sysfs_trace(struct tmc_drvdata *drvdata, > + struct ctcu_byte_cntr *byte_cntr_data, > + loff_t pos, size_t len, char **bufpp) Don't change "core" functionalilty to add in bytecntr parameters. Use helper functions to have a pattern such as: if (bytecntr_active()) call_byte_cntr_fn() else call_standard_fn() > { > switch (drvdata->config_type) { > case TMC_CONFIG_TYPE_ETB: > case TMC_CONFIG_TYPE_ETF: > return tmc_etb_get_sysfs_trace(drvdata, pos, len, bufpp); > case TMC_CONFIG_TYPE_ETR: > + if (byte_cntr_data && byte_cntr_data->thresh_val) > + return tmc_byte_cntr_get_data(drvdata, byte_cntr_data, len, bufpp); > + > return tmc_etr_get_sysfs_trace(drvdata, pos, len, bufpp); > } > > @@ -339,7 +343,21 @@ static ssize_t tmc_read(struct file *file, char __user *data, size_t len, > ssize_t actual; > struct tmc_drvdata *drvdata = container_of(file->private_data, > struct tmc_drvdata, miscdev); > - actual = tmc_get_sysfs_trace(drvdata, *ppos, len, &bufp); > + struct coresight_device *helper = coresight_get_helper(drvdata->csdev, > + CORESIGHT_DEV_SUBTYPE_HELPER_CTCU); > + struct ctcu_byte_cntr *byte_cntr_data = NULL; > + struct ctcu_drvdata *ctcu_drvdata = NULL; > + int port; > + > + if (helper) { > + port = coresight_get_port_helper(drvdata->csdev, helper); > + if (port >= 0) { > + ctcu_drvdata = dev_get_drvdata(helper->dev.parent); > + byte_cntr_data = &ctcu_drvdata->byte_cntr_data[port]; > + } > + } > + > + actual = tmc_get_sysfs_trace(drvdata, byte_cntr_data, *ppos, len, &bufp); > if (actual <= 0) > return 0; > > @@ -349,7 +367,12 @@ static ssize_t tmc_read(struct file *file, char __user *data, size_t len, > return -EFAULT; > } > > - *ppos += actual; > + if (byte_cntr_data && byte_cntr_data->thresh_val) { > + byte_cntr_data->total_size += actual; > + drvdata->reading_node->pos += actual; > + } else > + *ppos += actual; > + > dev_dbg(&drvdata->csdev->dev, "%zu bytes copied\n", actual); > > return actual; > diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtracing/coresight/coresight-tmc-etr.c > index 3e3e1b5e78ca..174411e76047 100644 > --- a/drivers/hwtracing/coresight/coresight-tmc-etr.c > +++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c > @@ -1163,6 +1163,10 @@ ssize_t tmc_etr_get_sysfs_trace(struct tmc_drvdata *drvdata, > ssize_t actual = len; > struct etr_buf *etr_buf = drvdata->sysfs_buf; > > + /* Reading the buffer from the buf_node if it exists*/ > + if (drvdata->reading_node) > + etr_buf = drvdata->reading_node->sysfs_buf; > + > if (pos + actual > etr_buf->len) > actual = etr_buf->len - pos; > if (actual <= 0) > @@ -1339,6 +1343,92 @@ static bool tmc_byte_cntr_switch_buffer(struct tmc_drvdata *drvdata, > return found_free_buf; > } > > +/* > + * tmc_byte_cntr_get_data() - reads data from the deactivated and filled buffer. > + * The byte-cntr reading work reads data from the deactivated and filled buffer. > + * The read operation waits for a buffer to become available, either filled or > + * upon timeout, and then reads trace data from the synced buffer. > + */ This entire function should be moved to one of the byte-cntr source files. > +ssize_t tmc_byte_cntr_get_data(struct tmc_drvdata *drvdata, > + struct ctcu_byte_cntr *byte_cntr_data, > + size_t len, char **bufpp) > +{ > + size_t thresh_val = byte_cntr_data->thresh_val; > + atomic_t *irq_cnt = &byte_cntr_data->irq_cnt; > + struct etr_buf *sysfs_buf = drvdata->sysfs_buf; > + struct device *dev = &drvdata->csdev->dev; > + struct etr_buf_node *nd, *next; > + ssize_t size = sysfs_buf->size; > + ssize_t actual; > + loff_t pos; > + int ret; > + > +wait_buffer: > + if (!byte_cntr_data->reading_buf) { > + ret = wait_event_interruptible_timeout(byte_cntr_data->wq, > + ((atomic_read(irq_cnt) + 1) * thresh_val >= size) || > + !byte_cntr_data->enable, > + BYTE_CNTR_TIMEOUT); > + if (ret < 0) > + return ret; > + /* > + * The current etr_buf is almost full or timeout is triggered, > + * so switch the buffer and mark the switched buffer as reading. > + */ > + if (byte_cntr_data->enable) { > + if (!tmc_byte_cntr_switch_buffer(drvdata, byte_cntr_data)) { > + dev_err(dev, "Switch buffer failed for byte-cntr\n"); > + return -EINVAL; > + } > + > + byte_cntr_data->reading_buf = true; > + } else { > + if (!drvdata->reading_node) { > + list_for_each_entry_safe(nd, next, &drvdata->etr_buf_list, node) { > + if (nd->sysfs_buf == sysfs_buf) { > + nd->pos = 0; > + drvdata->reading_node = nd; > + break; > + } > + } > + } > + > + pos = drvdata->reading_node->pos; > + actual = tmc_etr_get_sysfs_trace(drvdata, pos, len, bufpp); > + if (actual > 0) > + return actual; > + > + drvdata->reading_node = NULL; > + > + /* Exit byte-cntr reading */ > + return -EINVAL; > + } > + } > + > + /* Check the status of current etr_buf*/ > + if ((atomic_read(irq_cnt) + 1) * thresh_val >= size) > + /* > + * Unlikely to find a free buffer to switch, so just disable > + * the ETR for a while. > + */ > + if (!tmc_byte_cntr_switch_buffer(drvdata, byte_cntr_data)) > + dev_info(dev, "No available buffer to store data, disable ETR\n"); > + > + pos = drvdata->reading_node->pos; > + actual = tmc_etr_get_sysfs_trace(drvdata, pos, len, bufpp); > + if (actual == 0) { > + /* Reading work for marked buffer has finished, reset flags */ > + drvdata->reading_node->reading = false; > + byte_cntr_data->reading_buf = false; > + drvdata->reading_node = NULL; > + > + /* Nothing in the buffer, wait for next buffer to be filled */ > + goto wait_buffer; > + } > + > + return actual; > +} > + > static int tmc_enable_etr_sink_sysfs(struct coresight_device *csdev) > { > int ret = 0; > diff --git a/drivers/hwtracing/coresight/coresight-tmc.h b/drivers/hwtracing/coresight/coresight-tmc.h > index 1dbba0bc50a3..4136ec5ecaf7 100644 > --- a/drivers/hwtracing/coresight/coresight-tmc.h > +++ b/drivers/hwtracing/coresight/coresight-tmc.h > @@ -364,6 +364,9 @@ int tmc_read_prepare_byte_cntr(struct tmc_drvdata *drvdata, > struct ctcu_byte_cntr *byte_cntr_data); > int tmc_read_unprepare_byte_cntr(struct tmc_drvdata *drvdata, > struct ctcu_byte_cntr *byte_cntr_data); Declare this in a byte_cntr header file, not here. > +ssize_t tmc_byte_cntr_get_data(struct tmc_drvdata *drvdata, > + struct ctcu_byte_cntr *byte_cntr_data, > + size_t len, char **bufpp); > > #define TMC_REG_PAIR(name, lo_off, hi_off) \ > static inline u64 \ > -- > 2.34.1 > -- Mike Leach Principal Engineer, ARM Ltd. Manchester Design Centre. UK

5 months, 1 week

Re: [PATCH v3 RESEND 08/10] coresight: tmc: add a switch buffer function for byte-cntr

by Mike Leach

Hi, This buffer swap code looks OK in principle. The ETR is stopped, memory synced and set to be read. See other comments inline. On Mon, 14 Jul 2025 at 07:31, Jie Gan <jie.gan(a)oss.qualcomm.com> wrote: > > Switching the sysfs_buf when current buffer is full or the timeout is > triggered and resets rrp and rwp registers after switched the buffer. > Disable the ETR device if it cannot find an available buffer to switch. > > Signed-off-by: Jie Gan <jie.gan(a)oss.qualcomm.com> > --- > .../hwtracing/coresight/coresight-tmc-etr.c | 52 +++++++++++++++++++ > 1 file changed, 52 insertions(+) > > diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtracing/coresight/coresight-tmc-etr.c > index 2b73bd8074bb..3e3e1b5e78ca 100644 > --- a/drivers/hwtracing/coresight/coresight-tmc-etr.c > +++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c > @@ -1287,6 +1287,58 @@ static struct etr_buf *tmc_etr_get_sysfs_buffer(struct coresight_device *csdev) > return ret ? ERR_PTR(ret) : drvdata->sysfs_buf; > } > > +static bool tmc_byte_cntr_switch_buffer(struct tmc_drvdata *drvdata, > + struct ctcu_byte_cntr *byte_cntr_data) > +{ This entire function should be in one of the byte_cntr source files, not in the main etr files. Please keep byte cntr code separate as far as possible > + struct etr_buf_node *nd, *next, *curr_node, *picked_node; > + struct etr_buf *curr_buf = drvdata->sysfs_buf; > + bool found_free_buf = false; > + > + if (WARN_ON(!drvdata || !byte_cntr_data)) > + return found_free_buf; > + > + /* Stop the ETR before we start the switching process */ > + if (coresight_get_mode(drvdata->csdev) == CS_MODE_SYSFS) Can this function be called if the mode is not CS_MODE_SYSFS? > + __tmc_etr_disable_hw(drvdata); > + > + list_for_each_entry_safe(nd, next, &drvdata->etr_buf_list, node) { > + /* curr_buf is free for next round */ > + if (nd->sysfs_buf == curr_buf) { > + nd->is_free = true; > + curr_node = nd; > + } > + > + if (!found_free_buf && nd->is_free && nd->sysfs_buf != curr_buf) { > + if (nd->reading) > + continue; > + > + picked_node = nd; > + found_free_buf = true; > + } > + } > + > + if (found_free_buf) { > + curr_node->reading = true; > + curr_node->pos = 0; > + drvdata->reading_node = curr_node; > + drvdata->sysfs_buf = picked_node->sysfs_buf; > + drvdata->etr_buf = picked_node->sysfs_buf; > + picked_node->is_free = false; > + /* Reset irq_cnt for next etr_buf */ > + atomic_set(&byte_cntr_data->irq_cnt, 0); > + /* Reset rrp and rwp when the system has switched the buffer*/ > + CS_UNLOCK(drvdata->base); > + tmc_write_rrp(drvdata, 0); > + tmc_write_rwp(drvdata, 0); This cannot possibly be correct. RWP / RRP are pointers into the system memory where the ETR stores data. > + CS_LOCK(drvdata->base); > + /* Restart the ETR when we find a free buffer */ > + if (coresight_get_mode(drvdata->csdev) == CS_MODE_SYSFS) > + __tmc_etr_enable_hw(drvdata); What happens if the ETR is not restarted? Using __tmc_etr_disable_hw() is correct for this use case, but if you do not restart then the extra shutdown that would ordinarily happen in tmc_etr_disable_hw() does not occur. How is this handled in the rest of the update? > + } > + > + return found_free_buf; > +} > + > static int tmc_enable_etr_sink_sysfs(struct coresight_device *csdev) > { > int ret = 0; > -- > 2.34.1 > Regards Mike -- Mike Leach Principal Engineer, ARM Ltd. Manchester Design Centre. UK

5 months, 1 week

Re: [PATCH v6 0/7] Provides support for Trigger Generation Unit

by Mike Leach

Hi, On Wed, 9 Jul 2025 at 11:41, songchai <songchai(a)qti.qualcomm.com> wrote: > > From: Songwei Chai <quic_songchai(a)quicinc.com> > > Provide support for the TGU (Trigger Generation Unit), which can be > utilized to sense a plurality of signals and create a trigger into > the CTI or generate interrupts to processors once the input signal > meets the conditions. We can treat the TGU’s workflow as a flowsheet, > it has some “steps” regions for customization. In each step region, > we can set the signals that we want with priority in priority_group, set > the conditions in each step via condition_decode, and set the resultant > action by condition_select. Meanwhile, some TGUs (not all) also provide > timer/counter functionality. Based on the characteristics described > above, we consider the TGU as a helper in the CoreSight subsystem. > Its master device is the TPDM, which can transmit signals from other > subsystems, and we reuse the existing ports mechanism to link the TPDM to > the connected TGU. > > Here is a detailed example to explain how to use the TGU: > > In this example, the TGU is configured to use 2 conditions, 2 steps, and > the timer. The goal is to look for one of two patterns which are generated > from TPDM, giving priority to one, and then generate a trigger once the > timer reaches a certain value. In other words, two conditions are used > for the first step to look for the two patterns, where the one with the > highest priority is used in the first condition. Then, in the second step, > the timer is enabled and set to be compared to the given value at each > clock cycle. These steps are better shown below. > > |-----------------| > | | > | TPDM | > | | > |-----------------| > | > | > --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- ------ > | | | > | | |--------------------| | > | |---- ---> | | Go to next steps | | > | | | |--- ---> | Enable timer | | > | | v | | | | > | | |-----------------| | |--------------------| | > | | | | Yes | | | > | | | inputs==0xB | ----->| | <-------- | > | | | | | | No | | > | No | |-----------------| | v | | > | | | | |-----------------| | | > | | | | | | | | > | | | | | timer>=3 |-- | > | | v | | | | > | | |-----------------| | |-----------------| | > | | | | Yes | | | > | |--- | inputs==0xA | ----->| | Yes | > | | | | | > | |-----------------| v | > | |-----------------| | > | | | | > | | Trigger | | > | | | | > | |-----------------| | > | TGU | | > |--- --- --- --- --- --- --- --- --- --- --- --- --- --- |--- --- -- | > | > v > |-----------------| > |The controllers | > |which will use | > |triggers further | > |-----------------| > > steps: > 1. Reset TGU /*it will disable tgu and reset dataset*/ > - echo 1 > /sys/bus/coresight/devices/<tgu-name>/reset_tgu > > 2. Set the pattern match for priority0 to 0xA = 0b1010 and for > priority 1 to 0xB = 0b1011. > - echo 0x11113232 > /sys/bus/coresight/devices/<tgu-name>/step0_priority0/reg0 > - echo 0x11113233 > /sys/bus/coresight/devices/<tgu-name>/step0_priority1/reg0 > > Note: > Bit distribution diagram for each priority register > |-------------------------------------------------------------------| > | Bits | Field Nam | Description | > |-------------------------------------------------------------------| > | | | 00 = bypass for OR output | > | 29:28 | SEL_BIT7_TYPE2 | 01 = bypass for AND output | > | | | 10 = sense input '0' is true| > | | | 11 = sense input '1' is true| > |-------------------------------------------------------------------| > | | | 00 = bypass for OR output | > | 25:24 | SEL_BIT6_TYPE2 | 01 = bypass for AND output | > | | | 10 = sense input '0' is true| > | | | 11 = sense input '1' is true| > |-------------------------------------------------------------------| > | | | 00 = bypass for OR output | > | 21:20 | SEL_BIT5_TYPE2 | 01 = bypass for AND output | > | | | 10 = sense input '0' is true| > | | | 11 = sense input '1' is true| > |-------------------------------------------------------------------| > | | | 00 = bypass for OR output | > | 17:16 | SEL_BIT4_TYPE2 | 01 = bypass for AND output | > | | | 10 = sense input '0' is true| > | | | 11 = sense input '1' is true| > |-------------------------------------------------------------------| > | | | 00 = bypass for OR output | > | 13:12 | SEL_BIT3_TYPE2 | 01 = bypass for AND output | > | | | 10 = sense input '0' is true| > | | | 11 = sense input '1' is true| > |-------------------------------------------------------------------| > | | | 00 = bypass for OR output | > | 9:8 | SEL_BIT2_TYPE2 | 01 = bypass for AND output | > | | | 10 = sense input '0' is true| > | | | 11 = sense input '1' is true| > |-------------------------------------------------------------------| > | | | 00 = bypass for OR output | > | 5:4 | SEL_BIT1_TYPE2 | 01 = bypass for AND output | > | | | 10 = sense input '0' is true| > | | | 11 = sense input '1' is true| > |-------------------------------------------------------------------| > | | | 00 = bypass for OR output | > | 1:0 | SEL_BIT0_TYPE2 | 01 = bypass for AND output | > | | | 10 = sense input '0' is true| > | | | 11 = sense input '1' is true| > |-------------------------------------------------------------------| > These bits are used to identify the signals we want to sense, with > a maximum signal number of 140. For example, to sense the signal > 0xA (binary 1010), we set the value of bits 0 to 13 to 3232, which > represents 1010. The remaining bits are set to 1, as we want to use > AND gate to summarize all the signals we want to sense here. For > rising or falling edge detection of any input to the priority, set > the remaining bits to 0 to use an OR gate. > > 3. look for the pattern for priority_i i=0,1. > - echo 0x3 > /sys/bus/coresight/devices/<tgu-name>/step0_condition_decode/reg0 > - echo 0x30 > /sys/bus/coresight/devices/<tgu-name>/step0_condition_decode/reg1 > > |-------------------------------------------------------------------------------| > | Bits | Field Nam | Description | > |-------------------------------------------------------------------------------| > | | |For each decoded condition, this | > | 24 | NOT |inverts the output. If the condition | > | | |decodes to true, and the NOT field | > | | |is '1', then the output is NOT true. | > |-------------------------------------------------------------------------------| > | | |When '1' the output from the associated| > | 21 | BC0_COMP_ACTIVE |comparator will be actively included in| > | | |the decoding of this particular | > | | |condition. | > |-------------------------------------------------------------------------------| > | | |When '1' the output from the associated| > | | |comparator will need to be 1 to affect | > | 20 | BC0_COMP_HIGH |the decoding of this condition. | > | | |Conversely, a '0' here requires a '0' | > | | |from the comparator | > |-------------------------------------------------------------------------------| > | | |When '1' the output from the associated| > | 17 | |comparator will be actively included in| > | | TC0_COMP_ACTIVE |the decoding of this particular | > | | |condition. | > |-------------------------------------------------------------------------------| > | | |When '1' the output from the associated| > | | |comparator will need to be 1 to affect | > | 16 | TC0_COMP_HIGH |the decoding of this particular | > | | |condition.Conversely, a 0 here | > | | |requires a '0' from the comparator | > |-------------------------------------------------------------------------------| > | | |When '1' the output from Priority_n | > | | |OR logic will be actively | > | 4n+3 | Priority_n_OR_ACTIVE|included in the decoding of | > | | (n=0,1,2,3) |this particular condition. | > | | | | > |-------------------------------------------------------------------------------| > | | |When '1' the output from Priority_n | > | | |will need to be '1' to affect the | > | 4n+2 | Priority_n_OR_HIGH |decoding of this particular | > | | (n=0,1,2,3) |condition. Conversely, a '0' here | > | | |requires a '0' from Priority_n OR logic| > |-------------------------------------------------------------------------------| > | | |When '1' the output from Priority_n | > | | |AND logic will be actively | > | 4n+1 |Priority_n_AND_ACTIVE|included in the decoding of this | > | | (n=0,1,2,3) |particular condition. | > | | | | > |-------------------------------------------------------------------------------| > | | |When '1' the output from Priority_n | > | | |AND logic will need to be '1' to | > | 4n | Priority_n_AND_HIGH |affect the decoding of this | > | | (n=0,1,2,3) |particular condition. Conversely, | > | | |a '0' here requires a '0' from | > | | |Priority_n AND logic. | > |-------------------------------------------------------------------------------| > Since we use `priority_0` and `priority_1` with an AND output in step 2, we set `0x3` > and `0x30` here to activate them. > > 4. Set NEXT_STEP = 1 and TC0_ENABLE = 1 so that when the conditions > are met then the next step will be step 1 and the timer will be enabled. > - echo 0x20008 > /sys/bus/coresight/devices/<tgu-name>/step0_condition_select/reg0 > - echo 0x20008 > /sys/bus/coresight/devices/<tgu-name>/step0_condition_select/reg1 > > |-----------------------------------------------------------------------------| > | Bits | Field Nam | Description | > |-----------------------------------------------------------------------------| > | | |This field defines the next step the | > | 18:17 | NEXT_STEP |TGU will 'goto' for the associated | > | | |Condition and Step. | > |-----------------------------------------------------------------------------| > | | |For each possible output trigger | > | 13 | TRIGGER |available, set a '1' if you want | > | | |the trigger to go active for the | > | | |associated condition and Step. | > |-----------------------------------------------------------------------------| > | | |This will cause BC0 to increment if the| > | 9 | BC0_INC |associated Condition is decoded for | > | | |this step. | > |-----------------------------------------------------------------------------| > | | |This will cause BC0 to decrement if the| > | 8 | BC0_DEC |associated Condition is decoded for | > | | |this step. | > |-----------------------------------------------------------------------------| > | | |This will clear BC0 count value to 0 if| > | 7 | BC0_CLEAR |the associated Condition is decoded | > | | |for this step. | > |-----------------------------------------------------------------------------| > | | |This will cause TC0 to increment until | > | 3 | TC0_ENABLE |paused or cleared if the associated | > | | |Condition is decoded for this step. | > |-----------------------------------------------------------------------------| > | | |This will cause TC0 to pause until | > | 2 | TC0_PAUSE |enabled if the associated Condition | > | | |is decoded for this step. | > |-----------------------------------------------------------------------------| > | | |This will clear TC0 count value to 0 | > | 1 | TC0_CLEAR |if the associated Condition is | > | | |decoded for this step. | > |-----------------------------------------------------------------------------| > | | |This will set the done signal to the | > | 0 | DONE |TGU FSM if the associated Condition | > | | |is decoded for this step. | > |-----------------------------------------------------------------------------| > Based on the distribution diagram, we set `0x20008` for `priority0` and `priority1` to > achieve "jump to step 1 and enable TC0" once the signal is sensed. > > 5. activate the timer comparison for this step. > - echo 0x30000 > /sys/bus/coresight/devices/<tgu-name>/step1_condition_decode/reg0 > > |-------------------------------------------------------------------------------| > | | |When '1' the output from the associated| > | 17 | |comparator will be actively included in| > | | TC0_COMP_ACTIVE |the decoding of this particular | > | | |condition. | > |-------------------------------------------------------------------------------| > | | |When '1' the output from the associated| > | | |comparator will need to be 1 to affect | > | 16 | TC0_COMP_HIGH |the decoding of this particular | > | | |condition.Conversely, a 0 here | > | | |requires a '0' from the comparator | > |-------------------------------------------------------------------------------| > Accroding to the decode distribution diagram , we give 0x30000 here to set 16th&17th bit > to enable timer comparison. > > 6. Set the NEXT_STEP = 0 and TC0_PAUSE = 1 and TC0_CLEAR = 1 once the timer > has reached the given value. > - echo 0x6 > /sys/bus/coresight/devices/<tgu-name>/step1_condition_select/reg0 > > 7. Enable Trigger 0 for TGU when the condition 0 is met in step1, > i.e. when the timer reaches 3. > - echo 0x2000 > /sys/bus/coresight/devices/<tgu-name>/step1_condition_select/default > > Note: > 1. 'default' register allows for establishing the resultant action for > the default condition > > 2. Trigger:For each possible output trigger available from > the Design document, there are three triggers: interrupts, CTI, > and Cross-TGU mapping.All three triggers can occur, but > the choice of which trigger to use depends on the user's > needs. > > 8. Compare the timer to 3 in step 1. > - echo 0x3 > /sys/bus/coresight/devices/<tgu-name>/step1_timer/reg0 > > 9. enale tgu > - echo 1 > /sys/bus/coresight/devices/<tgu-name>/enable_tgu > --- > Link to V5: https://lore.kernel.org/all/20250529081949.26493-1-quic_songchai@quicinc.co… > > Changes in V6: > - Replace spinlock with guard(spinlock) in tgu_enable. > - Remove redundant blank line. > - Update publish date and contact member's name in "sysfs-bus-coresight-devices-tgu". > --- > Link to V4: https://patchwork.kernel.org/project/linux-arm-msm/cover/20250423101054.954… > > Changes in V5: > - Update publish date and kernel_version in "sysfs-bus-coresight-devices-tgu" > --- > Link to V3: https://lore.kernel.org/all/20250227092640.2666894-1-quic_songchai@quicinc.… > > Changes in V4: > - Add changlog in coverletter. > - Correct 'year' in Copyright in patch1. > - Correct port mechansim description in patch1. > - Remove 'tgu-steps','tgu-regs','tgu-conditions','tgu-timer-counters' from dt-binding > and set them through reading DEVID register as per Mike's suggestion. > - Modify tgu_disable func to make it have single return point in patch2 as per > Mike's suggestion. > - Use sysfs_emit in enable_tgu_show func in ptach2. > - Remove redundant judgement in enable_tgu_store in patch2. > - Correct typo in description in patch3. > - Set default ret as SYSFS_GROUP_INVISIBLE, and returnret at end in pacth3 as > per Mike's suggestion. > - Remove tgu_dataset_ro definition in patch3 > - Use #define constants with explanations of what they are rather than > arbitrary magic numbers in patch3 and patch4. > - Check -EINVAL before using 'calculate_array_location()' in array in patch4. > - Add 'default' in 'tgu_dataset_show''s switch part in patch4. > - Document the value needed to initiate the reset in pacth7. > - Check "value" in 'reset_tgu_store' and bail out with an error code if 0 in patch7. > - Remove dev_dbg in 'reset_tgu_store' in patch7. > --- > Link to V2: https://lore.kernel.org/all/20241010073917.16023-1-quic_songchai@quicinc.co… > > Changes in V3: > - Correct typo and format in dt-binding in patch1 > - Rebase to the latest kernel version > --- > Link to V1: https://lore.kernel.org/all/20240830092311.14400-1-quic_songchai@quicinc.co… > > Changes in V2: > - Use real name instead of login name, > - Correct typo and format in dt-binding and code. > - Bring order in tgu_prob(declarations with and without assignments) as per > Krzysztof's suggestion. > - Add module device table in patch2. > - Set const for tgu_common_grp and tgu_ids in patch2. > - Initialize 'data' in tgu_ids to fix the warning in pacth2. > --- > > Songwei Chai (7): > dt-bindings: arm: Add support for Coresight TGU trace > coresight: Add coresight TGU driver > coresight-tgu: Add signal priority support > coresight-tgu: Add TGU decode support > coresight-tgu: add support to configure next action > coresight-tgu: add timer/counter functionality for TGU > coresight-tgu: add reset node to initialize > > .../testing/sysfs-bus-coresight-devices-tgu | 51 ++ > .../bindings/arm/qcom,coresight-tgu.yaml | 92 +++ > drivers/hwtracing/coresight/Kconfig | 11 + > drivers/hwtracing/coresight/Makefile | 1 + > drivers/hwtracing/coresight/coresight-tgu.c | 776 ++++++++++++++++++ > drivers/hwtracing/coresight/coresight-tgu.h | 255 ++++++ > 6 files changed, 1186 insertions(+) > create mode 100644 Documentation/ABI/testing/sysfs-bus-coresight-devices-tgu > create mode 100644 Documentation/devicetree/bindings/arm/qcom,coresight-tgu.yaml > create mode 100644 drivers/hwtracing/coresight/coresight-tgu.c > create mode 100644 drivers/hwtracing/coresight/coresight-tgu.h > > As per the discussion here in v3 of this patchset https://lists.infradead.org/pipermail/linux-arm-kernel/2025-March/1012896.h… this component is primarily a part of the qualcom proprietary QPMDA subsystem, and is capable of operating independently from the CoreSight hardware trace generation system. The only link to Coresight is via the trigger input to CTI component(s). CTI triggers can either be part of the ARM architected or recommended connections between Coresight infrastructure from the coresight specs and TRM documents, or platform specific triggers from components external to coresight. For example on the Juno board a trigger from the PL011 serial port is input to one of the system CTIs on the board. Having Coresight management registers does not necessarily mean that the component should be maintained under the hwtracing/coresight. Some ARM Corelink interconnect components have the capability to generate ATB trace into the coresight subsystem, and have some of the coresight management registers. However, I would not expect the drivers for these components to appear in hwtracing/coresight. As such this component could probably be better managed and maintained as part of the /drivers/soc/qcom or similar area. The only changes to the Coresight infrastructure you should need to get this component connected, is to alter the CTI declaration in board device tree to add the incoming trigger as per the CTI bindings. Regards Mike -- Mike Leach Principal Engineer, ARM Ltd. Manchester Design Centre. UK

5 months, 1 week

Re: [PATCH next] coresight: Fix a NULL vs IS_ERR() bug in probe

by Suzuki K Poulose

On Wed, 16 Jul 2025 14:38:30 -0500, Dan Carpenter wrote: > The devm_ioremap_resource() function returns error pointers on error. > It never returns NULL. Update the error checking to match. > > Applied, thanks! [1/1] coresight: Fix a NULL vs IS_ERR() bug in probe https://git.kernel.org/coresight/c/f59b9437ac95 Best regards, -- Suzuki K Poulose <suzuki.poulose(a)arm.com>

5 months, 1 week

Re: [PATCH v4] coresight: Replace scnprintf() with sysfs_emit() in sysfs show functions

by Suzuki K Poulose

On 19/07/2025 23:45, Chelsy Ratnawat wrote: > Documentation/filesystems/sysfs.rst mentions that show() should only > use sysfs_emit() or sysfs_emit_at() when formating the value to be > returned to user space. So replace scnprintf() with sysfs_emit(). > > Signed-off-by: Chelsy Ratnawat <chelsyratnawat2001(a)gmail.com> > --- > Changes in v4: > - Applied changes to 5 more files to replace sprintf/scnprintf with > sysfs_emit() and sysfs_emit_at() Please could you rebase this on coresight tree "next" branch ? There are conflicts. https://git.kernel.org/pub/scm/linux/kernel/git/coresight/linux.git/log/?h=… Suzuki

5 months, 1 week

[PATCH v2 0/3] Coresight TMC-ETR some bugfixes and cleanups

by Junhao He

This patchset builds upon Yicong's previous patches [1]. Introducing fix two race issues found by using TMC-ETR and CATU, Two cleanups found when debugging the issues. [1] https://lore.kernel.org/linux-arm-kernel/20241202092419.11777-1-yangyicong@… --- Changes in v2: - Updated the commit of patch2. - Rebase to v6.16-rc1 Junhao He (1): coresight: tmc: refactor the tmc-etr mode setting to avoid race conditions Yicong Yang (2): coresight: tmc: Add missing doc of tmc_drvdata::reading coresight: tmc: Decouple the perf buffer allocation from sysfs mode .../hwtracing/coresight/coresight-tmc-etr.c | 102 +++++++++--------- drivers/hwtracing/coresight/coresight-tmc.h | 1 + 2 files changed, 53 insertions(+), 50 deletions(-) -- 2.33.0

5 months, 1 week

[PATCH v3 0/6] Refactoring finding CPU phandles in DT

by Alireza Sanaee

This series refactor the way CPU IDs are retrieved from the device tree. Usually, there is a for loop that goes over every single CPU that can be avoided. This also reduces the amount of NULL pointer checks in drivers. I have abstracted away that loop and introduced a new function (of_cpu_node_to_id) for this. This patchset is a subset of [1], where I removed content and patches relevant to hyper-threaded cores for DT. Based on the discussion, the code refactor is still useful, hence this patchset. [1] https://lore.kernel.org/all/20250512080715.82-1-alireza.sanaee@huawei.co Changes since v2: - Addressed Jonathan Cameron's comments. - Added reviewed-by tags. - Added a new commit where I suggest simplfing the code in arch_topology.c to remove the use of cpu_node on failure path. - Improve documentation. - Caught a bug in patch 1. - Commit message fixed for patch 2. Changes since v1: - Rebased on top of the latest mainline. - Addressed Krzysztof Kozlowski's comments -- Hopefully :-) - Addressed Jonathan Cameron's comments. Alireza Sanaee (6): of: add infra for finding CPU id from phandle arch_topology: drop the use of cpu_node in the pr_info arch_topology: update CPU map to use of_cpu_phandle_to_id coresight: cti: Use of_cpu_phandle_to_id for grabbing CPU id coresight: Use of_cpu_phandle_to_id for grabbing CPU ID perf/arm-dsu: refactor cpu id retrieval via new API of_cpu_phandle_to_id drivers/base/arch_topology.c | 22 ++++----- .../coresight/coresight-cti-platform.c | 13 +---- .../hwtracing/coresight/coresight-platform.c | 15 +----- drivers/of/cpu.c | 49 +++++++++++++++++++ drivers/perf/arm_dsu_pmu.c | 7 +-- include/linux/of.h | 9 ++++ 6 files changed, 72 insertions(+), 43 deletions(-) -- 2.43.0

5 months, 1 week

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