CoreSight

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2601 discussions

[PATCH v2 0/3] coresight-tnoc: Add support for Interconnect TNOC

by Yuanfang Zhang

This patch series adds support for the Qualcomm CoreSight Interconnect TNOC (Trace Network On Chip) block, which acts as a CoreSight graph link forwarding trace data from subsystems to the Aggregator TNOC. Unlike the Aggregator TNOC, this block does not support aggregation or ATID assignment. Signed-off-by: Yuanfang Zhang <yuanfang.zhang(a)oss.qualcomm.com> --- Changes in v2: - Refactor the dt-binding file. - Change "atid" type from u32 to int, set it as "-EOPNOTSUPP" for non-AMBA device. - Link to v1: https://lore.kernel.org/r/20250815-itnoc-v1-0-62c8e4f7ad32@oss.qualcomm.com --- Yuanfang Zhang (3): dt-bindings: arm: qcom: Add Coresight Interconnect TNOC coresight-tnoc: add platform driver to support Interconnect TNOC coresight-tnoc: Add runtime PM support for Interconnect TNOC .../bindings/arm/qcom,coresight-itnoc.yaml | 96 ++++++++++++++ drivers/hwtracing/coresight/coresight-tnoc.c | 147 ++++++++++++++++++--- 2 files changed, 226 insertions(+), 17 deletions(-) --- base-commit: 2b52cf338d39d684a1c6af298e8204902c026aca change-id: 20250815-itnoc-460273d1b80c Best regards, -- Yuanfang Zhang <yuanfang.zhang(a)oss.qualcomm.com>

4 months, 2 weeks

[PATCH 0/3] coresight-tnoc: Add support for Interconnect TNOC

by Yuanfang Zhang

This patch series adds support for the Qualcomm CoreSight Interconnect TNOC (Trace Network On Chip) block, which acts as a CoreSight graph link forwarding trace data from subsystems to the Aggregator TNOC. Unlike the Aggregator TNOC, this block does not support aggregation or ATID assignment. Signed-off-by: Yuanfang Zhang <yuanfang.zhang(a)oss.qualcomm.com> --- Yuanfang Zhang (3): dt-bindings: arm: qcom: Add Coresight Interconnect TNOC coresight-tnoc: add platform driver to support Interconnect TNOC coresight-tnoc: Add runtime PM support for Interconnect TNOC .../bindings/arm/qcom,coresight-itnoc.yaml | 108 +++++++++++++ drivers/hwtracing/coresight/coresight-tnoc.c | 179 +++++++++++++++------ 2 files changed, 240 insertions(+), 47 deletions(-) --- base-commit: 2b52cf338d39d684a1c6af298e8204902c026aca change-id: 20250815-itnoc-460273d1b80c Best regards, -- Yuanfang Zhang <yuanfang.zhang(a)oss.qualcomm.com>

4 months, 2 weeks

Re: [PATCH 1/3] dt-bindings: arm: qcom: Add Coresight Interconnect TNOC

by yuanfang zhang

On 8/16/2025 4:33 PM, Krzysztof Kozlowski wrote: > On 15/08/2025 15:18, Yuanfang Zhang wrote: >> Add device tree binding for Qualcomm Coresight Interconnect Trace >> Netwrok On Chip (ITNOC). This TNOC acts as a CoreSight >> graph link that forwards trace data from a subsystem to the >> Aggregator TNOC, without aggregation or ATID functionality. >> >> Signed-off-by: Yuanfang Zhang <yuanfang.zhang(a)oss.qualcomm.com> >> --- >> .../bindings/arm/qcom,coresight-itnoc.yaml | 108 +++++++++++++++++++++ >> 1 file changed, 108 insertions(+) >> >> diff --git a/Documentation/devicetree/bindings/arm/qcom,coresight-itnoc.yaml b/Documentation/devicetree/bindings/arm/qcom,coresight-itnoc.yaml >> new file mode 100644 >> index 0000000000000000000000000000000000000000..fd224e07ce68918b453210763aacda585d5a5ca2 >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/arm/qcom,coresight-itnoc.yaml >> @@ -0,0 +1,108 @@ >> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause >> +%YAML 1.2 >> +--- >> +$id: http://devicetree.org/schemas/arm/qcom,coresight-itnoc.yaml# >> +$schema: http://devicetree.org/meta-schemas/core.yaml# >> + >> +title: Qualcomm Interconnect Trace Network On Chip - ITNOC >> + >> +maintainers: >> + - Yuanfang Zhang <yuanfang.zhang(a)oss.qualcomm.com> >> + >> +description: | > Do not need '|' unless you need to preserve formatting. sure, will remove it. >> + The Interconnect TNOC is a CoreSight graph link that forwards trace data >> + from a subsystem to the Aggregator TNOC. Compared to Aggregator TNOC, it >> + does not have aggregation and ATID functionality. >> + >> +select: >> + properties: >> + compatible: >> + contains: >> + enum: >> + - qcom,coresight-itnoc >> + required: >> + - compatible > Why all this? Drop sure. >> + >> +properties: >> + $nodename: >> + pattern: "^tnoc(@[0-9a-f]+)?$" > Why are you requiring a non-generic name? will update the name. >> + >> + compatible: >> + items: > No need for items sure, will remove it. >> + - const: qcom,coresight-itnoc >> + >> + reg: >> + maxItems: 1 >> + description: Base address and size of the ITNOC registers. > Drop, redundant sure, will remove it. >> + >> + clock-names: >> + items: >> + - const: apb > Drop clock-names, obvious. Also, odd order - names are never before > actual property. sure, will update the order. >> + >> + clocks: >> + maxItems: 1 >> + >> + in-ports: >> + $ref: /schemas/graph.yaml#/properties/ports >> + >> + properties: >> + '#address-cells': >> + const: 1 >> + '#size-cells': >> + const: 0 >> + >> + patternProperties: >> + '^port(@[0-9a-f]{1,2})?$': > Why do you have here 255 ports? It supports a maximum of 256 input ports, so it is limited to 0-255. >> + description: Input connections from CoreSight Trace Bus >> + $ref: /schemas/graph.yaml#/properties/port >> + additionalProperties: false > This goes after $ref sure, will update. >> + >> + out-ports: >> + $ref: /schemas/graph.yaml#/properties/ports >> + >> + properties: >> + port: >> + description: out connections to aggregator TNOC >> + $ref: /schemas/graph.yaml#/properties/port >> + additionalProperties: false > This goes after ref sure, will update. >> + >> +required: >> + - compatible >> + - reg >> + - clocks >> + - clock-names > And here different order... Be consistent. See also DTS coding style. sure, will update the order. >> + - in-ports >> + - out-ports >> + >> +additionalProperties: false >> + > > > Best regards, > Krzysztof

4 months, 2 weeks

Re: [PATCH v2] coresight-etm4x: Conditionally access register TRCEXTINSELR

by James Clark

On 12/08/2025 9:24 am, Yuanfang Zhang wrote: > The TRCEXTINSELR is only implemented if TRCIDR5.NUMEXTINSEL > 0. > To avoid invalid accesses, introduce a check on numextinsel > (derived from TRCIDR5[11:9]) before reading or writing to this register. > > Fixes: f5bd523690d2 ("coresight: etm4x: Convert all register accesses") This tag isn't right. Although this is where the register accesses were last touched, the root issue was present from the introduction of the driver. > Signed-off-by: Yuanfang Zhang <yuanfang.zhang(a)oss.qualcomm.com> > --- > Changes in v2: > - Add fixes tag. > - Replace "if (drvdata->nrseqstate)" with "if (drvdata->numextinsel)" > - Link to v1: https://lore.kernel.org/r/20250811-trcextinselr_issue-v1-1-ed78f3215502@oss… > --- > drivers/hwtracing/coresight/coresight-etm4x-core.c | 11 ++++++++--- > drivers/hwtracing/coresight/coresight-etm4x.h | 2 ++ > 2 files changed, 10 insertions(+), 3 deletions(-) > > diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c > index 42e5d37403addc6ec81f2e3184522d67d1677c04..4e411427303981104d11720d3c73af91030f8df3 100644 > --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c > +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c > @@ -528,7 +528,8 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata) > etm4x_relaxed_write32(csa, config->seq_rst, TRCSEQRSTEVR); > etm4x_relaxed_write32(csa, config->seq_state, TRCSEQSTR); > } > - etm4x_relaxed_write32(csa, config->ext_inp, TRCEXTINSELR); > + if (drvdata->numextinsel) > + etm4x_relaxed_write32(csa, config->ext_inp, TRCEXTINSELR); > for (i = 0; i < drvdata->nr_cntr; i++) { > etm4x_relaxed_write32(csa, config->cntrldvr[i], TRCCNTRLDVRn(i)); > etm4x_relaxed_write32(csa, config->cntr_ctrl[i], TRCCNTCTLRn(i)); > @@ -1423,6 +1424,7 @@ static void etm4_init_arch_data(void *info) > etmidr5 = etm4x_relaxed_read32(csa, TRCIDR5); > /* NUMEXTIN, bits[8:0] number of external inputs implemented */ > drvdata->nr_ext_inp = FIELD_GET(TRCIDR5_NUMEXTIN_MASK, etmidr5); > + drvdata->numextinsel = FIELD_GET(TRCIDR5_NUMEXTINSEL_MASK, etmidr5); > /* TRACEIDSIZE, bits[21:16] indicates the trace ID width */ > drvdata->trcid_size = FIELD_GET(TRCIDR5_TRACEIDSIZE_MASK, etmidr5); > /* ATBTRIG, bit[22] implementation can support ATB triggers? */ > @@ -1852,7 +1854,9 @@ static int __etm4_cpu_save(struct etmv4_drvdata *drvdata) > state->trcseqrstevr = etm4x_read32(csa, TRCSEQRSTEVR); > state->trcseqstr = etm4x_read32(csa, TRCSEQSTR); > } > - state->trcextinselr = etm4x_read32(csa, TRCEXTINSELR); > + > + if (drvdata->numextinsel) > + state->trcextinselr = etm4x_read32(csa, TRCEXTINSELR); > > for (i = 0; i < drvdata->nr_cntr; i++) { > state->trccntrldvr[i] = etm4x_read32(csa, TRCCNTRLDVRn(i)); > @@ -1984,7 +1988,8 @@ static void __etm4_cpu_restore(struct etmv4_drvdata *drvdata) > etm4x_relaxed_write32(csa, state->trcseqrstevr, TRCSEQRSTEVR); > etm4x_relaxed_write32(csa, state->trcseqstr, TRCSEQSTR); > } > - etm4x_relaxed_write32(csa, state->trcextinselr, TRCEXTINSELR); > + if (drvdata->numextinsel) > + etm4x_relaxed_write32(csa, state->trcextinselr, TRCEXTINSELR); > > for (i = 0; i < drvdata->nr_cntr; i++) { > etm4x_relaxed_write32(csa, state->trccntrldvr[i], TRCCNTRLDVRn(i)); > diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h > index ac649515054d905fa365203bd35f1d839b03292f..823914fefa90a36a328b652b0dc3828b9bddd990 100644 > --- a/drivers/hwtracing/coresight/coresight-etm4x.h > +++ b/drivers/hwtracing/coresight/coresight-etm4x.h > @@ -162,6 +162,7 @@ > #define TRCIDR4_NUMVMIDC_MASK GENMASK(31, 28) > > #define TRCIDR5_NUMEXTIN_MASK GENMASK(8, 0) > +#define TRCIDR5_NUMEXTINSEL_MASK GENMASK(11, 9) > #define TRCIDR5_TRACEIDSIZE_MASK GENMASK(21, 16) > #define TRCIDR5_ATBTRIG BIT(22) > #define TRCIDR5_LPOVERRIDE BIT(23) > @@ -999,6 +1000,7 @@ struct etmv4_drvdata { > u8 nr_cntr; > u8 nr_ext_inp; > u8 numcidc; > + u8 numextinsel; > u8 numvmidc; > u8 nrseqstate; > u8 nr_event; > > --- > base-commit: 8f5ae30d69d7543eee0d70083daf4de8fe15d585 > change-id: 20250811-trcextinselr_issue-f267afa0e5ed > > Best regards,

4 months, 3 weeks

Re: [PATCH v2] coresight-etm4x: Conditionally access register TRCEXTINSELR

by James Clark

On 12/08/2025 9:24 am, Yuanfang Zhang wrote: > The TRCEXTINSELR is only implemented if TRCIDR5.NUMEXTINSEL > 0. > To avoid invalid accesses, introduce a check on numextinsel > (derived from TRCIDR5[11:9]) before reading or writing to this register. > > Fixes: f5bd523690d2 ("coresight: etm4x: Convert all register accesses") > Signed-off-by: Yuanfang Zhang <yuanfang.zhang(a)oss.qualcomm.com> > --- > Changes in v2: > - Add fixes tag. > - Replace "if (drvdata->nrseqstate)" with "if (drvdata->numextinsel)" > - Link to v1: https://lore.kernel.org/r/20250811-trcextinselr_issue-v1-1-ed78f3215502@oss… > --- > drivers/hwtracing/coresight/coresight-etm4x-core.c | 11 ++++++++--- > drivers/hwtracing/coresight/coresight-etm4x.h | 2 ++ > 2 files changed, 10 insertions(+), 3 deletions(-) > > diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c > index 42e5d37403addc6ec81f2e3184522d67d1677c04..4e411427303981104d11720d3c73af91030f8df3 100644 > --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c > +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c > @@ -528,7 +528,8 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata) > etm4x_relaxed_write32(csa, config->seq_rst, TRCSEQRSTEVR); > etm4x_relaxed_write32(csa, config->seq_state, TRCSEQSTR); > } > - etm4x_relaxed_write32(csa, config->ext_inp, TRCEXTINSELR); > + if (drvdata->numextinsel) > + etm4x_relaxed_write32(csa, config->ext_inp, TRCEXTINSELR); > for (i = 0; i < drvdata->nr_cntr; i++) { > etm4x_relaxed_write32(csa, config->cntrldvr[i], TRCCNTRLDVRn(i)); > etm4x_relaxed_write32(csa, config->cntr_ctrl[i], TRCCNTCTLRn(i)); > @@ -1423,6 +1424,7 @@ static void etm4_init_arch_data(void *info) > etmidr5 = etm4x_relaxed_read32(csa, TRCIDR5); > /* NUMEXTIN, bits[8:0] number of external inputs implemented */ > drvdata->nr_ext_inp = FIELD_GET(TRCIDR5_NUMEXTIN_MASK, etmidr5); > + drvdata->numextinsel = FIELD_GET(TRCIDR5_NUMEXTINSEL_MASK, etmidr5); > /* TRACEIDSIZE, bits[21:16] indicates the trace ID width */ > drvdata->trcid_size = FIELD_GET(TRCIDR5_TRACEIDSIZE_MASK, etmidr5); > /* ATBTRIG, bit[22] implementation can support ATB triggers? */ > @@ -1852,7 +1854,9 @@ static int __etm4_cpu_save(struct etmv4_drvdata *drvdata) > state->trcseqrstevr = etm4x_read32(csa, TRCSEQRSTEVR); > state->trcseqstr = etm4x_read32(csa, TRCSEQSTR); > } > - state->trcextinselr = etm4x_read32(csa, TRCEXTINSELR); > + > + if (drvdata->numextinsel) > + state->trcextinselr = etm4x_read32(csa, TRCEXTINSELR); > > for (i = 0; i < drvdata->nr_cntr; i++) { > state->trccntrldvr[i] = etm4x_read32(csa, TRCCNTRLDVRn(i)); > @@ -1984,7 +1988,8 @@ static void __etm4_cpu_restore(struct etmv4_drvdata *drvdata) > etm4x_relaxed_write32(csa, state->trcseqrstevr, TRCSEQRSTEVR); > etm4x_relaxed_write32(csa, state->trcseqstr, TRCSEQSTR); > } > - etm4x_relaxed_write32(csa, state->trcextinselr, TRCEXTINSELR); > + if (drvdata->numextinsel) > + etm4x_relaxed_write32(csa, state->trcextinselr, TRCEXTINSELR); > > for (i = 0; i < drvdata->nr_cntr; i++) { > etm4x_relaxed_write32(csa, state->trccntrldvr[i], TRCCNTRLDVRn(i)); > diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h > index ac649515054d905fa365203bd35f1d839b03292f..823914fefa90a36a328b652b0dc3828b9bddd990 100644 > --- a/drivers/hwtracing/coresight/coresight-etm4x.h > +++ b/drivers/hwtracing/coresight/coresight-etm4x.h > @@ -162,6 +162,7 @@ > #define TRCIDR4_NUMVMIDC_MASK GENMASK(31, 28) > > #define TRCIDR5_NUMEXTIN_MASK GENMASK(8, 0) > +#define TRCIDR5_NUMEXTINSEL_MASK GENMASK(11, 9) > #define TRCIDR5_TRACEIDSIZE_MASK GENMASK(21, 16) > #define TRCIDR5_ATBTRIG BIT(22) > #define TRCIDR5_LPOVERRIDE BIT(23) > @@ -999,6 +1000,7 @@ struct etmv4_drvdata { > u8 nr_cntr; > u8 nr_ext_inp; > u8 numcidc; > + u8 numextinsel; > u8 numvmidc; > u8 nrseqstate; > u8 nr_event; > > --- > base-commit: 8f5ae30d69d7543eee0d70083daf4de8fe15d585 > change-id: 20250811-trcextinselr_issue-f267afa0e5ed > > Best regards, Reviewed-by: James Clark <james.clark(a)linaro.org>

4 months, 3 weeks

Re: [PATCH] coresight-etm4x: Conditionally access register TRCEXTINSELR

by James Clark

On 11/08/2025 10:57 am, Yuanfang Zhang wrote: > The TRCEXTINSELR is only implemented if TRCIDR5.NUMEXTINSEL > 0. > To avoid invalid accesses, introduce a check on numextinsel > (derived from TRCIDR5[11:9]) before reading or writing to this register. > Looks like this should have a fixes: tag. > Signed-off-by: Yuanfang Zhang <yuanfang.zhang(a)oss.qualcomm.com> > --- > drivers/hwtracing/coresight/coresight-etm4x-core.c | 11 ++++++++--- > drivers/hwtracing/coresight/coresight-etm4x.h | 2 ++ > 2 files changed, 10 insertions(+), 3 deletions(-) > > diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c > index 42e5d37403addc6ec81f2e3184522d67d1677c04..8a9c4caceff0165e4fce7ac4250f3e16ccc1d34e 100644 > --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c > +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c > @@ -528,7 +528,8 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata) > etm4x_relaxed_write32(csa, config->seq_rst, TRCSEQRSTEVR); > etm4x_relaxed_write32(csa, config->seq_state, TRCSEQSTR); > } > - etm4x_relaxed_write32(csa, config->ext_inp, TRCEXTINSELR); > + if (drvdata->numextinsel) > + etm4x_relaxed_write32(csa, config->ext_inp, TRCEXTINSELR); > for (i = 0; i < drvdata->nr_cntr; i++) { > etm4x_relaxed_write32(csa, config->cntrldvr[i], TRCCNTRLDVRn(i)); > etm4x_relaxed_write32(csa, config->cntr_ctrl[i], TRCCNTCTLRn(i)); > @@ -1423,6 +1424,7 @@ static void etm4_init_arch_data(void *info) > etmidr5 = etm4x_relaxed_read32(csa, TRCIDR5); > /* NUMEXTIN, bits[8:0] number of external inputs implemented */ > drvdata->nr_ext_inp = FIELD_GET(TRCIDR5_NUMEXTIN_MASK, etmidr5); > + drvdata->numextinsel = FIELD_GET(TRCIDR5_NUMEXTINSEL_MASK, etmidr5); > /* TRACEIDSIZE, bits[21:16] indicates the trace ID width */ > drvdata->trcid_size = FIELD_GET(TRCIDR5_TRACEIDSIZE_MASK, etmidr5); > /* ATBTRIG, bit[22] implementation can support ATB triggers? */ > @@ -1852,7 +1854,9 @@ static int __etm4_cpu_save(struct etmv4_drvdata *drvdata) > state->trcseqrstevr = etm4x_read32(csa, TRCSEQRSTEVR); > state->trcseqstr = etm4x_read32(csa, TRCSEQSTR); > } > - state->trcextinselr = etm4x_read32(csa, TRCEXTINSELR); > + > + if (drvdata->nrseqstate) Shouldn't this be "if (drvdata->numextinsel)"? Or it needs a comment saying why it's different to the others. Otherwise looks ok. > + state->trcextinselr = etm4x_read32(csa, TRCEXTINSELR); > > for (i = 0; i < drvdata->nr_cntr; i++) { > state->trccntrldvr[i] = etm4x_read32(csa, TRCCNTRLDVRn(i)); > @@ -1984,7 +1988,8 @@ static void __etm4_cpu_restore(struct etmv4_drvdata *drvdata) > etm4x_relaxed_write32(csa, state->trcseqrstevr, TRCSEQRSTEVR); > etm4x_relaxed_write32(csa, state->trcseqstr, TRCSEQSTR); > } > - etm4x_relaxed_write32(csa, state->trcextinselr, TRCEXTINSELR); > + if (drvdata->numextinsel) > + etm4x_relaxed_write32(csa, state->trcextinselr, TRCEXTINSELR); > > for (i = 0; i < drvdata->nr_cntr; i++) { > etm4x_relaxed_write32(csa, state->trccntrldvr[i], TRCCNTRLDVRn(i)); > diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h > index ac649515054d905fa365203bd35f1d839b03292f..823914fefa90a36a328b652b0dc3828b9bddd990 100644 > --- a/drivers/hwtracing/coresight/coresight-etm4x.h > +++ b/drivers/hwtracing/coresight/coresight-etm4x.h > @@ -162,6 +162,7 @@ > #define TRCIDR4_NUMVMIDC_MASK GENMASK(31, 28) > > #define TRCIDR5_NUMEXTIN_MASK GENMASK(8, 0) > +#define TRCIDR5_NUMEXTINSEL_MASK GENMASK(11, 9) > #define TRCIDR5_TRACEIDSIZE_MASK GENMASK(21, 16) > #define TRCIDR5_ATBTRIG BIT(22) > #define TRCIDR5_LPOVERRIDE BIT(23) > @@ -999,6 +1000,7 @@ struct etmv4_drvdata { > u8 nr_cntr; > u8 nr_ext_inp; > u8 numcidc; > + u8 numextinsel; > u8 numvmidc; > u8 nrseqstate; > u8 nr_event; > > --- > base-commit: 8f5ae30d69d7543eee0d70083daf4de8fe15d585 > change-id: 20250811-trcextinselr_issue-f267afa0e5ed > > Best regards,

4 months, 3 weeks

Re: [PATCH v1] coresight: tpda: fix the logic to setup the element size

by James Clark

On 06/08/2025 9:09 am, Jie Gan wrote: > Some TPDM devices support both CMB and DSB datasets, requiring > the system to enable the port with both corresponding element sizes. > > Currently, the logic treats tpdm_read_element_size as successful if > the CMB element size is retrieved correctly, regardless of whether > the DSB element size is obtained. This behavior causes issues > when parsing data from TPDM devices that depend on both element sizes. > > To address this, the function should explicitly fail if the DSB > element size cannot be read correctly. > > Fixes: e6d7f5252f73 ("coresight-tpda: Add support to configure CMB element") > Signed-off-by: Jie Gan <jie.gan(a)oss.qualcomm.com> > --- > drivers/hwtracing/coresight/coresight-tpda.c | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/drivers/hwtracing/coresight/coresight-tpda.c b/drivers/hwtracing/coresight/coresight-tpda.c > index 0633f04beb24..333b3cb23685 100644 > --- a/drivers/hwtracing/coresight/coresight-tpda.c > +++ b/drivers/hwtracing/coresight/coresight-tpda.c > @@ -71,6 +71,8 @@ static int tpdm_read_element_size(struct tpda_drvdata *drvdata, > if (tpdm_data->dsb) { > rc = fwnode_property_read_u32(dev_fwnode(csdev->dev.parent), > "qcom,dsb-element-bits", &drvdata->dsb_esize); > + if (rc) > + goto out; > } > > if (tpdm_data->cmb) { > @@ -78,6 +80,7 @@ static int tpdm_read_element_size(struct tpda_drvdata *drvdata, > "qcom,cmb-element-bits", &drvdata->cmb_esize); > } > > +out: > if (rc) > dev_warn_once(&csdev->dev, > "Failed to read TPDM Element size: %d\n", rc); Reviewed-by: James Clark <james.clark(a)linaro.org>

5 months

[PATCH v10 0/2] coresight: Add label sysfs node support

by Mao Jinlong

Change since V9: 1. Replace scnprintf with sysfs_emit. 2. Update date in ABI files. V9 link: https://lkml.org/lkml/2025/7/17/832 Change since V8: 1. Add label in all documentations of coresight components. 2. Add control of the visibility of the label sysfs attribute. V8 link: https://lkml.org/lkml/2025/7/3/985 Change since V7: 1. Update the conflict when apply to coresight next. 2. Update the Date and version in ABI file. V7 link: https://patchwork.kernel.org/project/linux-arm-kernel/patch/20250226121926.… Change since V6: 1. Update the date and version in ABI file. Change since V5: 1. Update the kernel version of ABI files. 2. Add link of different patch versions. V5 link: https://patchwork.kernel.org/project/linux-arm-msm/cover/20241210122253.319… Change since V4: 1. Add label in DT and add label sysfs node for each coresight device. V4 link: https://patchwork.kernel.org/project/linux-arm-msm/cover/20240703122340.268… Change since V3: 1. Change device-name to arm,cs-dev-name. 2. Add arm,cs-dev-name to only CTI and sources' dt-binding. V3 link: https://patchwork.kernel.org/project/linux-arm-msm/cover/20240131082628.628… Change since V2: 1. Fix the error in coresight core. drivers/hwtracing/coresight/coresight-core.c:1775:7: error: assigning to 'char *' from 'const char *' discards qualifiers 2. Fix the warning when run dtbinding check. Documentation/devicetree/bindings/arm/arm,coresight-cpu-debug.yaml: device-name: missing type definition V2 link: https://patchwork.kernel.org/project/linux-arm-msm/cover/20240115164252.265… Change since V1: 1. Change coresight-name to device name. 2. Add the device-name in coresight dt bindings. V1 link: https://patchwork.kernel.org/project/linux-arm-kernel/patch/20230208110716.… Mao Jinlong (2): dt-bindings: arm: Add label in the coresight components coresight: Add label sysfs node support .../testing/sysfs-bus-coresight-devices-cti | 6 ++ .../sysfs-bus-coresight-devices-dummy-source | 6 ++ .../testing/sysfs-bus-coresight-devices-etb10 | 6 ++ .../testing/sysfs-bus-coresight-devices-etm3x | 6 ++ .../testing/sysfs-bus-coresight-devices-etm4x | 6 ++ .../sysfs-bus-coresight-devices-funnel | 6 ++ .../testing/sysfs-bus-coresight-devices-stm | 6 ++ .../testing/sysfs-bus-coresight-devices-tmc | 6 ++ .../testing/sysfs-bus-coresight-devices-tpdm | 6 ++ .../testing/sysfs-bus-coresight-devices-trbe | 6 ++ .../bindings/arm/arm,coresight-cti.yaml | 4 ++ .../arm/arm,coresight-dummy-sink.yaml | 4 ++ .../arm/arm,coresight-dummy-source.yaml | 4 ++ .../arm/arm,coresight-dynamic-funnel.yaml | 4 ++ .../arm/arm,coresight-dynamic-replicator.yaml | 4 ++ .../bindings/arm/arm,coresight-etb10.yaml | 4 ++ .../bindings/arm/arm,coresight-etm.yaml | 4 ++ .../arm/arm,coresight-static-funnel.yaml | 4 ++ .../arm/arm,coresight-static-replicator.yaml | 4 ++ .../bindings/arm/arm,coresight-tmc.yaml | 4 ++ .../bindings/arm/arm,coresight-tpiu.yaml | 4 ++ .../bindings/arm/qcom,coresight-ctcu.yaml | 4 ++ .../arm/qcom,coresight-remote-etm.yaml | 4 ++ .../bindings/arm/qcom,coresight-tpda.yaml | 4 ++ .../bindings/arm/qcom,coresight-tpdm.yaml | 4 ++ drivers/hwtracing/coresight/coresight-sysfs.c | 71 ++++++++++++++++++- 26 files changed, 189 insertions(+), 2 deletions(-) -- 2.25.1

5 months

[PATCH v9 0/2] coresight: Add label sysfs node support

by Mao Jinlong

Change since V8: 1. Add label in all documentations of coresight components. 2. Add control of the visibility of the label sysfs attribute. V8 link: https://lkml.org/lkml/2025/7/3/985 Change since V7: 1. Update the conflict when apply to coresight next. 2. Update the Date and version in ABI file. V7 link: https://patchwork.kernel.org/project/linux-arm-kernel/patch/20250226121926.… Change since V6: 1. Update the date and verison in ABI file. Change since V5: 1. Update the kernel version of ABI files. 2. Add link of different patch versions. V5 link: https://patchwork.kernel.org/project/linux-arm-msm/cover/20241210122253.319… Change since V4: 1. Add label in DT and add label sysfs node for each coresight device. V4 link: https://patchwork.kernel.org/project/linux-arm-msm/cover/20240703122340.268… Change since V3: 1. Change device-name to arm,cs-dev-name. 2. Add arm,cs-dev-name to only CTI and sources' dt-binding. V3 link: https://patchwork.kernel.org/project/linux-arm-msm/cover/20240131082628.628… Change since V2: 1. Fix the error in coresight core. drivers/hwtracing/coresight/coresight-core.c:1775:7: error: assigning to 'char *' from 'const char *' discards qualifiers 2. Fix the warning when run dtbinding check. Documentation/devicetree/bindings/arm/arm,coresight-cpu-debug.yaml: device-name: missing type definition V2 link: https://patchwork.kernel.org/project/linux-arm-msm/cover/20240115164252.265… Change since V1: 1. Change coresight-name to device name. 2. Add the device-name in coresight dt bindings. V1 link: https://patchwork.kernel.org/project/linux-arm-kernel/patch/20230208110716.… Mao Jinlong (2): dt-bindings: arm: Add label in the coresight components coresight: Add label sysfs node support .../testing/sysfs-bus-coresight-devices-cti | 6 ++ .../sysfs-bus-coresight-devices-dummy-source | 6 ++ .../testing/sysfs-bus-coresight-devices-etb10 | 6 ++ .../testing/sysfs-bus-coresight-devices-etm3x | 6 ++ .../testing/sysfs-bus-coresight-devices-etm4x | 6 ++ .../sysfs-bus-coresight-devices-funnel | 6 ++ .../testing/sysfs-bus-coresight-devices-stm | 6 ++ .../testing/sysfs-bus-coresight-devices-tmc | 6 ++ .../testing/sysfs-bus-coresight-devices-tpdm | 6 ++ .../testing/sysfs-bus-coresight-devices-trbe | 6 ++ .../bindings/arm/arm,coresight-cti.yaml | 4 ++ .../arm/arm,coresight-dummy-sink.yaml | 4 ++ .../arm/arm,coresight-dummy-source.yaml | 4 ++ .../arm/arm,coresight-dynamic-funnel.yaml | 4 ++ .../arm/arm,coresight-dynamic-replicator.yaml | 4 ++ .../bindings/arm/arm,coresight-etb10.yaml | 4 ++ .../bindings/arm/arm,coresight-etm.yaml | 4 ++ .../arm/arm,coresight-static-funnel.yaml | 4 ++ .../arm/arm,coresight-static-replicator.yaml | 4 ++ .../bindings/arm/arm,coresight-tmc.yaml | 4 ++ .../bindings/arm/arm,coresight-tpiu.yaml | 4 ++ .../bindings/arm/qcom,coresight-ctcu.yaml | 4 ++ .../arm/qcom,coresight-remote-etm.yaml | 4 ++ .../bindings/arm/qcom,coresight-tpda.yaml | 4 ++ .../bindings/arm/qcom,coresight-tpdm.yaml | 4 ++ drivers/hwtracing/coresight/coresight-sysfs.c | 71 ++++++++++++++++++- 26 files changed, 189 insertions(+), 2 deletions(-) -- 2.25.1

5 months

[PATCH v3 0/2] Add Qualcomm extended CTI support

by Mao Jinlong

The QCOM extended CTI is a heavily parameterized version of ARM’s CSCTI. It allows a debugger to send to trigger events to a processor or to send a trigger event to one or more processors when a trigger event occurs on another processor on the same SoC, or even between SoCs. QCOM extended CTI supports up to 128 triggers. And some of the register offsets are changed. The commands to configure CTI triggers are the same as ARM's CTI. Changes in v3: 1. Rename is_extended_cti() to of_is_extended_cti(). 2. Add the missing 'i' when write the CTI trigger registers. 3. Convert the multi-line output in sysfs to single line. 4. Initialize offset arrays using designated initializer. Link to V2 - https://lore.kernel.org/all/20250429071841.1158315-3-quic_jinlmao@quicinc.c… Changes in V2: 1. Add enum for compatible items. 2. Move offset arrays to coresight-cti-core Yingchao Deng (2): dt-bindings: arm: Add Qualcomm extended CTI coresight: cti: Add Qualcomm extended CTI support .../bindings/arm/arm,coresight-cti.yaml | 4 +- .../hwtracing/coresight/coresight-cti-core.c | 127 +++++++++++++---- .../coresight/coresight-cti-platform.c | 16 ++- .../hwtracing/coresight/coresight-cti-sysfs.c | 128 ++++++++++++++---- drivers/hwtracing/coresight/coresight-cti.h | 75 +++++----- 5 files changed, 248 insertions(+), 102 deletions(-) -- 2.25.1

5 months

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