Hi,
I read in the armv8 architecture reference manual that a number of AArch32 instructions have been obsoleted. Do the current armv7 version of GCC ever generate code containing any of these, without me explicitly writing inline assembly? If it can, how can this be turned off? Just would like to make sure that a C-program (without inline assembly) compiled today for armv7 will run in AArch32 mode when armv8 boards come out.
The following are obsoleted in ARMv8:
A32 SWP and SWPB instructions.
Jazelle (only trivial implementations are supported).
VFP short vectors and asynchronous bounces.
Fast Context Switch Extension (FCSE).
Thanks: Magnus
Magnus Karlsson
Software Development Engineering Manager
LSI Corporation
Box 1024, Knarrarnäsgatan 15
SE-164 21 Kista, Sweden
TEL +46 8 594 607 09
FAX +46 8 594 607 10
CELL +46 73 80 444 88
magnus.karlsson(a)lsi.com
== Issues ==
* none
== Progress ==
* LRA on AArch32:
o TCWG-343 : Make LRA the default for the ARM backend (0/10)
- Stop progress on this card, will close it when FSF 4.9 will be released.
o TCWG-345 : Analyse performance of LRA for ARM. (4/10)
- Spec2K figures on Cortex-a15 Analysis.
- re-run benchs in console mode chrubuntu without ASLR + perf tool
* Backports review: (2/10)
o Start to prepare cortex-a53 backports review
* Misc:
o Various meetings and slideware (4/10).
- Linaro and internal ones.
== Next ==
- continue cortex-a53 review
- some backports to do.
- continue on TCWG-345
== Progress ==
* Worked on getting eglibc git mirror back up and running
* Released eglibc 2.19 2014.04
* Respin of glibc aarch64 setcontext patches
* Respin of ld aarch64 RELASZ patch
* Tidied up, rebased and committed ARM ld pointer equality patch
* Work on resurrecting glibc benchmark result graphing script
* Holiday on Friday
== Issues ==
* Couple of hours power outage on Monday
== Plan ==
* Get outstanding glibc and binutils patches committed
* Reorganise JIRA cards for malloc work
* glibc benchmarking
--
Will Newton
Toolchain Working Group, Linaro
== Progress ==
* Add support for fork/vfork/exec events/catchpoints in remote
gdbserver [TCWG-263] [4/10]
-- Debugged catchpoint code and reviewed gdbserver implementation for events.
-- Still require a lot of code understanding before actual
implementation can start.
* Wrote a script that takes two gdb build trees and configuration
arguments to test them in native, remote-native and remote-target
configurations [TCWG-96] [3/10]
* Laptop OS re-install [1/10]
* GDB open cards issues review [1/10]
* Sick half day off on Friday [1/10]
== Plan ==
* Complete work on TCWG-96.
-- Write a script that tests gdb in remote-native configuration using ssh.
-- Integrate all testing scripts and test them.
-- Update wiki page with updated scripts and how to use them.
* Monday Day Off: Pakistan Day 23rd March public holiday roll over.
== Progress ==
CARD-1210 - optimizing prologue/epilogue With -fomit-frame-pointer (4/10)
- regression tested the patch and fixed issues
- Dropping the patch and closing the card as it has been worked on at arm.
TCWG-15 - zero/sign extension elimination for crc (3/10)
- Looked at crc and looked at the other optimizations listed in card 440.
- Improved the local patch to remove the missing optimization
TCWG-413 - Running spec2006 with aarch64 (3/10)
- Built and set-up spec2006.
- Ran into to some compile time and run time errors
== Plan ==
Continue with zero/sign extension elimination
Start looking at literal pool merging
== This week ==
Merged all backports related to a53 support and successfully built arm
and aarch64 cross compilers:
202333 - [AArch64, ARM] Introduce "mrs" type attribute.
202334 - [AArch64] Use neon_<ldm,stm>_2 where appropriate as "type".
202448 - [AArch64] Prevent generic pipeline description from dominating
other pipeline descriptions.
202560 - set "type" attribute properly in arm_cmpsi_insn, cleanup
203241 - Cortex-a53 use Cortex tuning
203611 – 203621 – Neon types Parts 1 to 10
204575 - [ARM, AArch64] Make aarch-common.c files more robust.
205050 - [ARM] Add missing type attribute to zero_extend on arm
204782 - [AArch64] [-mtune cleanup 2/5] Tune for Cortex-A53 by default.
204784 - [AArch64] [-mtune cleanup 4/5] Remove "example-1", "example-2"
tuning options.
204852 - [AArch64] Remove simd_type
205014 - [AArch64] Remove v8type attribute.
205105 - [AArch64] Remove "mode", "mode2" attributes
204783 - [AArch64] [-mtune cleanup 3/5] [Temporary] When asked to tune
for Cortex-A57, tune for Cortex-A15
== Next week ==
Test a53 support
Backport vectorization bug
== Future ==
== Issues ==
* None
== Progress ==
* Identify a missing instruction pattern which blocks fcsel
optimization. A patch was sent out for community review. [2/10,
TCWG-309]
* Identify a ICE when handling dwarf-info in ARM backend when testing
shrink-wrap. A fix was committed to trunk. [2/10]
* Rebase and test the shrink-wrap codes for APCS_FRAME. [5/10]
* Prepare Linaro toolchain 2014.03 binaries release [1/10].
* Investigate CRC improvement chances.
== Plans ==
* Create a prebuilt sysroot based on Linaro eglibc-2014.04.
* Continue on shrink-wrap.
== Progress ==
* AArch64 (TCWG-387)
- Implemented simple C sin/cos functions for sphereflake
- AArch64 builds, passes check-all and test-suite
- Closed Jira task
* IAS (TCWG-377)
- Updated release notes
- IAS build, passes check-all, test-suite and compiles other large codebases
- Closed Jira task
* EHABI (TCWG-124)
- Updated release notes
- EHABI builds, passes check-all, test-suite
- Waiting for last patch to go to close the Jira task
* Compiler-RT (TCWG-125)
- Re-testing with current trunk+RT, all pass
- Next step, libunwind (not ready yet)
* Background
- Patch review, etc
- Studying TableGen, writing some docs (http://llvm.org/docs/TableGen/)
- Proposing changes to debug/EH unwind function attributes in IR
- Changing Zorg to not submit LNT reports by default (avoids bot breakage)
- Planning LLVM+Linux involvement as next big task
* Time
- CARD-862 8/10
- Others 2/10
== Plan ==
* Continue pushing __builtin___clear_cache and -fno-unwind-tables upstream
* Implement the Clang part of __builtin___clear_cache and update the docs
* Try to add LLVM/Clang to cbuildv2
* Start merging libunwind from libc++ to Compiler-RT and test it on ARM
* Get the kernel task started with the LLVMLinux guys
Hello,
the attached program changes the output from "true" to "false" when the
-Bsymbolic / -Bsymbolic-functions options are passed to GCC. This
happens on ARM -- on x86-64 output is always "true".
The program involves a comparison, within a shared library, of a PMF
defined inside the shared library itself with the same PMF passed by the
application.
At this stage I still don't know if it's a GCC problem, a ld.so problem,
ABI constraints, undefined behaviour, or whatnot; but any help is
appreciated.
Compile with:
> g++ -fPIC -shared -Wall -o libshared.so -Wl,-Bsymbolic shared.cpp
> g++ -fPIE -Wall -o main main.cpp -L. -lshared
(The long story is that Qt 5 is taking PMFs in its public API, and the
comparison failing inside of Qt shared libraries is breaking code on
ARM, as -Bsymbolic is set by default there.)
Thanks,
--
Giuseppe D'Angelo | giuseppe.dangelo(a)kdab.com | Software Engineer
KDAB (UK) Ltd., a KDAB Group company
Tel. UK +44-1738-450410, Sweden (HQ) +46-563-540090
KDAB - Qt Experts - Platform-independent software solutions