== Progress ==
* Short Week
-- Monday Day Off: Pakistan Day 23rd March public holiday roll over. [2/10]
-- Short leave on Thursday [1/10]
* Work on gdb testing utility [TCWG-96] [7/10]
-- Writing a new gdb testing utility script that automates gdb
testing in various configurations and compares testsuite results.
-- Support for all kind of native, native-gdbserver and
remote-gdbserver gdb configurations has been added.
-- Interactive and configuration file based user input mode has been added.
-- Testing configurations host alive, ssh possible, board file found
and ability to build sources using user defined configure flags has
been added.
== Plan ==
* Work on gdb testing utility [TCWG-96].
-- Add support to run native and native-gdbserver test via ssh on
remote machines like arm-linux.
-- Bug fix and test gdb testing utility by running it various configurations.
-- Update wiki page with testing utility and how to use it.
== This week ==
a53 support
- Fixed regression found in arm testing and resubmitted build and
merge requests
- arrch64 testing passed with no regressions. Testing with a53
support enabled still required
Merged 202663 (vectorizer bug) into 4.7 and 4.8 branches. Submitted
merge and build requests
== Next week ==
- Test aarch64 with a53 support enabled on qemu64
- Work on bug 60657 - [4.9 Regresssion] ICE: error: insn does not
satisfy its constraints
== Future ==
== Issues ==
* None
== Progress ==
* Create prebuilt sysroot based on Linaro eglibc 2014.04 release
(https://launchpad.net/linaro-toolchain-binaries/support/01/+download/linaro…)
(1/10).
* Enable shrink-wrap for apcs. Patch was out for community review. (1/10)
* Reinvestigate shrink-wrap enhancement (4/10, TCWG-133)
- There was improvement in ira to split_live_ranges_for_shrink_wrap
(http://gcc.gnu.org/bugzilla/show_bug.cgi?id=10474). But it still can
not handle the case in 453.povray.
- Investigate to do a simple copy-forward when prepare_shrink_wrap.
* Investigate lp:1296942 (pr60663). Patch is sent out for community
review. (4/10)
* Backporting the fix for pr60264 to Linaro 4..8.
== Plans ==
* Continue on shrink-wrap enhancement.
== Planned leaves ==
* April 7: Qingming holiday.
== Progress ==
- TCWG-413 Spec2006 (7/10)
- Investigated compiler error for 481.wrf with FSF 4.8.2. Issue is
due to aarch64_cm<cmp><mode> pattern (fcmle and fcmlt supports only #0
as third val). This is already fixed in trunk and Linaro 4.8.
- Ran profiling to analyse 4.9 regressions. Started looking into
P7Vitterbui which is one of the functions that performs badly.
- TCWG-291 CRC (3/10)
Came up with a patch for improving vrp for test-case. Some c++ test
cases are failing in regression testing with this patch. Looking into it.
- TCWG-394 / PR60034
Patch committed and card closed.
http://gcc.gnu.org/viewcvs?rev=208949&root=gcc&view=rev
== Plan ==
Continue with Spec2006 and crc
== Progress ==
* Android (no card, 10 minutes. ;)
- Implemented __builtin___clear_cache in Clang
* Kernel (TCWG-417) 6/10
- VLAIS in crypto (last place in kernel)
- __builtin__stack_pointer (new builtin)
- Discussion in GCC list, named registers might be a better option
- Discussion in LLVM list about implementing named registers
- Implementing named register variables...
- Planning on LAVA testing LLVM kernels with LLVMLinux
- __aeabi_memset/cpy/move (both Android and Kernel) will have to be fixed
* Libraries (TCWG-125) 2/10
- libc++abi's unwind routines assume (ARM == SjLj)
- libc++ doesn't work without them
- We'll need to teach it about EHABI (later)
* Background 2/10
- Installed ArchLinux on my laptop, took some time to setup
- Re-org of LLVM Jira Cards (TCWG-417)
- Reviewing some GSoC proposals
== Plan ==
* implement named register variables in LLVM, then Clang
* Continue helping LLVMLinux and Milosz to test the LLVM kernel
* Time allowing, check CBuild2 for an LLVM build
* Two long weeks of holidays...
== Progress ==
* Bugfix aarch64 setcontext patch (2/10, TCWG-410)
* malloc requirements wiki page (2/10, TCWG-414)
* Lots of creating and updating and updating JIRA cards (1/10)
* glibc patch review (1/10)
* Assorted small patches - ld relasz, gnulib obstack, glibc strtod
benchmark (2/10)
* Investigate a couple of issues raised by member services and on lists (2/10)
== Issues ==
* None
== Plan ==
* Resurrect glibc malloc benchtest
* More glibc benchmark infrastructure work
* Check status of glibc ARM port build warnings
--
Will Newton
Toolchain Working Group, Linaro
== Week of March 17th ==
- STREAM regression (TCWG-388, 4/10)
-- Investigated how to prioritize memory references instructions in GCC scheduler to take full advantage of L2 autopretch hardware in certain ARM cores.
-- Fixed -fdbg-cnt=sched_insn debug counter along the way. It appear to have been broken since GCC 4.7.
- Discussed reg_pressure instruction scheduling with Charlie. (TCWG-135, 1/10)
- Various discussions about instruction scheduling in GCC. (1/10)
- Together with Michael prepared patch list for GCC contingency plan. (3/10)
- Made first-in-series video about tips-and-trick of GCC development. Your critiques are welcome!
-- Using GCC debug counters (7m34s): https://www.youtube.com/watch?v=IWRYCOkgL04
== Week of March 24th ==
- STREAM regression (TCWG-388)
-- Get a prototype patch.
- Other expected and unexpected tasks that come up.
--
Maxim Kuvyrkov
www.linaro.org
Last week
* one day off [2/10]
* NEON scheduling investigation - TCWG-135 [3/10]
. investigated scheduler register pressure heuristics
. call with Maxim about scheduling algorithm
. still more investigation required
* NEON intrinsics vs assembler libvpx performance difference
investigation [5/10]
. GCC seems to generate poor code for address generation in NEON loads/stores
. maybe some improvements to the intrinsics code would also be possible
Plan:
. write down some conclusions about libvpx performance
. investigate PR60609
. more on TCWG-135
. investigate LP1296676 & LP1296601 ICEs when building the kernel
== Progress ==
Machine descriptions for stack smashing in Aarch64 - TCWG-23 (5/10)
* Completed building QEMU for Aarch64 on Ubuntu 13.10. Ran
regression tests on it.
* Submitted patches for libssp as per Marcus suggestions and got it approved.
PGO support for Aarch64 -TCWG- 179 (2/10)
* Installed "CPU2006" tools in foundation model running open embedded image
and started running benchmarks. Plan is to build it with -PGO next.
Bug fix (2/10)
* Working on reproducing and fixing PR60617.
Misc (1/10)
* AMD Internal meeting and work.
== Plan ==
* Bug fix PR60617.
* Build CPU006 benchmarks with -PGO flag
* Restart PGO bootstrap failure investigations
Hi,
I read in the armv8 architecture reference manual that a number of AArch32 instructions have been obsoleted. Do the current armv7 version of GCC ever generate code containing any of these, without me explicitly writing inline assembly? If it can, how can this be turned off? Just would like to make sure that a C-program (without inline assembly) compiled today for armv7 will run in AArch32 mode when armv8 boards come out.
The following are obsoleted in ARMv8:
A32 SWP and SWPB instructions.
Jazelle (only trivial implementations are supported).
VFP short vectors and asynchronous bounces.
Fast Context Switch Extension (FCSE).
Thanks: Magnus
Magnus Karlsson
Software Development Engineering Manager
LSI Corporation
Box 1024, Knarrarnäsgatan 15
SE-164 21 Kista, Sweden
TEL +46 8 594 607 09
FAX +46 8 594 607 10
CELL +46 73 80 444 88
magnus.karlsson(a)lsi.com