linaro-toolchain

linaro-toolchain@lists.linaro.org

4 participants
5631 discussions

[ACTIVITY] 24 - 28 March 2014

by Kugan

== Progress == - TCWG-413 Spec2006 (7/10) - Investigated compiler error for 481.wrf with FSF 4.8.2. Issue is due to aarch64_cm<cmp><mode> pattern (fcmle and fcmlt supports only #0 as third val). This is already fixed in trunk and Linaro 4.8. - Ran profiling to analyse 4.9 regressions. Started looking into P7Vitterbui which is one of the functions that performs badly. - TCWG-291 CRC (3/10) Came up with a patch for improving vrp for test-case. Some c++ test cases are failing in regression testing with this patch. Looking into it. - TCWG-394 / PR60034 Patch committed and card closed. http://gcc.gnu.org/viewcvs?rev=208949&root=gcc&view=rev == Plan == Continue with Spec2006 and crc

11 years, 5 months

[ACTIVITY] Week 13

by Renato Golin

== Progress == * Android (no card, 10 minutes. ;) - Implemented __builtin___clear_cache in Clang * Kernel (TCWG-417) 6/10 - VLAIS in crypto (last place in kernel) - __builtin__stack_pointer (new builtin) - Discussion in GCC list, named registers might be a better option - Discussion in LLVM list about implementing named registers - Implementing named register variables... - Planning on LAVA testing LLVM kernels with LLVMLinux - __aeabi_memset/cpy/move (both Android and Kernel) will have to be fixed * Libraries (TCWG-125) 2/10 - libc++abi's unwind routines assume (ARM == SjLj) - libc++ doesn't work without them - We'll need to teach it about EHABI (later) * Background 2/10 - Installed ArchLinux on my laptop, took some time to setup - Re-org of LLVM Jira Cards (TCWG-417) - Reviewing some GSoC proposals == Plan == * implement named register variables in LLVM, then Clang * Continue helping LLVMLinux and Milosz to test the LLVM kernel * Time allowing, check CBuild2 for an LLVM build * Two long weeks of holidays...

11 years, 5 months

[ACTIVITY] 24 - 28 March 2014

by Will Newton

== Progress == * Bugfix aarch64 setcontext patch (2/10, TCWG-410) * malloc requirements wiki page (2/10, TCWG-414) * Lots of creating and updating and updating JIRA cards (1/10) * glibc patch review (1/10) * Assorted small patches - ld relasz, gnulib obstack, glibc strtod benchmark (2/10) * Investigate a couple of issues raised by member services and on lists (2/10) == Issues == * None == Plan == * Resurrect glibc malloc benchtest * More glibc benchmark infrastructure work * Check status of glibc ARM port build warnings -- Will Newton Toolchain Working Group, Linaro

11 years, 5 months

[ACTIVITY] March 17-23

by Maxim Kuvyrkov

== Week of March 17th == - STREAM regression (TCWG-388, 4/10) -- Investigated how to prioritize memory references instructions in GCC scheduler to take full advantage of L2 autopretch hardware in certain ARM cores. -- Fixed -fdbg-cnt=sched_insn debug counter along the way. It appear to have been broken since GCC 4.7. - Discussed reg_pressure instruction scheduling with Charlie. (TCWG-135, 1/10) - Various discussions about instruction scheduling in GCC. (1/10) - Together with Michael prepared patch list for GCC contingency plan. (3/10) - Made first-in-series video about tips-and-trick of GCC development. Your critiques are welcome! -- Using GCC debug counters (7m34s): https://www.youtube.com/watch?v=IWRYCOkgL04 == Week of March 24th == - STREAM regression (TCWG-388) -- Get a prototype patch. - Other expected and unexpected tasks that come up. -- Maxim Kuvyrkov www.linaro.org

11 years, 5 months

[Activity] 17-21 March 2014

by Charles Baylis

Last week * one day off [2/10] * NEON scheduling investigation - TCWG-135 [3/10] . investigated scheduler register pressure heuristics . call with Maxim about scheduling algorithm . still more investigation required * NEON intrinsics vs assembler libvpx performance difference investigation [5/10] . GCC seems to generate poor code for address generation in NEON loads/stores . maybe some improvements to the intrinsics code would also be possible Plan: . write down some conclusions about libvpx performance . investigate PR60609 . more on TCWG-135 . investigate LP1296676 & LP1296601 ICEs when building the kernel

11 years, 5 months

[Activity] March 17-21 (2014)

by Venkataramanan Kumar

== Progress == Machine descriptions for stack smashing in Aarch64 - TCWG-23 (5/10) * Completed building QEMU for Aarch64 on Ubuntu 13.10. Ran regression tests on it. * Submitted patches for libssp as per Marcus suggestions and got it approved. PGO support for Aarch64 -TCWG- 179 (2/10) * Installed "CPU2006" tools in foundation model running open embedded image and started running benchmarks. Plan is to build it with -PGO next. Bug fix (2/10) * Working on reproducing and fixing PR60617. Misc (1/10) * AMD Internal meeting and work. == Plan == * Bug fix PR60617. * Build CPU006 benchmarks with -PGO flag * Restart PGO bootstrap failure investigations

11 years, 5 months

Compatiblity of armv7 GCC produced binary on AArch32 on armv8

by Karlsson, Magnus

Hi, I read in the armv8 architecture reference manual that a number of AArch32 instructions have been obsoleted. Do the current armv7 version of GCC ever generate code containing any of these, without me explicitly writing inline assembly? If it can, how can this be turned off? Just would like to make sure that a C-program (without inline assembly) compiled today for armv7 will run in AArch32 mode when armv8 boards come out. The following are obsoleted in ARMv8:  A32 SWP and SWPB instructions.  Jazelle (only trivial implementations are supported).  VFP short vectors and asynchronous bounces.  Fast Context Switch Extension (FCSE). Thanks: Magnus Magnus Karlsson Software Development Engineering Manager LSI Corporation Box 1024, Knarrarnäsgatan 15 SE-164 21 Kista, Sweden TEL +46 8 594 607 09 FAX +46 8 594 607 10 CELL +46 73 80 444 88 magnus.karlsson(a)lsi.com

11 years, 5 months

[ACTIVITY] Week 12

by Yvan Roux

== Issues == * none == Progress == * LRA on AArch32: o TCWG-343 : Make LRA the default for the ARM backend (0/10) - Stop progress on this card, will close it when FSF 4.9 will be released. o TCWG-345 : Analyse performance of LRA for ARM. (4/10) - Spec2K figures on Cortex-a15 Analysis. - re-run benchs in console mode chrubuntu without ASLR + perf tool * Backports review: (2/10) o Start to prepare cortex-a53 backports review * Misc: o Various meetings and slideware (4/10). - Linaro and internal ones. == Next == - continue cortex-a53 review - some backports to do. - continue on TCWG-345

11 years, 5 months

[ACTIVITY] 17 - 21 March 2014

by Will Newton

== Progress == * Worked on getting eglibc git mirror back up and running * Released eglibc 2.19 2014.04 * Respin of glibc aarch64 setcontext patches * Respin of ld aarch64 RELASZ patch * Tidied up, rebased and committed ARM ld pointer equality patch * Work on resurrecting glibc benchmark result graphing script * Holiday on Friday == Issues == * Couple of hours power outage on Monday == Plan == * Get outstanding glibc and binutils patches committed * Reorganise JIRA cards for malloc work * glibc benchmarking -- Will Newton Toolchain Working Group, Linaro

11 years, 5 months

[ACTIVITY] 17 - 21 March 2014

by Omair Javaid

== Progress == * Add support for fork/vfork/exec events/catchpoints in remote gdbserver [TCWG-263] [4/10] -- Debugged catchpoint code and reviewed gdbserver implementation for events. -- Still require a lot of code understanding before actual implementation can start. * Wrote a script that takes two gdb build trees and configuration arguments to test them in native, remote-native and remote-target configurations [TCWG-96] [3/10] * Laptop OS re-install [1/10] * GDB open cards issues review [1/10] * Sick half day off on Friday [1/10] == Plan == * Complete work on TCWG-96. -- Write a script that tests gdb in remote-native configuration using ssh. -- Integrate all testing scripts and test them. -- Update wiki page with updated scripts and how to use them. * Monday Day Off: Pakistan Day 23rd March public holiday roll over.

11 years, 5 months

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