== Progress ==
* Named Register (CARD-1246 2/10)
- Changing type of intrinsics, rebasing patch
* Build & Benchmark (CARD-716 6/10)
- Adding Clang+LLVM builds to CBuild2
- Re-setting APM's testing environment after replacement
* Background (2/10)
- Code review, etc.
- EuroLLVM 2014 outcome analysis, plans for 2015
== Plan ==
* Get Clang+LLVM in CBuild2
* Get Named registers in, then try Clang's parser
* Try SPEC on APM
hi,
For building arm64 kernel, I tried all toolchain released from
http://releases.linaro.org/latest/components/toolchain/binaries/
But it complained about some instructions bad:
/home/work/linux/arch/arm64/include/asm/irqflags.h: Assembler
messages:
/home/work/linux/arch/arm64/include/asm/irqflags.h:49: Error: no
such instruction: `msr daifset,'
/home/work/linux/arch/arm64/include/asm/irqflags.h:68: Error: no
such instruction: `mrs %rax,daif//arch_local_save_flags'
/home/work/linux/arch/arm64/include/asm/irqflags.h:49: Error: no
such instruction: `msr daifset,'
/home/work/linux/arch/arm64/include/asm/irqflags.h:68: Error: no
such instruction: `mrs %rax,daif//arch_local_save_flags'
/home/work/linux/arch/arm64/include/asm/irqflags.h:40: Error: no
such instruction: `msr daifclr,'
/home/work/linux/arch/arm64/include/asm/irqflags.h:68: Error: no
such instruction: `mrs %rax,daif//arch_local_save_flags'
/home/work/linux/arch/arm64/include/asm/irqflags.h:40: Error: no
such instruction: `msr daifclr,'
Could anyone tell how to solve it? thanks!
== Progress==
TCWG-435 needless busy-wait in lowlevellock.c (3/10)
* Patches ready, testing a bit slow & fiddly
TCWG-156 cortex-strings memset (3/10)
* Worried about noisy benchmarks
* Learned to use Lava
* Found some helpful internal docs
* Managed to tweak the code slightly
== Misc ==
Meetings/mail/etc 2/10
(Public) holiday 2/10
== Plan ==
Stop worrying and follow the general curve of the noisy benchmarks
(But also try to convince Maxim's spec scripts + lava to generate some
less noisy results)
Another public holiday next Monday
== Progress ==
* GDB reverse debugging on aarch64
-- Complete decoding of aarch64 data processing immediate instructions.
[TCWG-399] [1/10]
-- Complete decoding of aarch64 data processing register instructions.
[TCWG-402] [1/10]
-- Completed decoding of aarch64 exception and system instructions.
[TCWG-400] [2/10]
-- Further progress on decoding of aarch64 load store instructions.
[TCWG-401] [2/10]
-- Started implementation of aarch64 syscall record/replay. [TCWG-409]
[2/10]
* Sick Day Off on Monday [2/10]
== Plan ==
* GDB reverse debugging on aarch64
-- Further progress on decoding of aarch64 load store instructions.
[TCWG-401]
-- Further progress on aarch64 syscall record/replay. [TCWG-409]
* Public Holiday on 1st May.
Short week, Easter Monday + child care (3/10)
== Issues ==
* Toolchain64 disk still full every 2 days
== Progress ==
* Linaro GCC 4.9 2014.04 release (3/10)
- Branch merge with FSF 4.9.1
- Release tarball available on releases.linaro.org
- Announcement will follow
* Launchpad bugs: (2/10)
o LP #1169164 : including signal.h exposes various PSR_MODE #defines
- Discussed and implemented a fix
- Validation on-going
* Misc:
o Cbuildv1 baby-sitting (1/10)
o Various meetings (1/10).
o Resolved cards :
- TCWG-343. Make LRA the default for the ARM backend
- TCWG-422. LP-bug 1296676 : ICE in assign_by_spills building linux
btrfs module
== Next ==
- One day off (Labor day)
- Submit patch for LP #1169164
- TCWG-345. Analyse performance of LRA for ARM
== Progress ==
PGO - AArch64 (TCWG-179) (4/10)
* Completed SPEC2006 runs ( -O3 + PGO) in chroot + qemu-arm64-saucy
with Linaro branch(4.9).
* Perlbench train run failed, issue with qemu.
* DealII train runs failed due to system libstdc++.so.6 not compatible
with GCC 4.9.
Changing the LD_LIBRARY_PATH to point to the libstdc++.so.6 that
gets built along with GCC 4.9 solves the problem.
* CPU2000 runs are completed my maxim so functional testing of PGO for
spec benchmarks completed.
* Wating on Arm64 hardware to benchmark SPEC2000 and SPEC2006 and
compare against the PGO runs for x86.
Misc (2/10)
* Setup arm64-trusty chroot and built GCC 4.9 compiler
* Maxim 1-1 discussions and set up opennx client
* Checked libssp patch upstream status
* Read about gcc debug counters.
* Upgrade laptop to Ubuntu 14.04 LTS
Short week (22nd and 23rd leave (4/10))
== Plan ==
* Bug fixing.
== Issues==
* Waiting on hardware to Benchmark SPEC2006 PGO runs in hardware.
== Issue ==
* None
== Progress ==
* More tests on shrink-wrap changes (TCWG-133, 6/10).
- Cortex-m3 tests exposes a data flow issue: New BB created after
dfinit does not have correct df_lr info.
- Collect Spec2k benchmarks on X86-64 and ARM.
* Linaro 4.9 binaries release (2/10).
- Update Linaro crosstool-ng config and samples to support 4.9.
- Disable parallel build for gcc manual (pdf & html).
- Prebuild binaries for aarch64:
http://cbuild.validation.linaro.org/binaries/4.9-prerelease-2014.04
* Ping aarch64 fcel patch. But still no comments.
* Fix a trunk build fail issue @r209556.
* One day off (2/10).
== Plans ==
* Send the shrink-wrap related patches for review.
* PING the pending patches.
* Investigate move-loop-invariants heuristics.
== Planed leaves ==
* May 1-3: Labour day holiday.
== Progress ==
* Got Jenkins working with matrix builds so we can utilize all LAVA
slaves. (TCWG 1387 - 3/10)
* Write script to take a list of revisions and then build and test
them all and diff the results. (TCWG 448 - 4/10)
* More experimenting with Kugan's benchmarking branch. (1/10)
* Meetings and Misc (2/10)
== Plan ==
* More work on matrix builds. (TCWG 1387)
* More work on regression test analysis and reporting. (TCWG 448)
== Progress ==
* Short week (21st and 25th are public holidays) (4/10)
* TCWG-447 (5/10)
* Implemented and tested fenv target hooks, necessary built-ins and md
patterns
* Posted RFC patches for review for both arm and aarch64
* http://gcc.gnu.org/ml/gcc-patches/2014-04/msg01743.html
* http://gcc.gnu.org/ml/gcc-patches/2014-04/msg01744.html
* TCWG-413 Spec2006 (1/10)
* Finished the set-up
* On hold for now
== Plan ==
* upstream zero/sign extension elimination activities
* start with literal pool merging
== Progress ==
* Holidays (3 days)
- Clearing emails/tasks backlog
- Some post-trip illness
* AArch64 vs. ARM64
- Comparing performance of both back-ends
* Named Register
- Re-implementing after code review
- http://reviews.llvm.org/D3261
* Time
- CARD-1246 4/10
- Others 6/10
== Plan ==
* Finish named register in LLVM, check Clang
* Continue testing and benchmarking ARM64 back-end
* Have a try at CBuildv2
