== Progress ==
* Validation
- experimenting backport-multijob
- noticed dejagnu problems when trying to kill processes that timed out
- abe and jenkins configs patches / reviews
* Backports/snapshots
- restarted a few validations, to try to recover from disk full issues
* GCC
- neon-testgen.ml removal patch sent upstream
- PR 67591 (ARM v8 Thumb IT blocks deprecated)
- followup on vect.exp's check_vect() support for old arm cores.
- neon-fp16 tests consistency patch posted
- a couple of regressions flagged on trunk
* cortex-strings
- updated aarch64/strlen
* Support
* misc (conf-calls, meetings, emails, ....)
== Next ==
* Validation:
- patch reviews
- look at xenial, docker builders
* Backports
- restart the ones that failed due to disk space issues
* GCC
- monitor trunk regressions
- fix "check_vect" guard in gcc.dg/vect tests
- pr 67591
- advsimd tests
== Progress ==
o Extended Validation (1/10)
- Benchmarking job babysitting.
o Linaro GCC (5/10)
- Merged FSF GCtC 6 branch
- Reviewed backports (very tedious because of infra issues)
- Released June snapshots (5.4 and 6.1)
o Upstream GCC (2/10)
- ARMv8.1 libatomic: Reading and code analysis.
o Misc (2/10)
* Various meetings and discussions.
== Plan ==
o Continue on-going tasks (libatomic, benchamrking)
# Progress #
* TCWG-333, ISA bit treatment in ARM thumb mode. [2/10]
Post a patch to skip the test for thumb mode. Finish the prototype
which shows many issues that I can't overcome. Convince myself that
we should skip the test rather than support that in GDB.
* TCWG-518, ARM range stepping patches. [3/10].
11 of 12 patches are approved, and some of them are already
committed. Need to address one comment that merge to execution paths
into one, which requires some big changes in GDBserver for linux.
* TCWG-651, Support 'catch syscall' in remote for aarch64 and arm.[3/10]
My patches are posted upstream.
* TCWG-556, aarch64 gdb buildbot. [1/10]
They are online.
http://gdb-build.sergiodj.net/builders/Ubuntu-AArch64-m64/http://gdb-build.sergiodj.net/builders/Ubuntu-AArch64-native-gdbserver-m64
* TCWG-654, Build both cross/native arm/aarch64 gcc 5.4.1 to replace
the gcc in my gdb tests. Ongoing. [1/10]
# Plan #
* Follow up all of them above,
* Holiday from Wed - Fri.
--
Yao
== Progress ==
1 day public holidays
IPA VRP
- Implemented a version of early VRP.
- Verified with simple test cases.
- Some test cases are failing in regression testing, looking into it.
- Some design decisions need to be firmed up with the upstream
discussions.
== Plan ==
- Follow upon remaining upstream patches
- IPA VRP
== Progress ==
* Out of office on Monday [2/10]
* Remove exit-on-error flag from CodeGen tests [TCWG-604] [1/10]
- This is a follow-up of TCWG-592: when changing the diag handler,
some of the tests started to fail, so we had to add an exit-on-error
flag to preserve the old behaviour until we can fix the tests.
- Patch fixing one of the AMDGPU tests (PR27761) - in upstream review
- Patch fixing the ARM test (PR27765) - committed upstream
- Submitted a patch removing the flag from llc - accepted upstream,
pending on approval of AMDGPU patch
* Use git worktree in llvm helper scripts [TCWG-587] [2/10]
- Merged. Working on some follow-up stories
- Change interface to llvm-build [TCWG-629] - Modify llvm-build to
accept the targets defined by CMake
- Fix a bug in llvm-env [TCWG-644] - Initially went unnoticed due to
zsh vs bash differences
- Allow cloning from read-only repo [TCWG-652] - This is so non-TCWG
people can use our helper scripts
* ARM: Do not test for CPUs, use SubtargetFeatures [TCWG-623] [5/10]
- Submitted a patch extracting 6 new subtarget features
- Investigating more features that could be extracted
== Plan ==
* OOO on Monday and Tuesday
* ARM: Do not test for CPUs, use SubtargetFeatures [TCWG-623]
== Progress ==
* Validation
- disk full on builders: analysis simply shows that we need more disk :)
- updated "buildapp" job to support building the Linux kernel. We
need more dev packages installed in the *build* schroots for it to
work though.
* Backports/snapshots
- fsf-6 branch merge review
* GCC
- small cleanup in neon* effective-target tests done
- re-testing neon-testgen.ml removal patch
- PR 67591 (ARM v8 Thumb IT blocks deprecated)
- followup on vect.exp's check_vect() support for old arm cores.
* Support
* Misc (conf-calls, meetings, emails, ...)
== Next ==
* Validation:
- patch reviews
* Backports
- restart the ones that failed due do disk space issues
* GCC
- monitor trunk regressions
- fix "check_vect" guard in gcc.dg/vect tests
- hopefully test-neongen.ml removal
- pr 67591
- advsimd tests
== Progress ==
TCWG-611 Initial Thumbv7a support for LLD committed upstream.
Interworking is supported via BLX only. This is enough to run hello
world on a modern arm-linux-gnueabihf target.
TCWG-653 Interworking veneer support for LLD
The existing support for veneers (thunks in LLD terminology) is Mips
specific for non-pi to pi calls. Unless there is something I'm missing
it looks broken in the general case as well.
I have an implementation of minimal veneers that I'm not particular
happy with, but can experiment with to see what the implementation
options are. I am likely to need to go via and RFC first.
Holiday on Friday.
== Next Week ==
Continue working on TCWG-653.
The Linaro Toolchain Working Group (TCWG) is pleased to announce the
2016.06 snapshot of both Linaro GCC 5 and Linaro GCC 6 source
packages.
Linaro GCC 6 monthly snapshot[1] is based on FSF GCC 6.1+svn237469 and
includes performance improvements and bug fixes backported from
mainline GCC. This snapshot contents will be part of the 2016.08
stable[2] quarterly release.
This snapshot tarball is available on:
http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.1-2016.06/
Interesting changes in this GCC source package snapshot include:
* Updates to GCC 6.1+svn237469
* Backport of [Bugfix] [AArch32] PR target/69857 Remove bogus early
return false; in gen_operands_ldrd_strd
* Backport of [AArch32] Add mode to probe_stack set operands
* Backport of [AArch32] arm/ieee754-df.S: Fix typos in comments
* Backport of [AArch32] Do not set ARM_ARCH_ISA_THUMB for armv5
* Backport of [AArch32] Error out for incompatible ARM multilibs
* Backport of [AArch32] Fix costing of sign-extending load in rtx costs
* Backport of [AArch32] Tie operand 1 to operand 0 in AESMC pattern
when fusing AES/AESMC
* Backport of [AArch32] Use proper output modifier for DImode register
in store exclusive patterns
* Backport of [AArch64] 1/4 Add the missing support of vfms_n_f32,
vfmsq_n_f32, vfmsq_n_f64
* Backport of [AArch64] 2/4 Extend vector mutiply by element to all
supported modes
* Backport of [AArch64] 3/4 Reimplement multiply by element to get rid
of inline assembly
* Backport of [AArch64] 4/4 Reimplement vmvn* intrinscis, remove inline assembly
* Backport of [AArch64] Adjust SIMD integer preference
* Backport of [AArch64] Delete ASM_OUTPUT_DEF and fallback to default
.set directive
* Backport of [AArch64] Don't define a macro when a variable will do
* Backport of [AArch64] Fix shift attributes
* Backport of [AArch64] Improve aarch64_case_values_threshold setting
* Backport of [AArch64] print_operand should not fallthrough from
register operand into generic operand
* Backport of [AArch64] Remove aarch64_simd_attr_length_move
* Backport of [AArch64] Set TARGET_OMIT_STRUCT_RETURN_REG to true
* Backport of [AArch64] Simplify ashl<mode>3 expander for SHORT modes
* Backport of [AArch64] Simplify reduc_plus_scal_v2[sd]f sequence
* Backport of [AArch64] Tie operand 1 to operand 0 in AESMC pattern
when AES/AESMC fusion is enabled
* Backport of [AArch64] Update documentation of AArch64 options for GCC6
* Backport of [AArch64] Wrap SHIFT_COUNT_TRUNCATED in brackets
* Backport of [Testsuite] [AArch32] 01/11 Fix typo in vreinterpret.c
test comment
* Backport of [Testsuite] [AArch32] 02/11 Remove useless #ifdefs from
these tests: vmul, vshl and vtst
* Backport of [Testsuite] [AArch32] 03/11 AdvSIMD tests: be more verbose
* Backport of [Testsuite] [AArch32] 04/11 Add forgotten vsliq_n_u64
vsliq_n_s64 tests
* Backport of [Testsuite] [AArch32] 05/11 Add missing
vreinterpretq_p{8,16} tests
* Backport of [Testsuite] [AArch32] 06/11 Add missing vtst_p16 and
vtstq_p16, and vtst_p{8,16} and vtstq_p{8,16} tests
* Backport of [Testsuite] [AArch32] 07/11 Add vget_lane fp16 tests
* Backport of [Testsuite] [AArch32] 08/11 Add missing vstX_lane fp16 tests
* Backport of [Testsuite] [AArch32] 09/11 Add missing vrnd{,a,m,n,p,x} tests
* Backport of [Testsuite] [AArch32] 10/11 Add missing tests for
intrinsics operating on poly64 and poly128 types
* Backport of [Testsuite] [AArch32] 11/11 Add missing tests for
vreinterpret, operating of fp16 type
* Backport of [Testsuite] [AArch64] Fix vmul_elem_1.c on big-endian
* Backport of [Testsuite] [AArch64] Guard float64_t with __aarch64__
* Backport of [Testsuite] [AArch64] Skip cpu-diagnostics tests when
overriding -mcpu
* Backport of [Testsuite] gcc-dg: handle all return values when
shouldfail is set
* Backport of [Testsuite] PR70227, skip g++.dg/lto/pr69589_0.C on
targets without -rdynamic support
* Backport of [Testsuite] PR tree-optimization/57206
* Backport of [Testsuite] Skip tail call tests on Thumb-1 targets
* Backport of [Misc] Increase default value of lto-min-partition to 10000
* Backport of [Misc] introduce --param max-lto-partition for having an
upper bound on partition size
* Backport of [Cleanup] [AArch32] Fix typos in *thumb1_mulsi3 comment
* Backport of [Cleanup] [AArch32] Remove unused TARGET_ARM_V*M macros
* Backport of [Cleanup] [AArch64] Delete obsolete CC_ZESWP and CC_SESWP CC modes
* Backport of [Cleanup] [AArch64] Remove an unused reload hook
* Backport of [Cleanup] Convert conditional compilation on
WORD_REGISTER_OPERATIONS
* Backport of [Cleanup] Remove spurious debug code
* Backport of [Cleanup] Move wrong ChangeLog entry from toplevel to
gcc ChangeLog
* Backport of [Doc] Fix minor doc bugs, signalling typo, major version
changes rare
Linaro GCC 5 monthly snapshot[1] is based on FSF GCC 5.4+svn237113 and
includes performance improvements and bug fixes backported from
mainline GCC. This snapshot contents will be part of the 2016.08
maintenance release.
This snapshot tarball is available on:
http://snapshots.linaro.org/components/toolchain/gcc-linaro/5.4-2016.06/
Interesting changes in this GCC source package snapshot include:
Updates to GCC 5.6+svn237113
* Backport of [Bugfix] [AArch64] [Linaro #2185] PR target/69245: Set
TREE_TARGET_GLOBALS in aarch64_set_current_function when new tree is
the default node to recalculate optab availability
* Backport of [Bugfix] [AArch64] [Linaro #2185] PR target/70002: Make
aarch64_set_current_function play nice with pragma resetting
Subscribe to the important Linaro mailing lists and join our IRC
channels to stay on top of Linaro development.
** Linaro Toolchain Development "mailing list":
http://lists.linaro.org/mailman/listinfo/linaro-toolchain
** Linaro Toolchain IRC channel on irc.freenode.net at @#linaro-tcwg@
* Bug reports should be filed in bugzilla against GCC product:
http://bugs.linaro.org/enter_bug.cgi?product=GCC
* Interested in commercial support? inquire at "Linaro support":
mailto:support@linaro.org
[1]. Source package snapshots are defined when the compiler is only
put through unit-testing and full validation is not performed.
[2]. Stable source package releases are defined as releases where the
full Linaro Toolchain validation plan is executed.
Hi,
I've stumbled across an assembler error message that I don't understand.
bl1/aarch64/bl1_exceptions.S: Assembler messages:
bl1/aarch64/bl1_exceptions.S:53: Error: non-constant expression in
".if" statement
It occurs when building ARM Trusted Firmware with aarch64-linux-gnu-gcc
that ships with Ubuntu 16.04. It does _not_ occur with an older Linaro
toolchain. More details in [1].
The .align directives in the vector_base and vector_entry macros _do_
make a difference. Are they the cause of the problem? Would you
recommend writing the code differently? Or is it a compiler bug?
[1] https://github.com/ARM-software/tf-issues/issues/401
Thanks,
--
Jerome
