Port to microinstance - TCWG-432 [2/10]
* Better reporting/error trapping in dispatch scripts
* Some back and forth with Lab about builder implementation
* Started assessing target stability
* Fixed a few bugs in reporting/bundle generation
Document benchmarking infrastructure - TCWG-496 [2/10]
* All done apart from Jenkins interface
* Need to finish Jenkins interface first...
Generate graphs for benchmarking - TCWG-268 [1/10]
* Generate a bunch of filters and charts to track Coremark-Pro
* Wrote up what I learned about LAVA's reporting interface
EEMBC benchmarks - (no ticket) [2/10]
* Checked over what we had, decided it was probably complete
* Imported to our repos
* Wrote up what I know about this
* Moved Coremark-Pro into its own repo
** Broke some code that had worked by coincidence
** Fixed it
Misc
* Usual meetings/mail/etc
* Some fun with what turned out to be a known bug in the
linaro-media-create now used in main LAVA instance
* Educated guess as to why Jenkins-triggered jobs produced no bundle
** Raised a ticket
** Think I know how to fix on my side
=Plan=
If updated builder becomes available, convert uinstance jobs to use it
Test release benchmark job
Finish backport benchmarking
Document Jenkins interface
Assess target stability
More image reports in microinstance
== This week ==
* Bugzilla 69663 - [ARM] Implement overflow arithmetic standard names (3/10)
- Successfully tested SImode add, sub, and neg overflow patterns
- Developed DImode addv and subv patterns
- Debugging failures in DImode overflow patterns
* TCWG 833 - [ARM] Exploit Wide Add operations when appropriate (2/10)
- Made changes corresponding to upstream review
- Rebased to latest trunk
- Resolved issues with new test cases
- Fixed formatting and style issues
- Resubmitted upstream for final review
- previous review gave conditional support for GCC 7
- Successfully retested
- One remaining expected failure on targets with wide add support
(including aarch64)
- Plan to file a upstream bugzilla
* Misc (1/10)
* Vacation (4/10)
== Next week ==
* Bugzilla 69663 - Debug and resolve DImode pattern failures
* Bugzilla 69008 - Restart investigation
== Progress ==
BUGS (8/10)
- PR69708:
* Posted a patch to fix.
- PR69589:
* Posted a patch to fix.
- PR66726:
* Omitted the patch bu that triggered a bootstrap failure for ppc64.
Reverted the patch and looking into it.
- Misc (2/10)
* gcc/bug list
* Undefined behaviors slides for connect
* Meetings
== Plan ==
* LTO
* bugs
== This Week ==
* LTO/IPA (8/10)
- TCWG-528: patch cross-tested on arm*-*-* and aarch64*-*-*
- Submitted patch upstream to add entry for aarch64 to target-supports.exp
- Experimenting with Kugan's ipa-vrp prototype
- Had a look at ipa-comdat
- Connect slides
* benchmarking (1/10)
- issues with deployment (TICKET-259)
- Using Bernie's workaround for the above issue
* Misc (1/10)
- Meetings
== Next Week ==
- LTO/IPA: tcwg-528, benchmarking, look at ipa-comdat enhancements.
- Investigate tcwg-310 with perf
- Finish connect slides
== Progress ==
* Conference (2/10)
- More EuroLLVM paper reviews, discussions
* Support (5/10)
- Looking at PR16275 (review D17141)
* Background (3/10)
- Code review, meetings, discussions, general support, etc.
- Buildbots broken, bisects, debugging
- Defining and posting Job ad (wanna work with us?)
# Progress #
* Support range stepping on arm-linux. TCWG-518. [4/10]
Preparatory patches are pushed in. Patches are being tested.
* Linaro connect. [3/10]
** Slides are done.
** Collect documents for visa application.
* GDB 7.11 release. TCWG-509. [1/10]
Release branch is created. Discuss on issue related to big endian,
but ARM is the only user of that code.
* Patch review, especially arm tracepoint support. [2/10].
# Plan #
* TCWG-518, upstream patches if tests are OK.
* TCWG-172, continue look at test parity between arm and x86_64.
* Go to London on Wed for visa application.
--
Yao
Hi Linaro Toolchain Group,
I have a question on the ldr instruction selection in the aarch64 backend.
Could someone help me in this regards, please?
I am trying to allow only type A instructions while disabling the type B.
Type A example: ldr x4, [x20,x1] ---> allow
Type B example: ldr x1, [x9,x3,lsl #3] ---> disable
Experiment/My Understanding -
aarch64_classify_address() returns true if rtx X is a valid address. If
allow_reg_index_p=true then it calls aarch64_classify_index().
aarch64_classify_index() identify the address mode of second operand (op1)
and accordingly calculate the shift.
If shift=0 then type A is generated otherwise Type B will be generated.
Thus if (shift != 0) then I am returning 'false' from
aarch64_classify_index().
-------------------------patch---------
--- a/gcc/config/aarch64/aarch64.c
+++ b/gcc/config/aarch64/aarch64.c
@@ -3586,6 +3586,9 @@ aarch64_classify_index (struct aarch64_address_info
*info, rtx x,
if (GET_CODE (index) == SUBREG)
index = SUBREG_REG (index);
+ if (shift != 0)
+ return false;
if ((shift == 0 ||
(shift > 0 && shift <= 3
&& (1 << shift) == GET_MODE_SIZE (mode)))
---------------------------------------
Result -
Before change
ldr x0, [x13,x0,lsl #3]
After Change
lsl x1, x1, #3
ldr x0, [x15,x1]
Question -
How the returning 'false' from aarch64_classify_index() is resulting in the
selection of type A versus type B?
I could not find the function which is taking the decision based on return
from aarch64_classify_address().
Could someone please explain this process or point me to the relevant files
or code?
Please correct me if my understanding is wrong.
Thanks in advance for your time and patience.
--
with regards,
Virendra Kumar Pathak
The Linaro Toolchain Working Group (TCWG) is pleased to announce the
2016.02 snapshot of the Linaro GCC 5 source package.
This monthly snapshot[1] is based on FSF GCC 5.3+svn233233 and
includes performance improvements and bug fixes backported from
mainline GCC. This snapshot contents will be part of the 2016.05
stable [1] quarterly release.
This snapshot tarball is available on:
http://snapshots.linaro.org/components/toolchain/gcc-linaro/5.3-2016.02/
Interesting changes in this GCC source package snapshot include:
* Updates to GCC 5.3+svn233233
* Backport of [Bugfix] [AArch32] PR target/69135: Mark ARMv8 vcvt
instructions as unconditional
* Backport of [Bugfix] [AArch32] PR target/69187 PR target/65624
* Backport of [Bugfix] [AArch32] PR target/69403: Bug in
thumb2_ior_scc_strict_it pattern
* Backport of [Bugfix] [AArch64] PR rtl-optimization/68796: Add
patterns for QImode and HImode comparison with zero
* Backport of [Bugfix] [AArch64] PR target/69176
* Backport of [Bugfix] PR target/69175
* Backport of [Bugfix] PR tree-optimization/67781
* Backport of [AArch32] Remove neon_reinterpret, use casts
* Backport of [AArch32] [RTEMS] Add Cortex-M7 multilib for FPU support
* Backport of [AArch64] Avoid emitting zero immediate as zero register
* Backport of [AArch64] Fix jit crash on aarch64
* Backport of [AArch64] Fix -mcpu/arch=native support for LSE
* Backport of [AArch64] Handle compare of zero_extract form of
TST-immediate in rtx costs
* Backport of [AArch64] Handle CSEL of zero_extended operands in rtx costs
* Backport of [AArch64] Properly reject invalid attribute strings
* Backport of [AArch64] Remove TODO (redundant type conversions) in arm_neon.h
* Backport of [Testsuite] [AArch32] Fix
gcc.c-torture/execute/loop-2b.c execution failure on cortex-m0
* Backport of [Testsuite] [AArch32] Fix g++.dg/pr67989.C test failure
when running with -march or -mcpu
* Backport of [Doc] Remove outdated text from lto.texi
Subscribe to the important Linaro mailing lists and join our IRC
channels to stay on top of Linaro development.
** Linaro Toolchain Development "mailing list":
http://lists.linaro.org/mailman/listinfo/linaro-toolchain
** Linaro Toolchain IRC channel on irc.freenode.net at @#linaro-tcwg@
* Bug reports should be filed in bugzilla against GCC product:
http://bugs.linaro.org/enter_bug.cgi?product=GCC
* Interested in commercial support? inquire at "Linaro support":
mailto:support@linaro.org
[1]. Stable source package releases are defined as releases where the
full Linaro Toolchain validation plan is executed.
[2]. Source package snapshots are defined when the compiler is only
put through unit-testing and full validation is not performed.
Automated release benchmark Jenkins job - TCWG-348 [2/10]
* Drafted a job, it succeeds in dispatching to the uinstance
* Needs testing
Port to microinstance - TCWG-432 [5/10]
* Almost entirely fixing up the CPU2006 -> LAVA reporting
* Should now be able to report CPU2000 results as well
Misc [3/10]
* Mail/meetings/etc
* Connect slides
=Plan=
If builder is available, convert uinstance jobs to use it
Test release benchmark job
Produce image reports in microinstance
Attempt to finish backport benchmarking
Actually finish documentation
== Progress ==
LLDB development
-- Committed patch fixing return value handling on arm-linux-gnueabihf
[TCWG-228]
-- Finished work on handling aggregate types return values on
arm-linux-gnueabihf ABI. [TCWG-228] [5/10]
-- Submitted single and double precision handlers for upstream review.
[TCWG-228]
-- Started work on vector return values and aggregate types return
values with vector elements. [TCWG-228] [2/10]
Miscellaneous [1/10]
-- Meetings, emails, discussions etc.
Public Holiday [2/10]
-- Friday 5th February 2016
== Plan ==
LLDB development
-- Update and commit aggregate type return values on
arm-linux-gnueabihf ABI patch.
-- Investigate issues while stepping over library functions on
arm-linux-gnueabihf
-- Further work on vector return values on arm-linux-gnueabihf ABI
