Hi All,
Does linaro distributes arm-gcc as a pre-built static tool chain
distribution? If yes, where can i download them from. Please point me some
location from where i can download.
--
Thanks & Regards,
M.Srikanth Kumar.
Bug with compiler flag handling - (no ticket) [2/10]
* Coremark-Pro was ignoring compiler flags
* Fixed that, made flag handling consistent across all benchmarks
Release benchmarking via Jenkins - TCWG-348 [1/10]
* Seems to work with test workload
Port to microinstance - TCG-432 [3/10]
* Looked at some inconsistent results
* Worried that one of the Junos may be sick, but unproven for now
Backport benchmarking via Jenkins - TCWG-352 [1/10]
* Finished 'general benchmarking' job
* Switched backport job to build/test cross-compilers
* Recent backport results bundles are corrupted, unable to work out why
Document benchmarking infrastructure - TCWG-496 [1/10]
* Documented Jenkins interface
Misc [2/10]
=Plan=
If updated builder becomes available, convert uinstance job to use it
Continue assessing target stability/looking at inconsistent results
Rework LAVA scripts to permit multiple targets per builder
Hi all,
I download the pre-built toolchain for one of our armv6 board.
https://releases.linaro.org/14.04/components/toolchain/binaries/gcc-linaro-…
After plug it into Yocto as an external toolchain, it failed to install it
correctly.
../meta-linaro/meta-linaro-toolchain/recipes-devtools/external-linaro-toolchain/
external-linaro-toolchain.bb, do_install
| DEBUG: Executing shell function do_install
| cp: cannot stat
`/opt/gcc-linaro-arm-none-eabi-4.8-2014.04_linux/arm-none-eabi/libc/lib/*':
No such file or directory
Any suggestion?
Thanks,
Joel
== This Week ==
* LTO (5/10)
- TCWG-528:
a) addressed Richard's comments.
b) investigating timeout with my patch for g++.dg/torture/pr31863.C
c) using hash_map to prevent decl from getting visited more than
once prevents the issue
d) patch: http://people.linaro.org/~prathamesh.kulkarni/increase-struct-align.diff
- Slides: mostly prepared, few tidbits (and demos) remaining
- Benchmarking: couple more failures due to my silly mistakes, now in progress.
* TCWG-310 (1/10)
- started to look at loop peeling with perf
* Public Holiday (2/10)
- Shiv Jayanti
* Misc (2/10)
- Meetings
- Committed r233426
- Looked at PR69766 caused due to r232622
== Next Week ==
- LTO: TCWG-528, benchmarking, slides
- TCWG-310
# Progress #
* Support range stepping on arm-linux. TCWG-518. [4/10]
My patches causes some regressions but my patches just expose the
existing problem in GDBserver. Fix them and post patches upstream.
* Linaro connect. [2/10]
Go to London for visa application.
* GDB 7.11 release. No issues from my side. The tentative date of
release is Feb 26th.
* Fix GDB reverse debugging tests failures.
** Add more test cases, TCWG-183/TCWG-174. [2/10]
** Fix syscall handling in reverse debugging on ARM and AArch64.
TCWG-532/TCWG-167. [2/10]
# Plan #
* Support range stepping on arm-linux. Continue.
* Fix GDB reverse debugging tests failures. Continue.
* Review upstream patches.
* Go to London to collect my passport.
--
Yao
== Progress ==
* Validation
- AArch64 bare metal validation fixed. Patches waiting approval
- noticed a few failures caused by timeouts and failure to download
testcases. Maybe we are causing too much load on the builders/testers
* Connect preparation
- thoughts on extended validation
* GCC
- upstream monitoring, reported a couple a of regressions
- a few backports
- target attributes backport. Still having problems with our branch
* Misc (conf calls, meetings, emails, ....)
== Next ==
Holidays most of next week
Hi Toolchain Group,
I am trying to study the effect of loop buffer size on loop unrolling & the
way gcc (aarch64) handles this.
To my understanding, Loop Buffer is like i-cache which contains pre-decoded
instruction that can be re-used if branch instruction loopbacks to an
instruction
which is still present in the buffer. For example, in Intel’s Nehalem loop
buffer size is 28 u-ops. In LLVM compiler, it seems LoopMicroOpBufferSize
is for the same purpose.
However, I could not find any parameter/variable inside config/aarch64
representing loop buffer size. I am using Linaro gcc 5.2.1
[Question]
1. Is there any example inside aarch64 (or in general) which uses the loop
buffer size in loop unrolling decision? If yes, could you please mention
the relevant files or code section?
2. Otherwise any guidance/input on adding this support in aarch64 backend
assuming architecture has the loop buffer support.
[My Experiments/Code Browsing]
I have collected following information from code browsing. Please correct
if I missed or misunderstood something.
TARGET_LOOP_UNROLL_ADJUST - This target hook return the number of times a
loop can be unrolled.
This can be used to handle the architecture constraint such number of
memory references inside a loop e.g. ix86_loop_unroll_adjust() &
s390_loop_unroll_adjust().
On the same note, can this be used to handle loop buffer size too?
Without above hook, in loop-unroll.c parameters like
PARAM_MAX_UNROLLED_INSNS (default 200), PARAM_MAX_AVERAGE_UNROLLED_INSNS
(default 80) decides the unrolling factor. e.g. nunroll = PARAM_VALUE
(PARAM_MAX_UNROLLED_INSNS) / loop->ninsns;
In config/aarch64.c, I found align_loops variable in
aarch64_override_options_after_change() function.
I guess this an alignment done before starting the loop header in the
executable. This should not play any role in loop unrolling. Right?
So any guidance on how we can instruct aarch64 backend to utilize loop
buffer size in deciding the loop unrolling factor?
Thanks in advance for your time.
--
with regards,
Virendra Kumar Pathak
== Progress ==
LLDB development
-- Handling aggregate types return values on arm-linux-gnueabihf ABI.
Patch review and committed upstream. [TCWG-228] [1/10]
-- Debugging of stepping issues on chromebook (arm hard float ABI)
[TCWG-230] [2/10]
-- Progress on vector return values and aggregate types return values
with vector elements. [TCWG-531] [2/10]
-- Started work on complex return values and aggregate types return
values with vector elements. [TCWG-531] [2/10]
-- Started writing test cases handling complex and vector return
values and aggregate types return values with vector and complex
elements. [TCWG-531] [2/10]
Miscellaneous [1/10]
-- Meetings, emails, discussions etc.
== Plan ==
LLDB development
-- Finish work on complex return values and aggregate types return
values with vector elements. [TCWG-531]
-- Finish work on vector return values and aggregate types return
values with vector elements. [TCWG-531]
-- Finish work on test cases handling complex and vector return
values. [TCWG-531]
