== Progress ==
* PR24234 - [AArch64] error in backend: fixup value out of range
[TCWG-681] [5/10]
- Wrong instruction size computed for TLS accesses
- Accepted upstream, will commit first thing next week
* [AArch64] Register all AArch64 passes [TCWG-687] [3/10]
- Cleanup that should enable us to run AArch64 passes in llc (incidentally,
this was useful for testing TCWG-681)
- Accepted upstream, will commit first thing next week
* Enable MLx Expansion pass for non-Cortex-A9 targets [TCWG-674] [2/10]
- Started playing with a code snippet so I can understand the pass better
== Plan ==
* Enable MLx Expansion pass for non-Cortex-A9 targets [TCWG-674]
- Brush up the code snippet and do some runs on a Cortex-A15 to see how it
behaves there
* Pick up another AArch64 bug from TCWG-678
* Off on Tue and Wed [4/10]
# Progress #
* TCWG-655, workaround ARM linux kernel ptrace bug on setting VFP
registers. Pedro isn't happy about the workaround, and inclined to
upgrade kernel.
* TCWG-685, GDB 7.12 release. [4/10]
Fix a bug on threads are disappeared when gdb detach. GDB gets
odd task state (disk sleep) from /proc/<pid>/status, and takes some
time understanding what does "disk sleep" mean for a thread to be
exited. Patch is being tested.
* US visa. [1/10]
Get the visa photo, finish the DS-160 form, and make an interview
appointment.
* Misc, [1/10]
# Plan #
* TCWG-685, GDB 7.12 release. More testing on aarch32.
* TCWG-655.
--
Yao
The Linaro Binary Toolchain
============================
The Linaro GCC 5.3-2016.05 Release is now available.
Notice: All Linaro GCC 5 series toolchain users should migrate to the
latest version of the Linaro GCC 5 toolchain in order to mitigate
potential security exposure to CVE-2015-7547. See the NEWS section
below for details.
Download release packages from:
http://releases.linaro.org/components/toolchain/gcc-linaro/5.3-2016.05/http://releases.linaro.org/components/toolchain/binaries/5.3-2016.05/
Previous snapshots and release-candidates are at:
http://snapshots.linaro.org/components/toolchain/binaries/
Previous releases are at:
http://releases.linaro.org/components/toolchain/binaries/
Host Requirements
==================
Linaro officially supports the current and previous Ubuntu LTS
releases (as of the time of this release). This does not mean that
the toolchain will not work on other/older Linux distributions. See
the following for the life-time of Ubuntu LTS releases.
https://wiki.ubuntu.com/Releases
The host system upon which the cross-compiler will run requires a
minimum of glibc 2.14, because of API changes to glibc's memcpy API.
https://bugs.linaro.org/show_bug.cgi?id=1869
Package Versions
=================
Linaro GCC 5.3-2016.05
Linaro glibc 2.21 (linaro/2.21)
Linaro newlib 2.1.0-2014.09 (linaro_newlib-branch)
Linaro binutils 2.25 (linaro_binutils-2_25-branch)
FSF GDB 7.10 (gdb-7.10-branch)
Linaro toolchain package git branches are hosted at:
http://git.linaro.org/?a=project_list&s=toolchain%2F&btnS=Search
NEWS for Linaro GCC 5.3-2016.05
================================
* Increment binutils release date to 2016_02 to reflect the most recent
commit:
commit ef90a4718f535cbe6345b4e7168baea7b1972abf
Author: Matthew Wahab <matthew.wahab(a)arm.com>
Date: Tue Jan 12 16:35:30 2016 +0000
[ARM] Support ARMv8.2 RAS extension.
* Baremetal sysroot names now contain 'newlib' rather than 'glibc'.
* Manifests now contain relative paths rather than absolute paths.
* Now generating proper manifest files.
* Fixed pi requeue support in glibc 2.21 while allowing the existing
2.21 minimum kernel default setting. This was checked into the
linaro/2.21/master branch.
commit a68cafa11c500d8a49a3014c43c5152859d037ae
Author: Adhemerval Zanella <adhemerval.zanella(a)linaro.org>
Date: Tue May 17 10:16:39 2016 -0300
Add runtime check for __ASSUME_REQUEUE_PI (BZ# 18463)
commit 6e5cb616b5b442ce8b2664ad673c0acf42a490ac
Author: Adhemerval Zanella <adhemerval.zanella(a)linaro.org>
Date: Mon May 16 19:01:10 2016 -0300
Remove __ASSUME_SET_ROBUST_LIST
commit 9ac61c0047295696cbcdbc26bdc174c7bd25a3c8
Author: Adhemerval Zanella <adhemerval.zanella(a)linaro.org>
Date: Mon May 16 10:35:25 2016 -0300
Remove __ASSUME_FUTEX_LOCK_PI
* Backported support into GCC for Cortex-A32, Cortex-A35, and Cortex-R8.
* Applied fix for CVE-2015-7547 - A stack-based buffer overflow in
glibc's getaddrinfo() was corrected in glibc 2.23 and backported into
glibc 2.21.
https://sourceware.org/ml/libc-alpha/2016-02/msg00416.html
* ARMv8.1 Instruction Support - ARMv8.1 instructions support was checked
into GCC and binutils. It has been backported into Linaro GCC 5.3
and Linaro binutils 2.25.
* Backported -Bsymbolic-functions into Linaro binutils 2.25.
* Performance related backports from Linaro GCC 5.2-2015.11, Linaro GCC
5.2-2015.12, and Linaro GCC 5.3-2016.01-1, Linaro GCC 5.3-2016.02,
Linaro GCC 5.3-2016.03, and Linaro GCC 5.3-2016.04 have been included.
See the following Linaro GCC snapshots:
http://snapshots.linaro.org/components/toolchain/gcc-linaro/5.2-2015.11/http://snapshots.linaro.org/components/toolchain/gcc-linaro/5.3-2015.12/http://snapshots.linaro.org/components/toolchain/gcc-linaro/5.3-2016.01-1/http://snapshots.linaro.org/components/toolchain/gcc-linaro/5.3-2016.02http://snapshots.linaro.org/components/toolchain/gcc-linaro/5.3-2016.03http://snapshots.linaro.org/components/toolchain/gcc-linaro/5.3-2016.04
Contact Linaro
===============
File bugs at http://bugs.linaro.org
For Linaro member support see http://support.linaro.org
For Linaro community support email linaro-toolchain(a)lists.linaro.org
--
Ryan S. Arnold | Linaro Toolchain Engineering Manager
ryan.arnold(a)linaro.org | ryanarn on #linaro-tcwg @ freenode.irc.net
T: +1-612-424-1861 <+16124241861>
== Progress ==
* IPA VRP and Early VRP
- Posted patch series and revised based on review
- Few patches are accepted; others are waiting for re-review
* Tree VRP
- Converted to use allocpool
* Committed upstream tree-reassoc patch for missed optimization due to
factoring out CONVERT_EXPR in phiopt.
== Plan ==
- Follow upon remaining upstream patches
- IPA VRP
== This Week ==
* TCWG-666 (2/10)
- Working through bootstrap and regtest failures
* TCWG-548 (1/10)
- Running benchmarks on chromebook (cortex-a15)
* Bugs (5/10)
- PR71947: Richard committed fix in vrp which solves this at -O2.
- PR70920: Patch passes bootstrap+test.
- Wrote patch to make ipa-pure-const pass warn for unused return values
- PR71315: Verified works on trunk, exposed another bug in tree-ssa-strlen
* Misc (2/10)
- Recovery from sprint
== Next Week ==
- Continue with TCWG-666 and TCWG-548
- Bugs
# Progress #
* TCWG-518, ARM range stepping patches. [2/10]
The last one is approved, and all patches are committed! Need to
enable range stepping and collect the performance data. Range
stepping should speed up remote debugging.
* TCWG-655, Workaround ARM linux kernel ptrace bug on setting VFP
registers. No response from upstreams.
* TCWG-333, Thumb mode function pointer assignment in GDB. [3/10]
Try a different approach, still causes regressions. I'll ask upstream
how to do it.
* TCWG-547, Change software_single_step interface to return a vector of
address. [4/10].
Patches are done, but need to figure out how to hook them together.
* TCWG-685, GDB 7.12 release. [1/10]
The release will be in Sep, and hopefully it can be done before the
Linaro Connect. Discuss on how/when to pick up 7.12 in Linaro
toolchain release. I am inclined to upgrade GDB in linaro release
from 7.11 to 7.12 in fall or winter.
# Plan #
* Off on Tue and Wed.
* GDB 7.12 release testing for ARM and AArch64.
* US visa application.
--
Yao
== Progress ==
TCWG-680 Some analysis on what non-compiler support would be required
for an llvm based EBC (UEFI) toolchain.
TCWG-612 ARM TLS support in LLD: Initial support and tests for
standard model upstreamed. There is still some work to be done for
corner cases where LLD's relaxations will cause assertion failures.
Static linking also needs some work as the TLS module index needs to
be written into the GOT without a dynamic relocation. I have a
prototype fix that needs cleaning up and tests written.
Did some experiments with static linking and TLS to work out what I'll
need to look at next. Discovered GNU ifunc support when static linking
is not working.
Did some thinking about what would be needed to support C++ exceptions
in LLD for ARM. This is probably the next major chunk of work as
supporting exceptions is needed when static linking against the C
library startup code.
== Plans ==
Plans for next 4 weeks:
On Sabbatical back on the 22nd August. Will probably have limited
access to email if there is anything urgent.
Peter
== Progress ==
* ARM: Different ABI functions based on optimization level [TCWG-669]
- Patch committed upstream
* PR26038 - inline assembly assertion building ARM linux kernel
[TCWG-590] [2/10]
- Patch committed upstream
* PR24234 - [AArch64] error in backend: fixup value out of range
[TCWG-681] [5/10]
- Started investigating
* AArch64 Bugzilla scrub [2/10]
- Closed a couple of bugs that couldn't be reproduced
- Added a few interesting bugs to TCWG-678
* Minor updates to the helper scripts [TCWG-630, TCWG-649] [1/10]
== Plan ==
* PR24234 - [AArch64] error in backend: fixup value out of range [TCWG-681]
- Looks like a tough one :)
Hi Everyone,
I'm looking at the features of a BeagleBone Black. Its /proc/cpuinfo is below.
I think vfpd32 cpu flag means I have 32 D-registers. The cpu flags
neon and vfpv3 flags means I want something more than -mfpu=neon-fp16,
but I'm not sure what that is.
My question is, what GCC ARM option is used when we encounter the
neon, vfpv3 and vfpd32 flags?
Thanks in advance.
**********
$ cat /proc/cpuinfo
processor : 0
model name : ARMv7 Processor rev 2 (v7l)
BogoMIPS : 996.14
Features : half thumb fastmult vfp edsp thumbee neon vfpv3 tls vfpd32
CPU implementer : 0x41
CPU architecture: 7
CPU variant : 0x3
CPU part : 0xc08
CPU revision : 2
Hardware : Generic AM33XX (Flattened Device Tree)
Revision : 0000
Serial : 0000000000000000
Hi Everyone,
I'm having trouble with ARMv8/Aarch64. One is an early Mustang server
board (without CRC or Crypto), and the other is a LeMaker HiKey (with
CRC and Crypto). Both run Linaro:
apm-mustang: $ cat /proc/cpuinfo
Features : fp asimd evtstrm
And:
hikey: $ cat /proc/cpuinfo
Features : fp asimd evtstrm aes pmull sha1 sha2 crc32
According to the GCC folks, we can get better code generation with
-mfpu=neon-fp-armv8
(http://gcc.gnu.org/ml/gcc-help/2016-05/msg00058.html and
https://gcc.gnu.org/onlinedocs/gcc/ARM-Options.html). However, it
results in:
$ g++ -DDEBUG -g3 -O0 -mfpu=neon-fp-armv8 -fPIC -pipe -c cryptlib.cpp
g++: error: unrecognized command line option ‘-mfpu=neon-fp-armv8’
GNUmakefile:753: recipe for target 'cryptlib.o' failed
It looks like -mfpu=neon-fp-armv8 is a GCC 4.9 feature
(http://gcc.gnu.org/gcc-4.9/changes.html), and Linaro supplies GCC
4.9.2:
$ g++ --version
g++ (Debian/Linaro 4.9.2-10) 4.9.2
Copyright (C) 2014 Free Software Foundation, Inc.
I'm wonder why the option is not being consumed by GCC. Are there any
ideas what I should be doing differently?
Thanks in advance.
Jeff
