The Linaro Toolchain Working Group (TCWG) announces the 2016.01-1
snapshot of the Linaro GCC 5 source package.
This package is a respin of 2016.01 source package and contains a fix
for Linaro bugzilla’s PR #2001:
* [AArch64] ICE in final_scan_insn on aarch64-linux-gnu.
This snapshot tarball is available on:
http://snapshots.linaro.org/components/toolchain/gcc-linaro/5.3-2016.01-1/
Original release notes from 2016.01 source package can be find below:
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The Linaro Toolchain Working Group (TCWG) is pleased to announce the
2016.01 snapshot of the Linaro GCC 5 source package.
This monthly snapshot[1] is based on FSF GCC 5.3+svn232321 and
includes performance improvements and bug fixes backported from
mainline GCC. This snapshot contents will be part of the 2016.02
stable [1] quarterly release.
Interesting changes in this GCC source package snapshot include:
* Updates to GCC 5.3+svn232321
* Fixes Linaro Bugzillas: #1982, #1980
* Backport of [BugFix] [AArch32] PR 68149 Fix ICE in unaligned_loaddi split
* Backport of [BugFix] [AArch32] PR target/68214: Delete
IP-reg-clobbering call-through-mem patterns
* Backport of [BugFix] [AArch32] PR target/68390
* Backport of [Bugfix] [AArch64] PR rtl-optimization/68796 Add
compare-of-zero_extract pattern
* Backport of [BugFix] [AArch64] PR target/68696 FAIL:
gcc.target/aarch64/vbslq_u64_1.c scan-assembler-times bif\tv 1
* Backport of [BugFix] PR rtl-optimization/68381
* Backport of [ARMv8.1] [AArch32] Add ACLE feature macro for ARMv8.1
instructions
* Backport of [ARMv8.1] [AArch32] Add ACLE intrinsics vqrdmlah and vqrdmlsh
* Backport of [ARMv8.1] [AArch32] Add ACLE intrinsics vqrdmlah_lane
and vqrdmlsh_lane
* Backport of [ARMv8.1] [AArch32] Add patterns for new instructions
* Backport of [ARMv8.1] [AArch32] Add support for ARMv8.1
* Backport of [ARMv8.1] [AArch32] Multilib support for ARMv8.1.
* Backport of [ARMv8.1] [AArch32] Support ARMv8.1 ARM tests
* Backport of [AArch32] [AArch32] Fix armv8.1 support at configure time
* Backport of [AArch32] Add attribute for compatibility with ARM pipeline models
* Backport of [AArch32] Fix vector TYPE_MODE in streaming-out
* Backport of [AArch64] 1/7 Add support for ARMv8.1 Adv.SIMD instructions
* Backport of [AArch64] 2/7 Add sqrdmah, sqrdmsh instructions
* Backport of [AArch64] 3/7 Add builtins for ARMv8.1 Adv.SIMD instructions
* Backport of [AArch64] 4/7 Add ACLE feature macro for ARMv8.1
Adv.SIMD instructions
* Backport of [AArch64] 5/7 Dejagnu support for ARMv8.1 Adv.SIMD
* Backport of [AArch64] 6/7 Add NEON intrinsics vqrdmlah and vqrdmlsh
* Backport of [AArch64] 7/7 Add NEON intrinsics vqrdmlah_lane and vqrdmlsh_lane
* Backport of [AArch64] Documentation fix for -fpic
* Backport of [AArch64] fix 3/7 Add builtins for ARMv8.1 Adv.SIMD instructions
* Backport of [AArch64] Fix a few failures with LSE enabled
* Backport of [AArch64] Improve add immediate expansion
* Backport of [AArch64] Improve comparison with complex immediates
followed by branch/cset
* Backport of [AArch64] Rework ARMv8.1 command line options
* Backport of [AArch64] Update patterns to support FP zero
* Backport of [AArch64] Use aarch64_sync_memory_operand in
atomic_store<mode> pattern
* Backport of [AArch64] Use vector wide add for mixed-mode adds
* Backport of [Misc] Only restrict pure simplification in mult-extend
subst case, allow other substitutions
* Backport of [Testsuite] [AArch64] Skip big-endian as well for
gcc.target/aarch64/got_mem_hoist_1.c
* Backport of [Testsuite] Make stackalign test LTO proof
* Backport of [Testsuite] Testcase for PR rtl-optimization/68381
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[1]. Stable source package releases are defined as releases where the
full Linaro Toolchain validation plan is executed.
[2]. Source package snapshots are defined when the compiler is only
put through unit-testing and full validation is not performed.
Folks,
I'd like to know the general opinion on this:
https://llvm.org/bugs/show_bug.cgi?id=23529
>From past experience, and my limited point of view, it seems that the
GCC community decided to change the ABI, plotted some runes, conjured
up a broken implementation (whose bugs people will exploit and GCC
will end up keeping them) and pushed distros to follow.
I don't know how much distros were involved in the original design.
Did they request the changes? Or was that an internal change? How do
you guys get to decide when to break the world?
I also don't know how will be your policy towards the bugs that people
started "using". Are you going to force them moving to a more sane
implementation (by issuing compiler/linker errors) or are you going to
support as legacy for the decades to come?
Is there a detailed document describing all the changes, and is the
GCC implementation following that to the letter, or are there still
bugs in the current version? I'm not talking about an email thread,
but an actual document on GCC's docs pages.
All I know is that people in the Clang community waited until GCC's
implementation was stable, but somehow Debian based distros started
moving as if there was something unholy about the previous ABI, and
we've been getting segmentation faults on Hello World!
I don't know much about the changes myself, nor I was involved in the
discussion, but this is now a major pain for release 3.8.0 and I
thought it would be better if I sent an email to Linaro folks and
members (which form most of the ARM GNU developers) instead of going
on the main lists.
That also gives me a bit more freedom to be more candid. I wouldn't
send those questions as they are to the GCC/binutils lists, or people
would kill me. I don't mean any of them as an offence, they are
genuine questions from someone that is not on top of that issue.
cheers,
--renato
Hi Linaro Toochain Group,
I have few questions on glibc+libm w.r.t aarch64.
If possible, please provide some insight, otherwise kindly redirect me to
the concerned person/forum.
1.It seems from the community patches that ARM/Linaro is optimizing glibc
functions such as memcpy/memmove, string for aarch64.
However, looks like some of these (e.g. memcpy/memmov) patches are still
not merged in glibc. Any comment on their availability in glibc?
e.g. https://www.sourceware.org/ml/libc-alpha/2015-12/msg00341.html
2. On the same note, is there any plan for optimizing/tuning libm functions
(e.g. trigonometric) for aarch64?
I could find any matching patches on review board. Please correct me if I
am wrong.
3. Looks like ARM have released an independent version of libm for certain
trigonometric functions.
https://github.com/ARM-software/optimized-routines.
Any plan of these optimization going in glibc's libm? Any comment on its
performance improvement over GNU libm ?
Thanks in advance for your time.
--
with regards,
Virendra Kumar Pathak
== Progress ==
- LTO and TCWG480 (6/10)
* Read and experimented with GCC's LTO codebase.
* Setup archlinux on chromebook and ran coremark with perf
* Read referenced publications
- PR66726 (2/10)
* Rebased the patch
* Regression tested on x86_64 and using Chritsope's setup
* getting ready to post upstream
- Misc (2/10)
* gcc/bug list
* abstract for connect presentation
* Meetings
== Plan ==
* LTO
* bugs
o Teaching activity (2/10)
== Progress ==
o Linaro GCC (4/10)
* Completed backports for 2016.01
* Merged FSF 5 branch into Linaro 5 one
* Delivered 2016.01 Snapshot
* Try to reproduce Linaro PR #1988 with 2016.01.
issue not reproducible
o GCC dev. (3/10)
* Fix armv8.1-a handling at configure time
patch committed upstream in trunk and backported in our branch.
* Investigate TCWG-128 (Thumb2 branch out of range with LTO)
o Misc (1/10)
* Various meetings
== Plan ==
o Look at diff between ABE branches in our validation context
o Continue on-going tasks
Port to microinstance - TCWG-432 [3/10]
* Fallout from attempts to fix race condition
* Various minor fixes - simplifications, better reporting
Backport benchmarking - TCWG-352 [1/10]
* Decoupled 'target triple' from 'toolchain' name
** Immediately, to let me benchmark with Juno-built native gcc
** But this has been causing minor pain for a while
Benchmarking infrastructure documentation - TCWG-496 [1/10]
* Finished drafts of LAVA wrapper and microinstance access docs
Unexpected 1/2 day off [1/10]
Misc [4/10]
* Unusual number of meetings
* Fiddling with my git workflow
* Some thinking about Benchmark-102 for Connect
* Figured out why our SPEC objects were disappearing
== This week ==
* Bugzilla 68543 - [AArch64] Implement overflow arithmetic standard
names (6/10)
- Re-implementing using sign/zero extends as this was not clear from
the documentation
* Bugzilla 69008 - gcc emits unneeded memory access when passing trivial
structs by value (1/10)
- Determined to be structure alignment issue
* Code review of patch posted for Bugzilla 68532 (1/10)
- Completed code review and successfully tested with my vaddw patches
* Bugzilla 67323 - Tested patch for TCWG-318 (non-unit stride loads) (1/10)
- Patch did not generated vld3 so the bug has been reopened
* TCWG-317 - No review feedback yet
* Misc (1/10)
== Next week ==
* Bugzilla 68543 - Complete re-implementation with zero/sign extends and
test
* Bugzilla 69008 - Determine where in compiler issue should be addressed
* USA Holiday (January 18th, MLK Day)
== Progress ==
* Support (5/10)
- Bug triage: reviewing the 300+ bugs on ARM
- closing fixed ones (+35)
- adding deps for meta bugs (kernel, android, ias, chromium) (~15)
- moving to ARM/AArch64 components, etc. (~30)
- Checking a few more kernel patches for Clang support with Arnd
* Plan (3/10)
- Still planning roadmap for 2016/2017
* Background (2/10)
- Code review, meetings, discussions, general support, etc.
# Progress #
* Estimate the effort of GDB kernel-awareness work. Give comments
on formal slides. [1/10]
* GDB inserts breakpoints on the wrong place if these files'
basename is the same. TCWG-491. At least, post a patch to avoid
GDB crash. Reproduced with a simpler case, open PR 19474. [3/10]
* Update document about input interrupt. [1/10]
Done. Patch is committed.
* TCWG-503, fix GDB test case by @progbits -> %progbits. Patch is
posted. [1/10]
* Clean up arm software single step code. [3/10]
In progress. Some patches are committed, but some are still in my
queue. The recent arm software single step change causes a
regression on stepping out of signal handler.
* Think about the GDB slides for Linaro Connect [1/10]
# Plan #
* Look into the arm software single step regression.
* Post the rest of patches for arm software single step clean up.
--
Yao
