CoreSight

coresight@lists.linaro.org

4 participants
2387 discussions

[PATCH] coresight: etm4x: Set skip_power_up in etm4_init_arch_data function

by Mao Jinlong

skip_power_up is used in etm4_init_arch_data when set lpoverride. So need to set the value of it before calling using it. Signed-off-by: Mao Jinlong <quic_jinlmao(a)quicinc.com> --- drivers/hwtracing/coresight/coresight-etm4x-core.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c index c5ea808ea662..8afc07d1dd23 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c @@ -1200,6 +1200,7 @@ static void etm4_init_arch_data(void *info) struct etm4_init_arg *init_arg = info; struct etmv4_drvdata *drvdata; struct csdev_access *csa; + struct device *dev = init_arg->dev; int i; drvdata = dev_get_drvdata(init_arg->dev); @@ -1213,6 +1214,10 @@ static void etm4_init_arch_data(void *info) if (!etm4_init_csdev_access(drvdata, csa)) return; + if (!csa->io_mem || + fwnode_property_present(dev_fwnode(dev), "qcom,skip-power-up")) + drvdata->skip_power_up = true; + /* Detect the support for OS Lock before we actually use it */ etm_detect_os_lock(drvdata, csa); @@ -2040,11 +2045,6 @@ static int etm4_add_coresight_dev(struct etm4_init_arg *init_arg) if (!drvdata->arch) return -EINVAL; - /* TRCPDCR is not accessible with system instructions. */ - if (!desc.access.io_mem || - fwnode_property_present(dev_fwnode(dev), "qcom,skip-power-up")) - drvdata->skip_power_up = true; - major = ETM_ARCH_MAJOR_VERSION(drvdata->arch); minor = ETM_ARCH_MINOR_VERSION(drvdata->arch); -- 2.41.0

1 year, 4 months

Re: [PATCH v4 2/7] arm64: KVM: Use shared area to pass PMU event state to hypervisor

by James Clark

On 05/02/2024 14:52, Marc Zyngier wrote: > On Mon, 05 Feb 2024 14:17:10 +0000, > James Clark <james.clark(a)arm.com> wrote: >> >> On 05/02/2024 13:21, Oliver Upton wrote: >>> On Mon, Feb 05, 2024 at 01:15:36PM +0000, Marc Zyngier wrote: >>>> On Mon, 05 Feb 2024 13:04:51 +0000, >>>> Oliver Upton <oliver.upton(a)linux.dev> wrote: >>>>> >>>>> Unless someone has strong opinions about making this work in protected >>>>> mode, I am happy to see tracing support limited to the 'normal' nVHE >>>>> configuration. The protected feature as a whole is just baggage until >>>>> upstream support is completed. >>>> >>>> Limiting tracing to non-protected mode is a must IMO. Allowing tracing >>>> when pKVM is enabled is a sure way to expose secrets that should >>>> stay... secret. The only exception I can think of is when >>>> CONFIG_NVHE_EL2_DEBUG is enabled, at which point all bets are off. >>> >>> Zero argument there :) I left off the "and PMU" part of what I was >>> saying, because that was a feature that semi-worked in protected mode >>> before VM/VCPU shadowing support landed. >>> >> >> In that case I can hide all this behind CONFIG_NVHE_EL2_DEBUG for pKVM. >> This will also have the effect of disabling PMU again for pKVM because I >> moved that into this new shared area. > > I'm not sure what you have in mind, but dropping PMU support for > non-protected guests when protected-mode is enabled is not an > acceptable outcome. > > Hiding the trace behind a debug option is fine as this is a global > setting that has no userspace impact, but impacting guests isn't. > > M. > Hmmm in that case if there's currently no way to distinguish between normal VMs and pVMs in protected-mode then what I was thinking of probably won't work. I'll actually just leave PMU as it is and only have tracing disabled in protected-mode. My only question now is whether to: * Keep this new shared area and use it for both PMU and trace status (well, for PMU only in protected mode as trace would always be disabled and doesn't actually need any state) * Delete patch 2, add a new normal per-cpu struct just for trace status that's only used in non-protected mode and revert to copying the PMU status into the vCPU on guest switch as it was previously.

1 year, 4 months

Re: [PATCH v4 2/7] arm64: KVM: Use shared area to pass PMU event state to hypervisor

by James Clark

On 05/02/2024 13:21, Oliver Upton wrote: > On Mon, Feb 05, 2024 at 01:15:36PM +0000, Marc Zyngier wrote: >> On Mon, 05 Feb 2024 13:04:51 +0000, >> Oliver Upton <oliver.upton(a)linux.dev> wrote: >>> >>> Unless someone has strong opinions about making this work in protected >>> mode, I am happy to see tracing support limited to the 'normal' nVHE >>> configuration. The protected feature as a whole is just baggage until >>> upstream support is completed. >> >> Limiting tracing to non-protected mode is a must IMO. Allowing tracing >> when pKVM is enabled is a sure way to expose secrets that should >> stay... secret. The only exception I can think of is when >> CONFIG_NVHE_EL2_DEBUG is enabled, at which point all bets are off. > > Zero argument there :) I left off the "and PMU" part of what I was > saying, because that was a feature that semi-worked in protected mode > before VM/VCPU shadowing support landed. > In that case I can hide all this behind CONFIG_NVHE_EL2_DEBUG for pKVM. This will also have the effect of disabling PMU again for pKVM because I moved that into this new shared area. The same place will be used to store the state for normal nVHE and at least then there is some code re-use and flexibility to use trace and PMU for debugging if needed. And the copy on every switch gets deleted.

1 year, 4 months

Re: [PATCH v4 2/7] arm64: KVM: Use shared area to pass PMU event state to hypervisor

by James Clark

On 02/02/2024 22:00, Oliver Upton wrote: > On Thu, Jan 04, 2024 at 04:27:02PM +0000, James Clark wrote: > > [...] > >> diff --git a/arch/arm64/kvm/hyp/nvhe/switch.c b/arch/arm64/kvm/hyp/nvhe/switch.c >> index c50f8459e4fc..89147a9dc38c 100644 >> --- a/arch/arm64/kvm/hyp/nvhe/switch.c >> +++ b/arch/arm64/kvm/hyp/nvhe/switch.c >> @@ -130,13 +130,18 @@ static void __hyp_vgic_restore_state(struct kvm_vcpu *vcpu) >> } >> } >> >> +static struct kvm_pmu_events *kvm_nvhe_get_pmu_events(struct kvm_vcpu *vcpu) >> +{ >> + return &kvm_host_global_state[vcpu->cpu].pmu_events; >> +} >> + >> /* >> * Disable host events, enable guest events >> */ >> #ifdef CONFIG_HW_PERF_EVENTS >> static bool __pmu_switch_to_guest(struct kvm_vcpu *vcpu) >> { >> - struct kvm_pmu_events *pmu = &vcpu->arch.pmu.events; >> + struct kvm_pmu_events *pmu = kvm_nvhe_get_pmu_events(vcpu); >> >> if (pmu->events_host) >> write_sysreg(pmu->events_host, pmcntenclr_el0); >> @@ -152,7 +157,7 @@ static bool __pmu_switch_to_guest(struct kvm_vcpu *vcpu) >> */ >> static void __pmu_switch_to_host(struct kvm_vcpu *vcpu) >> { >> - struct kvm_pmu_events *pmu = &vcpu->arch.pmu.events; >> + struct kvm_pmu_events *pmu = kvm_nvhe_get_pmu_events(vcpu); >> >> if (pmu->events_guest) >> write_sysreg(pmu->events_guest, pmcntenclr_el0); > > This now allows the host to program event counters for a protected > guest. That _might_ be a useful feature behind some debug option, but is > most definitely *not* something we want to do for pVMs generally. Unless I'm missing something, using PMUs on protected guests was added by 722625c6f4c5b ("KVM: arm64: Reenable pmu in Protected Mode"). This change is just a refactor that will allow us to add the same behavior for a similar feature (tracing) without adding yet another copy of some state before the guest switch. > > Do we even need to make this shared data work at all for pKVM? The rest > of the shared data between pKVM and the kernel is system information, > which (importantly) doesn't have any guest context in it. > Probably not, Marc actually mentioned on one of the first versions of that this could be hidden behind a debug flag. To be honest one of the reasons I didn't do that was because I wasn't sure what the appropriate debug setting was. NVHE_EL2_DEBUG didn't seem quite right. DEBUG_KERNEL maybe? Or a new one? And then I suppose I got distracted by trying to make it have feature parity with PMUs and forgot about the debug only thing. > I'm perfectly happy leaving these sorts of features broken for pKVM and > using the 'normal' way of getting percpu data to the nVHE hypervisor > otherwise. > I can do that. But do I also disable PMU at the same time in a new commit? Now that both PMU and tracing is working maybe it would be a waste to throw that away and hiding it behind an option is better. Or I can leave the PMU as it is and just keep tracing disabled in pKVM. I don't mind either way, my main goal was to get exclude/include guest tracing working for normal VMs. For pKVM I don't have a strong opinion.

1 year, 4 months

[PATCH v6 00/10] Add support to configure TPDM CMB subunit

by Tao Zhang

Introduction of TPDM CMB(Continuous Multi Bit) subunit CMB subunit is responsible for creating a dataset element, and is also optionally responsible for packing it to fit multiple elements on a single ATB transfer if possible in the configuration. The TPDM Core Datapath requests timestamps be stored by the TPDA and then delivering ATB sized data (depending on ATB width and element size, this could be smaller or larger than a dataset element) to the ATB Mast FSM. The CMB makes trace elements in two modes. In �continuous� mode, every valid data cycle creates an element. In �trace on change� mode, when valid data changes on the bus, a trace element is created. In continuous mode, all cycles where this condition is true create trace elements. In trace on change mode, a data element is only when the previously sampled input is different from the current sampled input. The CMB subunit must be configured prior to enablement. This series adds support for TPDM to configure the configure CMB subunit. Once this series patches are applied properly, the new tpdm nodes for should be observed at the tpdm path /sys/bus/coresight/devices/tpdm* which supports CMB subunit. e.g. root@qemuarm64:/sys/devices/platform/soc@0/684c000.tpdm/tpdm0# ls -l -rw-r--r-- 1 root root 4096 Jan 1 00:00 cmb_mode drwxr-xr-x 2 root root 0 Jan 1 00:00 cmb_msr drwxr-xr-x 2 root root 0 Jan 1 00:00 cmb_patt drwxr-xr-x 2 root root 0 Jan 1 00:00 cmb_trig_patt -rw-r--r-- 1 root root 4096 Jan 1 00:00 cmb_trig_ts -rw-r--r-- 1 root root 4096 Jan 1 00:00 cmb_ts_all drwxr-xr-x 2 root root 0 Jan 1 00:00 connections drwxr-xr-x 2 root root 0 Jan 1 00:00 dsb_edge drwxr-xr-x 2 root root 0 Jan 1 00:00 dsb_msr drwxr-xr-x 2 root root 0 Jan 1 00:00 dsb_patt drwxr-xr-x 2 root root 0 Jan 1 00:00 dsb_trig_patt -rw-r--r-- 1 root root 4096 Jan 1 00:00 enable_source --w------- 1 root root 4096 Jan 1 00:00 integration_test drwxr-xr-x 2 root root 0 Ja? 1 00:00 power --w------- 1 root root 4096 Jan 1 00:00 reset_dataset lrwxrwxrwx 1 root root 0 Apr 5 2021 subsystem -> ../../../../../bus/coresight -rw-r--r-- 1 root root 4096 Apr 5 2021 uevent -r--r--r-- 1 root root 4096 Jan 1 00:00 waiting_for_supplier We can use the commands are similar to the below to configure the TPDMs which support CMB subunit. Enable coresight sink first. echo 1 > /sys/bus/coresight/devices/tmc_etf0/enable_sink echo 1 > /sys/bus/coresight/devices/tpdm0/reset_dataset echo 1 > /sys/bus/coresight/devices/tpdm0/cmb_mode echo 1 > /sys/bus/coresight/devices/tpdm0/cmb_patt/enable_ts echo 0xFFFFFFFF > /sys/bus/coresight/devices/tpdm0/cmb_patt/tpmr0 echo 0 > /sys/bus/coresight/devices/tpdm0/cmb_trig_ts echo 0xFFFFFFFF > /sys/bus/coresight/devices/tpdm0/cmb_trig_patt/xpr1 echo 1 > /sys/bus/coresight/devices/tpdm0/enable_source codelinaro link: https://git.codelinaro.org/clo/linux-kernel/coresight/-/commits/tpdm-cmb-v6 Changes in V6: 1. Clear all the relevant fields before setting them in the function "tpda_set_element_size". In patch#5. -- Suzuki K Poulose 2. Leave a space after/before '/*' & '*/'. In patch#7 #8. -- Suzuki K Poulose Changes in V5: 1. Return directly to refine the process of "tpdm_enable_dsb" and "tpdm_disable_dsb" if the TPDM does not support DSB dataset. -- Suzuki K Poulose 2. Change the new property name from "qcom,cmb-element-size" to "qcom,cmb-element-bits". And update the property name to the new tpdm example which supports the CMB dataset. -- Krzysztof 3. Drop unnecessary () around the drvdata member access in patch#5. -- Suzuki K Poulose 4. Replace the error code "-EEXIST" with the port number in detecting multiple TPDMs on one input port. In patch#5. -- Suzuki K Poulose 5. Due to the modification of the new property name, the searched property name was changed from "qcom,cmb-element-size" to "qcom,cmb-element-bits". In patch#5. 6. Replace the judgement "tpdm_has_cmb_dataset(drvdata)" with "drvdata->cmb" in the function "tpdm_reset_datasets". In patch#6. -- Suzuki K Poulose 7. Drop unnecessary () around kstrtoul() in the function "cmb_mode_store". In patch#6. -- Suzuki K Poulose 8. Update the date and the kernel version in the Document. -- Suzuki K Poulose 9. Initialize the return value to "-EINVAL" and remove the unnecessary code in the function "enable_ts_show". In patch#8. -- Suzuki K Poulose 10. Replace spin lock/unlock with guard(spinlock). In patch#8. -- Suzuki K Poulose 11. Drop _rw from the macro "tpdm_patt_enable_ts_rw". In patch#8. -- Suzuki K Poulose Changes in V4: 1. Replace spin lock/unlock to avoid forgetting to unlock when the function exits. -- Suzuki K Poulose 2. Move the helper "tpdm_has_dsb_dataset" to the header file. -- Suzuki K Poulose 3. Fix the incorrect property of the sample in the documents. -- James Clark 4. Clear the dsb/cmb element size directly in the clear helper. -- Suzuki K Poulose 5. Correct the comment of "tpdm_read_element_size". -- Suzuki K Poulose 6. Call the helper "tpdm_has_dsb/cmb_dataset" in TPDA driver to check what dataset the TPDM supports. -- Suzuki K Poulose 7. Refine the dsb/cmb dataset support check in enable/disable functions. -- Suzuki K Poulose 8. Get rid of redundant code in function "set_cmb_tier". -- Suzuki K Poulose 9. Since one SysFs file should follow "one value", use "dev_ext_attribute" to instead of the previous "enable_ts" Sysfs file approach. -- Suzuki K Poulose 10. Change the kernel version to 6.9 for the MSR related SysFs file. -- James Clark 11. Refine the function "tpdm_simple_dataset_store". -- Suzuki K Poulose Changes in V3: 1. Add 8-bit support to the description in the TPDM devicetree document. -- Rob Herring 2. Change how the result is produced in "tpdm_read_element_size". -- James Clark 3. Calling "tpdm_clear_element_size" at the beginning of "tpda_enable_port". -- James Clark 4. Use "dsb_esize" and "cmb_esize" to determine whether multiple TPDMs are detected on a TPDA input port in "tpda_get_element_size". -- James Clark 5. Modify the judgment logic in "tpda_enable_port". -- James Clark 6. Add more description of "cmb_mode" to TPDM SysFS document. -- James Clark Changes in V2: 1. Optimizate and modify this patch series based on the patch series "Add support to configure TPDM CMB subunit". 2. Modify the functions that read the element size of DSB/CMB in TPDA driver. Tao Zhang (10): coresight-tpdm: Optimize the store function of tpdm simple dataset coresight-tpdm: Optimize the useage of tpdm_has_dsb_dataset dt-bindings: arm: qcom,coresight-tpdm: Add support for CMB element size coresight-tpdm: Add CMB dataset support coresight-tpda: Add support to configure CMB element coresight-tpdm: Add support to configure CMB coresight-tpdm: Add pattern registers support for CMB coresight-tpdm: Add timestamp control register support for the CMB dt-bindings: arm: qcom,coresight-tpdm: Add support for TPDM CMB MSR register coresight-tpdm: Add msr register support for CMB .../testing/sysfs-bus-coresight-devices-tpdm | 87 ++++ .../bindings/arm/qcom,coresight-tpdm.yaml | 35 ++ drivers/hwtracing/coresight/coresight-tpda.c | 125 +++-- drivers/hwtracing/coresight/coresight-tpda.h | 6 + drivers/hwtracing/coresight/coresight-tpdm.c | 455 ++++++++++++++++-- drivers/hwtracing/coresight/coresight-tpdm.h | 113 +++++ 6 files changed, 729 insertions(+), 92 deletions(-) -- 2.17.1

1 year, 5 months

Re: [PATCH V4 00/11] perf/core: Add ability for an event to "pause" or "resume" AUX area tracing

by James Clark

On 31/01/2024 16:53, Ian Rogers wrote: > On Mon, Jan 29, 2024 at 4:49 AM Adrian Hunter <adrian.hunter(a)intel.com> wrote: >> >> On 11/01/24 10:19, Adrian Hunter wrote: >>> Hi >>> >>> Hardware traces, such as instruction traces, can produce a vast amount of >>> trace data, so being able to reduce tracing to more specific circumstances >>> can be useful. >>> >>> The ability to pause or resume tracing when another event happens, can do >>> that. >>> >>> These patches add such a facilty and show how it would work for Intel >>> Processor Trace. >>> >>> Maintainers of other AUX area tracing implementations are requested to >>> consider if this is something they might employ and then whether or not >>> the ABI would work for them. >>> >>> Changes to perf tools are now (since V4) fleshed out. >>> >>> >>> Changes in V4: >>> >>> perf/core: Add aux_pause, aux_resume, aux_start_paused >>> Rename aux_output_cfg -> aux_action >>> Reorder aux_action bits from: >>> aux_pause, aux_resume, aux_start_paused >>> to: >>> aux_start_paused, aux_pause, aux_resume >>> Fix aux_action bits __u64 -> __u32 >>> >>> coresight: Have a stab at support for pause / resume >>> Dropped >>> >>> perf tools >>> All new patches >>> >>> Changes in RFC V3: >>> >>> coresight: Have a stab at support for pause / resume >>> 'mode' -> 'flags' so it at least compiles >>> >>> Changes in RFC V2: >>> >>> Use ->stop() / ->start() instead of ->pause_resume() >>> Move aux_start_paused bit into aux_output_cfg >>> Tighten up when Intel PT pause / resume is allowed >>> Add an example of how it might work for CoreSight >> >> Any more comments? > > I think the tools side looks good. The parsing changes match the > existing style. I wonder if it wouldn't be better to handle the valid > strings (pause, resume, etc.) in the lexer rather than a separate > parse function, but the pattern used matches the existing one. You can > have my Acked-by on the tools changes, although the subtleties of ARM > PMUs makes me somewhat nervous in this regard. > > Thanks, > Ian Acked-by: James Clark <james.clark(a)arm.com> I will get round to adding the Coresight support at some point. I checked the new parsing in this version and it seems to work ok.

1 year, 5 months

[PATCH v4 2/7] arm64: KVM: Use shared area to pass PMU event state to hypervisor

by James Clark

Currently the state of the PMU events is copied into the VCPU struct before every VCPU run. This isn't scalable if more data for other features needs to be added too. So make a writable area that's shared between the host and the hypervisor to store this state. Normal per-cpu constructs can't be used because although the framework exists for the host to write to the hypervisor's per-cpu structs, this only works until the protection is enabled. And for the other way around, no framework exists for the hypervisor to access the host's size and layout of per-cpu data. Instead of making a new framework for the hypervisor to access the host's per-cpu data that would only be used once, just define the new shared area as an array with NR_CPUS elements. This also reduces the amount of sharing that needs to be done, because unlike this array, the per-cpu data isn't contiguous. Signed-off-by: James Clark <james.clark(a)arm.com> --- arch/arm64/include/asm/kvm_host.h | 8 ++++++++ arch/arm64/kernel/image-vars.h | 1 + arch/arm64/kvm/arm.c | 16 ++++++++++++++-- arch/arm64/kvm/hyp/nvhe/setup.c | 11 +++++++++++ arch/arm64/kvm/hyp/nvhe/switch.c | 9 +++++++-- arch/arm64/kvm/pmu.c | 4 +--- include/kvm/arm_pmu.h | 17 ----------------- 7 files changed, 42 insertions(+), 24 deletions(-) diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm_host.h index 824f29f04916..93d38ad257ed 100644 --- a/arch/arm64/include/asm/kvm_host.h +++ b/arch/arm64/include/asm/kvm_host.h @@ -466,6 +466,14 @@ struct kvm_cpu_context { struct kvm_vcpu *__hyp_running_vcpu; }; +struct kvm_host_global_state { + struct kvm_pmu_events { + u32 events_host; + u32 events_guest; + } pmu_events; +} ____cacheline_aligned; +extern struct kvm_host_global_state kvm_host_global_state[NR_CPUS]; + struct kvm_host_data { struct kvm_cpu_context host_ctxt; }; diff --git a/arch/arm64/kernel/image-vars.h b/arch/arm64/kernel/image-vars.h index 119ca121b5f8..1a9dbb02bb4a 100644 --- a/arch/arm64/kernel/image-vars.h +++ b/arch/arm64/kernel/image-vars.h @@ -59,6 +59,7 @@ KVM_NVHE_ALIAS(alt_cb_patch_nops); /* Global kernel state accessed by nVHE hyp code. */ KVM_NVHE_ALIAS(kvm_vgic_global_state); +KVM_NVHE_ALIAS(kvm_host_global_state); /* Kernel symbols used to call panic() from nVHE hyp code (via ERET). */ KVM_NVHE_ALIAS(nvhe_hyp_panic_handler); diff --git a/arch/arm64/kvm/arm.c b/arch/arm64/kvm/arm.c index 4796104c4471..bd6b2eda5f4f 100644 --- a/arch/arm64/kvm/arm.c +++ b/arch/arm64/kvm/arm.c @@ -47,6 +47,20 @@ static enum kvm_mode kvm_mode = KVM_MODE_DEFAULT; +/* + * Host state that isn't associated with any VCPU, but will affect any VCPU + * running on a host CPU in the future. This remains writable from the host and + * readable in the hyp. + * + * PER_CPU constructs aren't compatible between the hypervisor and the host so + * just define it as a NR_CPUS array. DECLARE_KVM_NVHE_PER_CPU works in both + * places, but not after the hypervisor protection is initialised. After that, + * kvm_arm_hyp_percpu_base isn't accessible from the host, so even if the + * kvm_host_global_state struct was shared with the host, the per-cpu offset + * can't be calculated without sharing even more data with the host. + */ +struct kvm_host_global_state kvm_host_global_state[NR_CPUS]; + DECLARE_KVM_HYP_PER_CPU(unsigned long, kvm_hyp_vector); DEFINE_PER_CPU(unsigned long, kvm_arm_hyp_stack_page); @@ -1016,8 +1030,6 @@ int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu) kvm_vgic_flush_hwstate(vcpu); - kvm_pmu_update_vcpu_events(vcpu); - /* * Ensure we set mode to IN_GUEST_MODE after we disable * interrupts and before the final VCPU requests check. diff --git a/arch/arm64/kvm/hyp/nvhe/setup.c b/arch/arm64/kvm/hyp/nvhe/setup.c index b5452e58c49a..3e45cc10ba96 100644 --- a/arch/arm64/kvm/hyp/nvhe/setup.c +++ b/arch/arm64/kvm/hyp/nvhe/setup.c @@ -159,6 +159,17 @@ static int recreate_hyp_mappings(phys_addr_t phys, unsigned long size, if (ret) return ret; + /* + * Similar to kvm_vgic_global_state, but this one remains writable by + * the host rather than read-only. Used to store per-cpu state about the + * host that isn't associated with any particular VCPU. + */ + prot = pkvm_mkstate(KVM_PGTABLE_PROT_RW, PKVM_PAGE_SHARED_OWNED); + ret = pkvm_create_mappings(&kvm_host_global_state, + &kvm_host_global_state + 1, prot); + if (ret) + return ret; + ret = create_hyp_debug_uart_mapping(); if (ret) return ret; diff --git a/arch/arm64/kvm/hyp/nvhe/switch.c b/arch/arm64/kvm/hyp/nvhe/switch.c index c50f8459e4fc..89147a9dc38c 100644 --- a/arch/arm64/kvm/hyp/nvhe/switch.c +++ b/arch/arm64/kvm/hyp/nvhe/switch.c @@ -130,13 +130,18 @@ static void __hyp_vgic_restore_state(struct kvm_vcpu *vcpu) } } +static struct kvm_pmu_events *kvm_nvhe_get_pmu_events(struct kvm_vcpu *vcpu) +{ + return &kvm_host_global_state[vcpu->cpu].pmu_events; +} + /* * Disable host events, enable guest events */ #ifdef CONFIG_HW_PERF_EVENTS static bool __pmu_switch_to_guest(struct kvm_vcpu *vcpu) { - struct kvm_pmu_events *pmu = &vcpu->arch.pmu.events; + struct kvm_pmu_events *pmu = kvm_nvhe_get_pmu_events(vcpu); if (pmu->events_host) write_sysreg(pmu->events_host, pmcntenclr_el0); @@ -152,7 +157,7 @@ static bool __pmu_switch_to_guest(struct kvm_vcpu *vcpu) */ static void __pmu_switch_to_host(struct kvm_vcpu *vcpu) { - struct kvm_pmu_events *pmu = &vcpu->arch.pmu.events; + struct kvm_pmu_events *pmu = kvm_nvhe_get_pmu_events(vcpu); if (pmu->events_guest) write_sysreg(pmu->events_guest, pmcntenclr_el0); diff --git a/arch/arm64/kvm/pmu.c b/arch/arm64/kvm/pmu.c index a243934c5568..136d5c6c1916 100644 --- a/arch/arm64/kvm/pmu.c +++ b/arch/arm64/kvm/pmu.c @@ -6,8 +6,6 @@ #include <linux/kvm_host.h> #include <linux/perf_event.h> -static DEFINE_PER_CPU(struct kvm_pmu_events, kvm_pmu_events); - /* * Given the perf event attributes and system type, determine * if we are going to need to switch counters at guest entry/exit. @@ -28,7 +26,7 @@ static bool kvm_pmu_switch_needed(struct perf_event_attr *attr) struct kvm_pmu_events *kvm_get_pmu_events(void) { - return this_cpu_ptr(&kvm_pmu_events); + return &kvm_host_global_state[smp_processor_id()].pmu_events; } /* diff --git a/include/kvm/arm_pmu.h b/include/kvm/arm_pmu.h index 4b9d8fb393a8..71a835970ab5 100644 --- a/include/kvm/arm_pmu.h +++ b/include/kvm/arm_pmu.h @@ -18,14 +18,8 @@ struct kvm_pmc { struct perf_event *perf_event; }; -struct kvm_pmu_events { - u32 events_host; - u32 events_guest; -}; - struct kvm_pmu { struct irq_work overflow_work; - struct kvm_pmu_events events; struct kvm_pmc pmc[ARMV8_PMU_MAX_COUNTERS]; int irq_num; bool created; @@ -79,17 +73,6 @@ void kvm_vcpu_pmu_resync_el0(void); #define kvm_vcpu_has_pmu(vcpu) \ (vcpu_has_feature(vcpu, KVM_ARM_VCPU_PMU_V3)) -/* - * Updates the vcpu's view of the pmu events for this cpu. - * Must be called before every vcpu run after disabling interrupts, to ensure - * that an interrupt cannot fire and update the structure. - */ -#define kvm_pmu_update_vcpu_events(vcpu) \ - do { \ - if (!has_vhe() && kvm_vcpu_has_pmu(vcpu)) \ - vcpu->arch.pmu.events = *kvm_get_pmu_events(); \ - } while (0) - /* * Evaluates as true when emulating PMUv3p5, and false otherwise. */ -- 2.34.1

1 year, 5 months

[PATCH v5 00/10] Add support to configure TPDM CMB subunit

by Tao Zhang

Introduction of TPDM CMB(Continuous Multi Bit) subunit CMB subunit is responsible for creating a dataset element, and is also optionally responsible for packing it to fit multiple elements on a single ATB transfer if possible in the configuration. The TPDM Core Datapath requests timestamps be stored by the TPDA and then delivering ATB sized data (depending on ATB width and element size, this could be smaller or larger than a dataset element) to the ATB Mast FSM. The CMB makes trace elements in two modes. In �continuous� mode, every valid data cycle creates an element. In �trace on change� mode, when valid data changes on the bus, a trace element is created. In continuous mode, all cycles where this condition is true create trace elements. In trace on change mode, a data element is only when the previously sampled input is different from the current sampled input. The CMB subunit must be configured prior to enablement. This series adds support for TPDM to configure the configure CMB subunit. Once this series patches are applied properly, the new tpdm nodes for should be observed at the tpdm path /sys/bus/coresight/devices/tpdm* which supports CMB subunit. e.g. root@qemuarm64:/sys/devices/platform/soc@0/684c000.tpdm/tpdm0# ls -l -rw-r--r-- 1 root root 4096 Jan 1 00:00 cmb_mode drwxr-xr-x 2 root root 0 Jan 1 00:00 cmb_msr drwxr-xr-x 2 root root 0 Jan 1 00:00 cmb_patt drwxr-xr-x 2 root root 0 Jan 1 00:00 cmb_trig_patt -rw-r--r-- 1 root root 4096 Jan 1 00:00 cmb_trig_ts -rw-r--r-- 1 root root 4096 Jan 1 00:00 cmb_ts_all drwxr-xr-x 2 root root 0 Jan 1 00:00 connections drwxr-xr-x 2 root root 0 Jan 1 00:00 dsb_edge drwxr-xr-x 2 root root 0 Jan 1 00:00 dsb_msr drwxr-xr-x 2 root root 0 Jan 1 00:00 dsb_patt drwxr-xr-x 2 root root 0 Jan 1 00:00 dsb_trig_patt -rw-r--r-- 1 root root 4096 Jan 1 00:00 enable_source --w------- 1 root root 4096 Jan 1 00:00 integration_test drwxr-xr-x 2 root root 0 Ja? 1 00:00 power --w------- 1 root root 4096 Jan 1 00:00 reset_dataset lrwxrwxrwx 1 root root 0 Apr 5 2021 subsystem -> ../../../../../bus/coresight -rw-r--r-- 1 root root 4096 Apr 5 2021 uevent -r--r--r-- 1 root root 4096 Jan 1 00:00 waiting_for_supplier We can use the commands are similar to the below to configure the TPDMs which support CMB subunit. Enable coresight sink first. echo 1 > /sys/bus/coresight/devices/tmc_etf0/enable_sink echo 1 > /sys/bus/coresight/devices/tpdm0/reset_dataset echo 1 > /sys/bus/coresight/devices/tpdm0/cmb_mode echo 1 > /sys/bus/coresight/devices/tpdm0/cmb_patt/enable_ts echo 0xFFFFFFFF > /sys/bus/coresight/devices/tpdm0/cmb_patt/tpmr0 echo 0 > /sys/bus/coresight/devices/tpdm0/cmb_trig_ts echo 0xFFFFFFFF > /sys/bus/coresight/devices/tpdm0/cmb_trig_patt/xpr1 echo 1 > /sys/bus/coresight/devices/tpdm0/enable_source codelinaro link: https://git.codelinaro.org/clo/linux-kernel/coresight/-/commits/tpdm-cmb-v5 Changes in V5: 1. Return directly to refine the process of "tpdm_enable_dsb" and "tpdm_disable_dsb" if the TPDM does not support DSB dataset. -- Suzuki K Poulose 2. Change the new property name from "qcom,cmb-element-size" to "qcom,cmb-element-bits". And update the property name to the new tpdm example which supports the CMB dataset. -- Krzysztof 3. Drop unnecessary () around the drvdata member access in patch#5. -- Suzuki K Poulose 4. Replace the error code "-EEXIST" with the port number in detecting multiple TPDMs on one input port. In patch#5. -- Suzuki K Poulose 5. Due to the modification of the new property name, the searched property name was changed from "qcom,cmb-element-size" to "qcom,cmb-element-bits". In patch#5. 6. Replace the judgement "tpdm_has_cmb_dataset(drvdata)" with "drvdata->cmb" in the function "tpdm_reset_datasets". In patch#6. -- Suzuki K Poulose 7. Drop unnecessary () around kstrtoul() in the function "cmb_mode_store". In patch#6. -- Suzuki K Poulose 8. Update the date and the kernel version in the Document. -- Suzuki K Poulose 9. Initialize the return value to "-EINVAL" and remove the unnecessary code in the function "enable_ts_show". In patch#8. -- Suzuki K Poulose 10. Replace spin lock/unlock with guard(spinlock). In patch#8. -- Suzuki K Poulose 11. Drop _rw from the macro "tpdm_patt_enable_ts_rw". In patch#8. -- Suzuki K Poulose Changes in V4: 1. Replace spin lock/unlock to avoid forgetting to unlock when the function exits. -- Suzuki K Poulose 2. Move the helper "tpdm_has_dsb_dataset" to the header file. -- Suzuki K Poulose 3. Fix the incorrect property of the sample in the documents. -- James Clark 4. Clear the dsb/cmb element size directly in the clear helper. -- Suzuki K Poulose 5. Correct the comment of "tpdm_read_element_size". -- Suzuki K Poulose 6. Call the helper "tpdm_has_dsb/cmb_dataset" in TPDA driver to check what dataset the TPDM supports. -- Suzuki K Poulose 7. Refine the dsb/cmb dataset support check in enable/disable functions. -- Suzuki K Poulose 8. Get rid of redundant code in function "set_cmb_tier". -- Suzuki K Poulose 9. Since one SysFs file should follow "one value", use "dev_ext_attribute" to instead of the previous "enable_ts" Sysfs file approach. -- Suzuki K Poulose 10. Change the kernel version to 6.9 for the MSR related SysFs file. -- James Clark 11. Refine the function "tpdm_simple_dataset_store". -- Suzuki K Poulose Changes in V3: 1. Add 8-bit support to the description in the TPDM devicetree document. -- Rob Herring 2. Change how the result is produced in "tpdm_read_element_size". -- James Clark 3. Calling "tpdm_clear_element_size" at the beginning of "tpda_enable_port". -- James Clark 4. Use "dsb_esize" and "cmb_esize" to determine whether multiple TPDMs are detected on a TPDA input port in "tpda_get_element_size". -- James Clark 5. Modify the judgment logic in "tpda_enable_port". -- James Clark 6. Add more description of "cmb_mode" to TPDM SysFS document. -- James Clark Changes in V2: 1. Optimizate and modify this patch series based on the patch series "Add support to configure TPDM CMB subunit". 2. Modify the functions that read the element size of DSB/CMB in TPDA driver. Tao Zhang (10): coresight-tpdm: Optimize the store function of tpdm simple dataset coresight-tpdm: Optimize the useage of tpdm_has_dsb_dataset dt-bindings: arm: qcom,coresight-tpdm: Add support for CMB element size coresight-tpdm: Add CMB dataset support coresight-tpda: Add support to configure CMB element coresight-tpdm: Add support to configure CMB coresight-tpdm: Add pattern registers support for CMB coresight-tpdm: Add timestamp control register support for the CMB dt-bindings: arm: qcom,coresight-tpdm: Add support for TPDM CMB MSR register coresight-tpdm: Add msr register support for CMB .../testing/sysfs-bus-coresight-devices-tpdm | 87 ++++ .../bindings/arm/qcom,coresight-tpdm.yaml | 35 ++ drivers/hwtracing/coresight/coresight-tpda.c | 123 +++-- drivers/hwtracing/coresight/coresight-tpda.h | 6 + drivers/hwtracing/coresight/coresight-tpdm.c | 455 ++++++++++++++++-- drivers/hwtracing/coresight/coresight-tpdm.h | 113 +++++ 6 files changed, 727 insertions(+), 92 deletions(-) -- 2.17.1

1 year, 5 months

[PATCH v3 0/2] coresight: core: Add device name support

by Mao Jinlong

With current design, the name of the non-cpu bounded coresight component is the device type with the number. And with 'ls' command we can get the register address of the component. But from these information, we can't know what the HW or system the component belongs to. Add device-name in DT to support it. cti_sys0 -> ../../../devices/platform/soc(a)0/138f0000.cti/cti_sys0 cti_sys1 -> ../../../devices/platform/soc(a)0/13900000.cti/cti_sys1 tpdm0 -> ../../../devices/platform/soc(a)0/10b0d000.tpdm/tpdm0 tpdm1 -> ../../../devices/platform/soc(a)0/10c28000.tpdm/tpdm1 tpdm2 -> ../../../devices/platform/soc(a)0/10c29000.tpdm/tpdm2 Change since V2: 1. Fix the error in coresight core. drivers/hwtracing/coresight/coresight-core.c:1775:7: error: assigning to 'char *' from 'const char *' discards qualifiers 2. Fix the warning when run dtbinding check. Documentation/devicetree/bindings/arm/arm,coresight-cpu-debug.yaml: device-name: missing type definition Change since V1: 1. Change coresight-name to device name. 2. Add the device-name in coresight dt bindings. Mao Jinlong (2): coresight: core: Add device name support dt-bindings: arm: Add device-name in the coresight components .../bindings/arm/arm,coresight-catu.yaml | 6 +++ .../bindings/arm/arm,coresight-cpu-debug.yaml | 6 +++ .../bindings/arm/arm,coresight-cti.yaml | 6 +++ .../arm/arm,coresight-dummy-sink.yaml | 6 +++ .../arm/arm,coresight-dummy-source.yaml | 6 +++ .../arm/arm,coresight-dynamic-funnel.yaml | 6 +++ .../arm/arm,coresight-dynamic-replicator.yaml | 6 +++ .../bindings/arm/arm,coresight-etb10.yaml | 6 +++ .../bindings/arm/arm,coresight-etm.yaml | 6 +++ .../arm/arm,coresight-static-funnel.yaml | 6 +++ .../arm/arm,coresight-static-replicator.yaml | 6 +++ .../bindings/arm/arm,coresight-stm.yaml | 6 +++ .../bindings/arm/arm,coresight-tmc.yaml | 6 +++ .../bindings/arm/arm,coresight-tpiu.yaml | 6 +++ .../bindings/arm/qcom,coresight-tpda.yaml | 6 +++ .../bindings/arm/qcom,coresight-tpdm.yaml | 6 +++ drivers/hwtracing/coresight/coresight-core.c | 37 ++++++++++--------- .../hwtracing/coresight/coresight-platform.c | 31 ++++++++++++++++ include/linux/coresight.h | 3 +- 19 files changed, 149 insertions(+), 18 deletions(-) -- 2.41.0

1 year, 5 months

[PATCH v4 00/10] Add support to configure TPDM CMB subunit

by Tao Zhang

Introduction of TPDM CMB(Continuous Multi Bit) subunit CMB subunit is responsible for creating a dataset element, and is also optionally responsible for packing it to fit multiple elements on a single ATB transfer if possible in the configuration. The TPDM Core Datapath requests timestamps be stored by the TPDA and then delivering ATB sized data (depending on ATB width and element size, this could be smaller or larger than a dataset element) to the ATB Mast FSM. The CMB makes trace elements in two modes. In �continuous� mode, every valid data cycle creates an element. In �trace on change� mode, when valid data changes on the bus, a trace element is created. In continuous mode, all cycles where this condition is true create trace elements. In trace on change mode, a data element is only when the previously sampled input is different from the current sampled input. The CMB subunit must be configured prior to enablement. This series adds support for TPDM to configure the configure CMB subunit. Once this series patches are applied properly, the new tpdm nodes for should be observed at the tpdm path /sys/bus/coresight/devices/tpdm* which supports CMB subunit. e.g. root@qemuarm64:/sys/devices/platform/soc@0/684c000.tpdm/tpdm0# ls -l -rw-r--r-- 1 root root 4096 Jan 1 00:00 cmb_mode drwxr-xr-x 2 root root 0 Jan 1 00:00 cmb_msr drwxr-xr-x 2 root root 0 Jan 1 00:00 cmb_patt drwxr-xr-x 2 root root 0 Jan 1 00:00 cmb_trig_patt -rw-r--r-- 1 root root 4096 Jan 1 00:00 cmb_trig_ts -rw-r--r-- 1 root root 4096 Jan 1 00:00 cmb_ts_all drwxr-xr-x 2 root root 0 Jan 1 00:00 connections drwxr-xr-x 2 root root 0 Jan 1 00:00 dsb_edge drwxr-xr-x 2 root root 0 Jan 1 00:00 dsb_msr drwxr-xr-x 2 root root 0 Jan 1 00:00 dsb_patt drwxr-xr-x 2 root root 0 Jan 1 00:00 dsb_trig_patt -rw-r--r-- 1 root root 4096 Jan 1 00:00 enable_source --w------- 1 root root 4096 Jan 1 00:00 integration_test drwxr-xr-x 2 root root 0 Ja? 1 00:00 power --w------- 1 root root 4096 Jan 1 00:00 reset_dataset lrwxrwxrwx 1 root root 0 Apr 5 2021 subsystem -> ../../../../../bus/coresight -rw-r--r-- 1 root root 4096 Apr 5 2021 uevent -r--r--r-- 1 root root 4096 Jan 1 00:00 waiting_for_supplier We can use the commands are similar to the below to configure the TPDMs which support CMB subunit. Enable coresight sink first. echo 1 > /sys/bus/coresight/devices/tmc_etf0/enable_sink echo 1 > /sys/bus/coresight/devices/tpdm0/reset_dataset echo 1 > /sys/bus/coresight/devices/tpdm0/cmb_mode echo 1 > /sys/bus/coresight/devices/tpdm0/cmb_patt/enable_ts echo 0xFFFFFFFF > /sys/bus/coresight/devices/tpdm0/cmb_patt/tpmr0 echo 0 > /sys/bus/coresight/devices/tpdm0/cmb_trig_ts echo 0xFFFFFFFF > /sys/bus/coresight/devices/tpdm0/cmb_trig_patt/xpr1 echo 1 > /sys/bus/coresight/devices/tpdm0/enable_source codelinaro link: https://git.codelinaro.org/clo/linux-kernel/coresight/-/commits/tpdm-cmb-v4 Changes in V4: 1. Replace spin lock/unlock to avoid forgetting to unlock when the function exits. -- Suzuki K Poulose 2. Move the helper "tpdm_has_dsb_dataset" to the header file. -- Suzuki K Poulose 3. Fix the incorrect property of the sample in the documents. -- James Clark 4. Clear the dsb/cmb element size directly in the clear helper. -- Suzuki K Poulose 5. Correct the comment of "tpdm_read_element_size". -- Suzuki K Poulose 6. Call the helper "tpdm_has_dsb/cmb_dataset" in TPDA driver to check what dataset the TPDM supports. -- Suzuki K Poulose 7. Refine the dsb/cmb dataset support check in enable/disable functions. -- Suzuki K Poulose 8. Get rid of redundant code in function "set_cmb_tier". -- Suzuki K Poulose 9. Since one SysFs file should follow "one value", use "dev_ext_attribute" to instead of the previous "enable_ts" Sysfs file approach. -- Suzuki K Poulose 10. Change the kernel version to 6.9 for the MSR related SysFs file. -- James Clark 11. Refine the function "tpdm_simple_dataset_store". -- Suzuki K Poulose Changes in V3: 1. Add 8-bit support to the description in the TPDM devicetree document. -- Rob Herring 2. Change how the result is produced in "tpdm_read_element_size". -- James Clark 3. Calling "tpdm_clear_element_size" at the beginning of "tpda_enable_port". -- James Clark 4. Use "dsb_esize" and "cmb_esize" to determine whether multiple TPDMs are detected on a TPDA input port in "tpda_get_element_size". -- James Clark 5. Modify the judgment logic in "tpda_enable_port". -- James Clark 6. Add more description of "cmb_mode" to TPDM SysFS document. -- James Clark Changes in V2: 1. Optimizate and modify this patch series based on the patch series "Add support to configure TPDM CMB subunit". 2. Modify the functions that read the element size of DSB/CMB in TPDA driver. Tao Zhang (10): coresight-tpdm: Optimize the store function of tpdm simple dataset coresight-tpdm: Optimize the useage of tpdm_has_dsb_dataset dt-bindings: arm: Add support for CMB element size coresight-tpdm: Add CMB dataset support coresight-tpda: Add support to configure CMB element coresight-tpdm: Add support to configure CMB coresight-tpdm: Add pattern registers support for CMB coresight-tpdm: Add timestamp control register support for the CMB dt-bindings: arm: Add support for TPDM CMB MSR register coresight-tpdm: Add msr register support for CMB .../testing/sysfs-bus-coresight-devices-tpdm | 87 +++ .../bindings/arm/qcom,coresight-tpdm.yaml | 37 ++ drivers/hwtracing/coresight/coresight-tpda.c | 123 +++-- drivers/hwtracing/coresight/coresight-tpda.h | 6 + drivers/hwtracing/coresight/coresight-tpdm.c | 508 +++++++++++++++--- drivers/hwtracing/coresight/coresight-tpdm.h | 113 ++++ 6 files changed, 757 insertions(+), 117 deletions(-) -- 2.17.1

1 year, 5 months

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

CoreSight