On 13/02/2024 22:29, Rob Herring wrote:
> On Tue, Feb 13, 2024 at 08:05:17AM -0800, Mao Jinlong wrote:
>> Change qcom,dsb-element-size to qcom,dsb-element-bits as the unit is
>> bit.
>
> That may be, but this is an ABI and you are stuck with it. Unless, you
> can justify why that doesn't matter. (IIRC, this is new, so maybe no
> users yet?)
This was added and support queued in v6.8. This change won't make it to
v6.8 (given it has to go via two levels and is technically not a fix).
As James also pointed out, it doesn't matter what the name is (now that
it has been published).
Suzuki
On 2/14/2024 6:29 AM, Rob Herring wrote:
> On Tue, Feb 13, 2024 at 08:05:17AM -0800, Mao Jinlong wrote:
>> Change qcom,dsb-element-size to qcom,dsb-element-bits as the unit is
>> bit.
> That may be, but this is an ABI and you are stuck with it. Unless, you
> can justify why that doesn't matter. (IIRC, this is new, so maybe no
> users yet?)
Hi Rob,
Because for CMB type, it uses qcom,cmb-element-bits. So I change the
format to be the same as
CMB.
Thanks
Jinlong Mao
On 13/02/2024 10:45, Arnd Bergmann wrote:
> On Tue, Feb 13, 2024, at 11:22, Suzuki K Poulose wrote:
>
>> coresight: tpdm: Fix build break due to uninitialised field
>>
>> {CMB/DSB}_PATT_ENABLE_TS attributes do not use an index field.
>> But some compilers complain for uninitialised "index" field in
>> the struct tpdm_dataset_attribute:
>>
> ...
>>
>> Reported-by: Arnd Bergmann <arnd(a)arndb.de>
>> Cc: Tao Zhang <quic_taozha(a)quicinc.com>
>> Signed-off-by: Suzuki K Poulose <suzuki.poulose(a)arm.com>
>
> Works fine here with this, thanks for the fix!
>
> Acked-by: Arnd Bergmann <arnd(a)arndb.de>
>
> I had actually missed that this is a warning option that
> is normally disabled even at W=1 level, but it does get
> added by drivers/hwtracing/coresight/Makefile setting
> -Wextra again because that comes after the
> -Wno-missing-field-initializers from scripts/Makefile.extrawarn.
>
> Arnd
Thanks for verifying, I have queued this.
https://git.kernel.org/coresight/c/c099fdd218a0
Suzuki
On 13/02/2024 10:45, Arnd Bergmann wrote:
> On Tue, Feb 13, 2024, at 11:22, Suzuki K Poulose wrote:
>
>> coresight: tpdm: Fix build break due to uninitialised field
>>
>> {CMB/DSB}_PATT_ENABLE_TS attributes do not use an index field.
>> But some compilers complain for uninitialised "index" field in
>> the struct tpdm_dataset_attribute:
>>
> ...
>>
>> Reported-by: Arnd Bergmann <arnd(a)arndb.de>
>> Cc: Tao Zhang <quic_taozha(a)quicinc.com>
>> Signed-off-by: Suzuki K Poulose <suzuki.poulose(a)arm.com>
>
> Works fine here with this, thanks for the fix!
>
> Acked-by: Arnd Bergmann <arnd(a)arndb.de>
>
> I had actually missed that this is a warning option that
> is normally disabled even at W=1 level, but it does get
> added by drivers/hwtracing/coresight/Makefile setting
> -Wextra again because that comes after the
> -Wno-missing-field-initializers from scripts/Makefile.extrawarn.
>
> Arnd
Thanks, I will queue this.
Suzuki
On Fri, 5 Jan 2024 13:33:32 +0100, Greg Kroah-Hartman wrote:
> Now that the driver core can properly handle constant struct bus_type,
> move the coresight_bustype variable to be a constant structure as well,
> placing it into read-only memory which can not be modified at runtime.
>
>
Moved to next, thanks!
[1/1] coresight: make coresight_bustype const
https://git.kernel.org/coresight/c/dd95255d44c0
Best regards,
--
Suzuki K Poulose <suzuki.poulose(a)arm.com>
Changes since V1:
* Clarify further "the selected sink" in _coresight_build_path()
* Move etm4x's mode to coresight device which was missing from V1
* Use explicit initialisers in coresight_dev_type
* Create functions for handling mode changes
I've been finding it quite difficult to reason about some of the state
and functions in coresight-core.c because they have generic names when
they are actually only relevant to the sysfs usage of Coresight rather
than usage through Perf. This is probably because sysfs came first and
Perf was added later. This has caused a couple of issues where these
things have been used in the wrong context, for example the first
commit is a fixup.
To fix this I've mainly just moved all of the sysfs stuff to the sysfs
file and removed the 'enable' state, which was just for sysfs. While
doing the refactor it became obvious that refcnt didn't need to be
atomic either, so that can be simplified along with some other comment
clarifications and simplifications.
Hopefully it's also a step towards to removing all of the duplicate
refcnt and mode tracking code from the individual devices. That tracking
pretty much always results in a one-shot enable/disable and fixes the
mode to either sysfs or Perf, and there is no reason that can't exist in
the core layer outside of the devices. I tried to finish that in this
set, but there turned out to be some complexities, so I cut it short at
a point where I can be sure that there are no behavioral changes.
James Clark (12):
coresight: Fix issue where a source device's helpers aren't disabled
coresight: Make language around "activated" sinks consistent
coresight: Remove ops callback checks
coresight: Move mode to struct coresight_device
coresight: Remove the 'enable' field.
coresight: Move all sysfs code to sysfs file
coresight: Remove atomic type from refcnt
coresight: Remove unused stubs
coresight: Add explicit member initializers to coresight_dev_type
coresight: Add helper for atomically taking the device
coresight: Add a helper for getting csdev->mode
coresight: Add helper for setting csdev->mode
drivers/hwtracing/coresight/coresight-core.c | 494 +-----------------
drivers/hwtracing/coresight/coresight-etb10.c | 29 +-
.../hwtracing/coresight/coresight-etm-perf.c | 2 +-
drivers/hwtracing/coresight/coresight-etm.h | 2 -
.../coresight/coresight-etm3x-core.c | 23 +-
.../coresight/coresight-etm3x-sysfs.c | 4 +-
.../coresight/coresight-etm4x-core.c | 26 +-
drivers/hwtracing/coresight/coresight-etm4x.h | 1 -
drivers/hwtracing/coresight/coresight-priv.h | 9 +-
drivers/hwtracing/coresight/coresight-stm.c | 30 +-
drivers/hwtracing/coresight/coresight-sysfs.c | 391 ++++++++++++++
.../hwtracing/coresight/coresight-tmc-core.c | 2 +-
.../hwtracing/coresight/coresight-tmc-etf.c | 46 +-
.../hwtracing/coresight/coresight-tmc-etr.c | 33 +-
drivers/hwtracing/coresight/coresight-tmc.h | 2 -
drivers/hwtracing/coresight/coresight-tpda.c | 13 +-
drivers/hwtracing/coresight/coresight-tpiu.c | 14 +-
drivers/hwtracing/coresight/ultrasoc-smb.c | 22 +-
drivers/hwtracing/coresight/ultrasoc-smb.h | 2 -
include/linux/coresight.h | 146 ++----
20 files changed, 606 insertions(+), 685 deletions(-)
--
2.34.1
Introduction of TPDM CMB(Continuous Multi Bit) subunit
CMB subunit is responsible for creating a dataset element, and is also
optionally responsible for packing it to fit multiple elements on a
single ATB transfer if possible in the configuration. The TPDM Core
Datapath requests timestamps be stored by the TPDA and then delivering
ATB sized data (depending on ATB width and element size, this could
be smaller or larger than a dataset element) to the ATB Mast FSM.
The CMB makes trace elements in two modes. In �continuous� mode, every
valid data cycle creates an element. In �trace on change� mode, when
valid data changes on the bus, a trace element is created. In
continuous mode, all cycles where this condition is true create trace
elements. In trace on change mode, a data element is only when the
previously sampled input is different from the current sampled input.
The CMB subunit must be configured prior to enablement. This series
adds support for TPDM to configure the configure CMB subunit.
Once this series patches are applied properly, the new tpdm nodes for
should be observed at the tpdm path /sys/bus/coresight/devices/tpdm*
which supports CMB subunit.
e.g.
root@qemuarm64:/sys/devices/platform/soc@0/684c000.tpdm/tpdm0# ls -l
-rw-r--r-- 1 root root 4096 Jan 1 00:00 cmb_mode
drwxr-xr-x 2 root root 0 Jan 1 00:00 cmb_msr
drwxr-xr-x 2 root root 0 Jan 1 00:00 cmb_patt
drwxr-xr-x 2 root root 0 Jan 1 00:00 cmb_trig_patt
-rw-r--r-- 1 root root 4096 Jan 1 00:00 cmb_trig_ts
-rw-r--r-- 1 root root 4096 Jan 1 00:00 cmb_ts_all
drwxr-xr-x 2 root root 0 Jan 1 00:00 connections
drwxr-xr-x 2 root root 0 Jan 1 00:00 dsb_edge
drwxr-xr-x 2 root root 0 Jan 1 00:00 dsb_msr
drwxr-xr-x 2 root root 0 Jan 1 00:00 dsb_patt
drwxr-xr-x 2 root root 0 Jan 1 00:00 dsb_trig_patt
-rw-r--r-- 1 root root 4096 Jan 1 00:00 enable_source
--w------- 1 root root 4096 Jan 1 00:00 integration_test
drwxr-xr-x 2 root root 0 Ja? 1 00:00 power
--w------- 1 root root 4096 Jan 1 00:00 reset_dataset
lrwxrwxrwx 1 root root 0 Apr 5 2021 subsystem -> ../../../../../bus/coresight
-rw-r--r-- 1 root root 4096 Apr 5 2021 uevent
-r--r--r-- 1 root root 4096 Jan 1 00:00 waiting_for_supplier
We can use the commands are similar to the below to configure the
TPDMs which support CMB subunit. Enable coresight sink first.
echo 1 > /sys/bus/coresight/devices/tmc_etf0/enable_sink
echo 1 > /sys/bus/coresight/devices/tpdm0/reset_dataset
echo 1 > /sys/bus/coresight/devices/tpdm0/cmb_mode
echo 1 > /sys/bus/coresight/devices/tpdm0/cmb_patt/enable_ts
echo 0xFFFFFFFF > /sys/bus/coresight/devices/tpdm0/cmb_patt/tpmr0
echo 0 > /sys/bus/coresight/devices/tpdm0/cmb_trig_ts
echo 0xFFFFFFFF > /sys/bus/coresight/devices/tpdm0/cmb_trig_patt/xpr1
echo 1 > /sys/bus/coresight/devices/tpdm0/enable_source
codelinaro link:
https://git.codelinaro.org/clo/linux-kernel/coresight/-/commits/tpdm-cmb-v7
Changes in V7:
1. Rename "tpdm_clear_element_size" to "tpda_clear_element_size" in
the patch#5.
-- Suzuki K Poulose
2. Remove the stale comments in "tpda_enable_port".
-- Suzuki K Poulose
Changes in V6:
1. Clear all the relevant fields before setting them in the function
"tpda_set_element_size". In patch#5.
-- Suzuki K Poulose
2. Leave a space after/before '/*' & '*/'. In patch#7 #8.
-- Suzuki K Poulose
Changes in V5:
1. Return directly to refine the process of "tpdm_enable_dsb" and
"tpdm_disable_dsb" if the TPDM does not support DSB dataset.
-- Suzuki K Poulose
2. Change the new property name from "qcom,cmb-element-size" to
"qcom,cmb-element-bits". And update the property name to the new
tpdm example which supports the CMB dataset.
-- Krzysztof
3. Drop unnecessary () around the drvdata member access in patch#5.
-- Suzuki K Poulose
4. Replace the error code "-EEXIST" with the port number in detecting
multiple TPDMs on one input port. In patch#5.
-- Suzuki K Poulose
5. Due to the modification of the new property name, the searched
property name was changed from "qcom,cmb-element-size" to
"qcom,cmb-element-bits". In patch#5.
6. Replace the judgement "tpdm_has_cmb_dataset(drvdata)" with
"drvdata->cmb" in the function "tpdm_reset_datasets". In patch#6.
-- Suzuki K Poulose
7. Drop unnecessary () around kstrtoul() in the function
"cmb_mode_store". In patch#6.
-- Suzuki K Poulose
8. Update the date and the kernel version in the Document.
-- Suzuki K Poulose
9. Initialize the return value to "-EINVAL" and remove the unnecessary
code in the function "enable_ts_show". In patch#8.
-- Suzuki K Poulose
10. Replace spin lock/unlock with guard(spinlock). In patch#8.
-- Suzuki K Poulose
11. Drop _rw from the macro "tpdm_patt_enable_ts_rw". In patch#8.
-- Suzuki K Poulose
Changes in V4:
1. Replace spin lock/unlock to avoid forgetting to unlock when the
function exits.
-- Suzuki K Poulose
2. Move the helper "tpdm_has_dsb_dataset" to the header file.
-- Suzuki K Poulose
3. Fix the incorrect property of the sample in the documents.
-- James Clark
4. Clear the dsb/cmb element size directly in the clear helper.
-- Suzuki K Poulose
5. Correct the comment of "tpdm_read_element_size".
-- Suzuki K Poulose
6. Call the helper "tpdm_has_dsb/cmb_dataset" in TPDA driver to
check what dataset the TPDM supports.
-- Suzuki K Poulose
7. Refine the dsb/cmb dataset support check in enable/disable functions.
-- Suzuki K Poulose
8. Get rid of redundant code in function "set_cmb_tier".
-- Suzuki K Poulose
9. Since one SysFs file should follow "one value", use "dev_ext_attribute"
to instead of the previous "enable_ts" Sysfs file approach.
-- Suzuki K Poulose
10. Change the kernel version to 6.9 for the MSR related SysFs file.
-- James Clark
11. Refine the function "tpdm_simple_dataset_store".
-- Suzuki K Poulose
Changes in V3:
1. Add 8-bit support to the description in the TPDM devicetree document.
-- Rob Herring
2. Change how the result is produced in "tpdm_read_element_size".
-- James Clark
3. Calling "tpdm_clear_element_size" at the beginning of
"tpda_enable_port".
-- James Clark
4. Use "dsb_esize" and "cmb_esize" to determine whether multiple TPDMs
are detected on a TPDA input port in "tpda_get_element_size".
-- James Clark
5. Modify the judgment logic in "tpda_enable_port".
-- James Clark
6. Add more description of "cmb_mode" to TPDM SysFS document.
-- James Clark
Changes in V2:
1. Optimizate and modify this patch series based on the patch series
"Add support to configure TPDM CMB subunit".
2. Modify the functions that read the element size of DSB/CMB in TPDA driver.
Tao Zhang (10):
coresight-tpdm: Optimize the store function of tpdm simple dataset
coresight-tpdm: Optimize the useage of tpdm_has_dsb_dataset
dt-bindings: arm: qcom,coresight-tpdm: Add support for CMB element
size
coresight-tpdm: Add CMB dataset support
coresight-tpda: Add support to configure CMB element
coresight-tpdm: Add support to configure CMB
coresight-tpdm: Add pattern registers support for CMB
coresight-tpdm: Add timestamp control register support for the CMB
dt-bindings: arm: qcom,coresight-tpdm: Add support for TPDM CMB MSR
register
coresight-tpdm: Add msr register support for CMB
.../testing/sysfs-bus-coresight-devices-tpdm | 87 ++++
.../bindings/arm/qcom,coresight-tpdm.yaml | 35 ++
drivers/hwtracing/coresight/coresight-tpda.c | 130 ++---
drivers/hwtracing/coresight/coresight-tpda.h | 6 +
drivers/hwtracing/coresight/coresight-tpdm.c | 455 ++++++++++++++++--
drivers/hwtracing/coresight/coresight-tpdm.h | 113 +++++
6 files changed, 729 insertions(+), 97 deletions(-)
--
2.17.1