CoreSight

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Re: [PATCH 1/2] coresight: tmc: Don't change the buffer size if it's in use

by James Clark

On 14/11/2024 2:51 pm, Yicong Yang wrote: > On 2024/11/14 18:30, James Clark wrote: >> >> >> On 14/11/2024 8:16 am, Yicong Yang wrote: >>> From: Yicong Yang <yangyicong(a)hisilicon.com> >>> >>> Enable the trace in below steps will crash the kernel by NULL pointer >>> dereferencing: >>> echo 1 > /sys/bus/coresight/devices/tmc_etr0/enable_sink >>> echo 1 > /sys/bus/coresight/devices/etm0/enable_source >>> echo 0x400000 > /sys/bus/coresight/devices/tmc_etr0/buffer_size >>> echo 1 > /sys/bus/coresight/devices/etm2/enable_source >>> dd if=/dev/tmc_etr0 of=test_etm_sysfs_etr_030.data >>> >>> The call trace will be like: >>> WARNING: CPU: 39 PID: 8586 at drivers/hwtracing/coresight/coresight-tmc-etr.c:1123 __tmc_etr_disable_hw+0x108/0x140 [coresight_tmc] >>> [...] >>> Call trace: >>> __tmc_etr_disable_hw+0x108/0x140 [coresight_tmc] >>> tmc_read_prepare_etr+0xc0/0xd0 [coresight_tmc] >>> tmc_open+0x60/0xa0 [coresight_tmc] >>> misc_open+0x11c/0x170 >>> chrdev_open+0xcc/0x2b0 >>> do_dentry_open+0x140/0x4e0 >>> vfs_open+0x34/0xf8 >>> path_openat+0x2b0/0xf58 >>> do_filp_open+0x8c/0x148 >>> do_sys_openat2+0xb8/0xe8 >>> __arm64_sys_openat+0x70/0xc0 >>> el0_svc_common.constprop.0+0x64/0x148 >>> do_el0_svc+0x24/0x38 >>> el0_svc+0x40/0x140 >>> el0t_64_sync_handler+0xc0/0xc8 >>> el0t_64_sync+0x1a4/0x1a8 >>> ---[ end trace 0000000000000000 ]--- >>> Unable to handle kernel NULL pointer dereference at virtual address 0000000000000028 >>> [...] >>> Call trace: >>> tmc_etr_get_sysfs_trace+0x10/0x80 [coresight_tmc] >>> vfs_read+0xcc/0x310 >>> ksys_read+0x74/0x108 >>> __arm64_sys_read+0x24/0x38 >>> el0_svc_common.constprop.0+0x64/0x148 >>> do_el0_svc+0x24/0x38 >>> el0_svc+0x40/0x140 >>> >>> Due to the buffer size changed, the buffer will be reallocated in >>> tmc_etr_get_sysfs_buffer() when the second source enabled. At trace >>> end tmc_etr_sync_sysfs_buf() will reset the drvdata->sysfs_buf and >>> trigger the later NULL pointer dereference when reading out the >>> data. >>> >>> But it doesn't make sense to change the buffer size when it's >>> already in use. So block such behavior. >>> >>> Signed-off-by: Yicong Yang <yangyicong(a)hisilicon.com> >>> --- >>> drivers/hwtracing/coresight/coresight-tmc-core.c | 5 +++++ >>> 1 file changed, 5 insertions(+) >>> >>> diff --git a/drivers/hwtracing/coresight/coresight-tmc-core.c b/drivers/hwtracing/coresight/coresight-tmc-core.c >>> index 475fa4bb6813..9660af63e9bc 100644 >>> --- a/drivers/hwtracing/coresight/coresight-tmc-core.c >>> +++ b/drivers/hwtracing/coresight/coresight-tmc-core.c >>> @@ -319,6 +319,11 @@ static ssize_t buffer_size_store(struct device *dev, >>> if (drvdata->config_type != TMC_CONFIG_TYPE_ETR) >>> return -EPERM; >>> + /* Don't change the buffer size if it's in use */ >>> + guard(spinlock)(&drvdata->spinlock); >>> + if (coresight_get_mode(drvdata->csdev) != CS_MODE_DISABLED) >> >> Size isn't used in perf mode is it? So it can be -EBUSY only when mode == CS_MODE_SYSFS. >> > > alloc_etr_buf() on the perf path will read drvdata->size, not sure it matters if user > change it through sysfs in the meanwhile. Will test and have a check if there are any > other places using size on the perf path. > Hmmm I assumed that Perf mode completely ignored anything from sysfs mode. I see that alloc_etr_buf() does sometimes use the sysfs value. I don't really see why that's necessary because that means it sometimes ignores the buffer size from the perf command line depending on what's in sysfs, but the modes should be mutually exclusive. Unless we fix that then I think you do need to use the device spinlock. But I think we should tidy up alloc_etr_buf() to only try to allocate from the Perf size down to TMC_ETR_PERF_MIN_BUF_SIZE, ignoring drvdata->size. Then the behavior is less surprising to users and also anyone reading the code. And rename it to alloc_etr_buf_perf(). Unless Suzuki knows of a reason it was done that way to begin with? I checked the commit message but it just says that it was like that but not why. >>> + return -EBUSY; >>> + >>> ret = kstrtoul(buf, 0, &val); >>> if (ret) >>> return ret; >> >> Looks ok to me. Although for consistency it might be worth changing to guard(mutex)(&coresight_mutex) because this is about sysfs mode only and other usages of mode and comments point to coresight_mutex. Using the device's spinlock will technically work but it did make me go and double check the code. And there are other cases of reading the mode like this: >> > > ok, I thought to also serialize the use of drvdata->size. But as you mentioned > use coresight_mutex is enough and will be consistenct with other places. > >> static ssize_t enable_source_show(struct device *dev, >> struct device_attribute *attr, >> char *buf) >> { >> struct coresight_device *csdev = to_coresight_device(dev); >> >> guard(mutex)(&coresight_mutex); >> return scnprintf(buf, PAGE_SIZE, "%u\n", >> coresight_get_mode(csdev) == CS_MODE_SYSFS); >> } >> >> Mode can change to CS_MODE_PERF while inside coresight_mutex but the device would end up not being enabled for sysfs, so it's still ok to update the sysfs size value in that case. >> >> With that change: >> >> Reviewed-by: James Clark <james.clark(a)linaro.org> > > Thanks. >

7 months, 2 weeks

Re: [PATCH 2/2] coresight: tmc: Add missing doc of tmc_drvdata::reading

by James Clark

On 14/11/2024 8:16 am, Yicong Yang wrote: > From: Yicong Yang <yangyicong(a)hisilicon.com> > > tmc_drvdata::reading is used to indicate whether a reading process > is performed through /dev/xyz.tmc. Document it. > > Signed-off-by: Yicong Yang <yangyicong(a)hisilicon.com> > --- > drivers/hwtracing/coresight/coresight-tmc.h | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/drivers/hwtracing/coresight/coresight-tmc.h b/drivers/hwtracing/coresight/coresight-tmc.h > index 2671926be62a..fdf7955e7350 100644 > --- a/drivers/hwtracing/coresight/coresight-tmc.h > +++ b/drivers/hwtracing/coresight/coresight-tmc.h > @@ -174,6 +174,7 @@ struct etr_buf { > * @pid: Process ID of the process that owns the session that is using > * this component. For example this would be the pid of the Perf > * process. > + * @reading: buffer's in the reading through "/dev/xyz.tmc" entry > * @buf: Snapshot of the trace data for ETF/ETB. > * @etr_buf: details of buffer used in TMC-ETR > * @len: size of the available trace for ETF/ETB. Reviewed-by: James Clark <james.clark(a)linaro.org>

7 months, 2 weeks

Re: [PATCH 1/2] coresight: tmc: Don't change the buffer size if it's in use

by James Clark

On 14/11/2024 8:16 am, Yicong Yang wrote: > From: Yicong Yang <yangyicong(a)hisilicon.com> > > Enable the trace in below steps will crash the kernel by NULL pointer > dereferencing: > echo 1 > /sys/bus/coresight/devices/tmc_etr0/enable_sink > echo 1 > /sys/bus/coresight/devices/etm0/enable_source > echo 0x400000 > /sys/bus/coresight/devices/tmc_etr0/buffer_size > echo 1 > /sys/bus/coresight/devices/etm2/enable_source > dd if=/dev/tmc_etr0 of=test_etm_sysfs_etr_030.data > > The call trace will be like: > WARNING: CPU: 39 PID: 8586 at drivers/hwtracing/coresight/coresight-tmc-etr.c:1123 __tmc_etr_disable_hw+0x108/0x140 [coresight_tmc] > [...] > Call trace: > __tmc_etr_disable_hw+0x108/0x140 [coresight_tmc] > tmc_read_prepare_etr+0xc0/0xd0 [coresight_tmc] > tmc_open+0x60/0xa0 [coresight_tmc] > misc_open+0x11c/0x170 > chrdev_open+0xcc/0x2b0 > do_dentry_open+0x140/0x4e0 > vfs_open+0x34/0xf8 > path_openat+0x2b0/0xf58 > do_filp_open+0x8c/0x148 > do_sys_openat2+0xb8/0xe8 > __arm64_sys_openat+0x70/0xc0 > el0_svc_common.constprop.0+0x64/0x148 > do_el0_svc+0x24/0x38 > el0_svc+0x40/0x140 > el0t_64_sync_handler+0xc0/0xc8 > el0t_64_sync+0x1a4/0x1a8 > ---[ end trace 0000000000000000 ]--- > Unable to handle kernel NULL pointer dereference at virtual address 0000000000000028 > [...] > Call trace: > tmc_etr_get_sysfs_trace+0x10/0x80 [coresight_tmc] > vfs_read+0xcc/0x310 > ksys_read+0x74/0x108 > __arm64_sys_read+0x24/0x38 > el0_svc_common.constprop.0+0x64/0x148 > do_el0_svc+0x24/0x38 > el0_svc+0x40/0x140 > > Due to the buffer size changed, the buffer will be reallocated in > tmc_etr_get_sysfs_buffer() when the second source enabled. At trace > end tmc_etr_sync_sysfs_buf() will reset the drvdata->sysfs_buf and > trigger the later NULL pointer dereference when reading out the > data. > > But it doesn't make sense to change the buffer size when it's > already in use. So block such behavior. > > Signed-off-by: Yicong Yang <yangyicong(a)hisilicon.com> > --- > drivers/hwtracing/coresight/coresight-tmc-core.c | 5 +++++ > 1 file changed, 5 insertions(+) > > diff --git a/drivers/hwtracing/coresight/coresight-tmc-core.c b/drivers/hwtracing/coresight/coresight-tmc-core.c > index 475fa4bb6813..9660af63e9bc 100644 > --- a/drivers/hwtracing/coresight/coresight-tmc-core.c > +++ b/drivers/hwtracing/coresight/coresight-tmc-core.c > @@ -319,6 +319,11 @@ static ssize_t buffer_size_store(struct device *dev, > if (drvdata->config_type != TMC_CONFIG_TYPE_ETR) > return -EPERM; > > + /* Don't change the buffer size if it's in use */ > + guard(spinlock)(&drvdata->spinlock); > + if (coresight_get_mode(drvdata->csdev) != CS_MODE_DISABLED) Size isn't used in perf mode is it? So it can be -EBUSY only when mode == CS_MODE_SYSFS. > + return -EBUSY; > + > ret = kstrtoul(buf, 0, &val); > if (ret) > return ret; Looks ok to me. Although for consistency it might be worth changing to guard(mutex)(&coresight_mutex) because this is about sysfs mode only and other usages of mode and comments point to coresight_mutex. Using the device's spinlock will technically work but it did make me go and double check the code. And there are other cases of reading the mode like this: static ssize_t enable_source_show(struct device *dev, struct device_attribute *attr, char *buf) { struct coresight_device *csdev = to_coresight_device(dev); guard(mutex)(&coresight_mutex); return scnprintf(buf, PAGE_SIZE, "%u\n", coresight_get_mode(csdev) == CS_MODE_SYSFS); } Mode can change to CS_MODE_PERF while inside coresight_mutex but the device would end up not being enabled for sysfs, so it's still ok to update the sysfs size value in that case. With that change: Reviewed-by: James Clark <james.clark(a)linaro.org>

7 months, 2 weeks

Re: [PATCH v2] Coresight: Narrow down the matching range of tpdm

by Suzuki K Poulose

On 09/10/2024 10:17, Songwei Chai wrote: > The format of tpdm's peripheral id is 1f0exx. To avoid potential > conflicts in the future, update the .id_table's id to 0x001f0e00. > This update will narrow down the matching range and prevent incorrect > matches. For example, another component's peripheral id might be > f0e00, which would incorrectly match the old id. > > Fixes: b3c71626a9333b0b29f9921a39ce ("Coresight: Add coresight TPDM source driver") > Signed-off-by: Songwei Chai <quic_songchai(a)quicinc.com> > --- > drivers/hwtracing/coresight/coresight-tpdm.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/hwtracing/coresight/coresight-tpdm.c b/drivers/hwtracing/coresight/coresight-tpdm.c > index b7d99e91ab84..3230d76aed90 100644 > --- a/drivers/hwtracing/coresight/coresight-tpdm.c > +++ b/drivers/hwtracing/coresight/coresight-tpdm.c > @@ -1308,8 +1308,8 @@ static void tpdm_remove(struct amba_device *adev) > */ > static struct amba_id tpdm_ids[] = { > { > - .id = 0x000f0e00, > - .mask = 0x000fff00, > + .id = 0x001f0e00, > + .mask = 0x00ffff00, > }, > { 0, 0, NULL }, > }; > Looks good to me, will queue this for v6.14. Apologies for missing the v6.13 cycle Suzuki

7 months, 2 weeks

Re: [PATCH V11 0/2] arm-cs-trace-disasm.py/perf must accommodate non-zero DSO text offset

by Steve Clevenger

On 11/9/2024 8:37 AM, Namhyung Kim wrote: > On Fri, 08 Nov 2024 12:11:19 -0700, Steve Clevenger wrote: > >> Changes in V11: >> - Corrected prefix. >> - Fixed compile-time error for perf debug build by substituting in >> the map__pgoff macro (trace_event_python.c). >> >> Changes in V10: >> - Removed errant space in patch file 0002. Passed 'git apply --check' >> at perf-tools-next, 6.11.0-rc6. >> - Added back missing prefixes. >> >> [...] > > Applied to perf-tools-next, thanks! > > Best regards, > Namhyung > Thanks, Namhyung. Steve C.

7 months, 2 weeks

[PATCH v7 00/12] kvm/coresight: Support exclude guest and exclude host

by James Clark

FEAT_TRF is a Coresight feature that allows trace capture to be completely filtered at different exception levels, unlike the existing TRCVICTLR controls which may still emit target addresses of branches, even if the following trace is filtered. Without FEAT_TRF, it was possible to start a trace session on a host and also collect trace from the guest as TRCVICTLR was never programmed to exclude guests (and it could still emit target addresses even if it was). With FEAT_TRF, the current behavior of trace in guests exists depends on whether nVHE or VHE are being used. Both of the examples below are from the host's point of view, as Coresight isn't accessible from guests. This patchset is only relevant to when FEAT_TRF exists, otherwise there is no change. Current behavior: nVHE/pKVM: Because the host and the guest are both using TRFCR_EL1, trace will be generated in guests depending on the same filter rules the host is using. For example if the host is tracing userspace only, then guest userspace trace will also be collected. (This is further limited by whether TRBE is used because an issue with TRBE means that it's completely disabled in nVHE guests, but it's possible to have other tracing components.) VHE: With VHE, the host filters will be in TRFCR_EL2, but the filters in TRFCR_EL1 will be active when the guest is running. Because we don't write to TRFCR_EL1, guest trace will be completely disabled. New behavior: The guest filtering rules from the Perf session are now honored for both nVHE and VHE modes. This is done by either writing to TRFCR_EL12 at the start of the Perf session and doing nothing else further, or caching the guest value and writing it at guest switch for nVHE. In pKVM, trace is now be disabled for both protected and unprotected guests. There is also an optimization where the SPE and Coresight drivers pass their enabled state to KVM. This means in the common case KVM doesn't have to touch any sysregs when the feature isn't in use. Applies to kvmarm/next (25a8556b54007) --- Changes since V6 [5]: * Implement a better "do nothing" case where both the SPE and Coresight drivers give the enabled state to KVM, allowing some register reads to be dropped. * Move the state and feature flags out of the vCPU into the per-CPU host_debug_state. * Simplify the switch logic by adding a new flag HOST_STATE_SWAP_TRFCR and only storing a single TRFCR value. * Rename vcpu flag macros to a more generic kvm_flag... Changes since V5 [4]: * Sort new sysreg entries by encoding * Add a comment about sorting arch/arm64/tools/sysreg * Warn on preemptible() before calling smp_processor_id() * Pickup tags * Change TRFCR_EL2 from SysregFields to Sysreg because it was only used once Changes since V4 [3]: * Remove all V3 changes that made it work in pKVM and just disable trace there instead * Restore PMU host/hyp state sharing back to how it was (kvm_pmu_update_vcpu_events()) * Simplify some of the duplication in the comments and function docs * Add a WARN_ON_ONCE() if kvm_etm_set_guest_trfcr() is called when the trace filtering feature doesn't exist. * Split sysreg change into a tools update followed by the new register addition Changes since V3: * Create a new shared area to store the host state instead of copying it before each VCPU run * Drop commit that moved SPE and trace registers from host_debug_state into the kvm sysregs array because the guest values were never used * Document kvm_etm_set_guest_trfcr() * Guard kvm_etm_set_guest_trfcr() with a feature check * Drop Mark B and Suzuki's review tags on the sysreg patch because it turned out that broke the Perf build and needed some unconventional changes to fix it (as in: to update the tools copy of the headers in the same commit as the kernel changes) Changes since V2: * Add a new iflag to signify presence of FEAT_TRF and keep the existing TRBE iflag. This fixes the issue where TRBLIMITR_EL1 was being accessed even if TRBE didn't exist * Reword a commit message Changes since V1: * Squashed all the arm64/tools/sysreg changes into the first commit * Add a new commit to move SPE and TRBE regs into the kvm sysreg array * Add a comment above the TRFCR global that it's per host CPU rather than vcpu Changes since nVHE RFC [1]: * Re-write just in terms of the register value to be written for the host and the guest. This removes some logic from the hyp code and a value of kvm_vcpu_arch:trfcr_el1 = 0 no longer means "don't restore". * Remove all the conditional compilation and new files. * Change the kvm_etm_update_vcpu_events macro to a function. * Re-use DEBUG_STATE_SAVE_TRFCR so iflags don't need to be expanded anymore. * Expand the cover letter. Changes since VHE v3 [2]: * Use the same interface as nVHE mode so TRFCR_EL12 is now written by kvm. [1]: https://lore.kernel.org/kvmarm/20230804101317.460697-1-james.clark@arm.com/ [2]: https://lore.kernel.org/kvmarm/20230905102117.2011094-1-james.clark@arm.com/ [3]: https://lore.kernel.org/linux-arm-kernel/20240104162714.1062610-1-james.cla… [4]: https://lore.kernel.org/all/20240220100924.2761706-1-james.clark@arm.com/ [5]: https://lore.kernel.org/linux-arm-kernel/20240226113044.228403-1-james.clar… James Clark (12): arm64/sysreg: Add a comment that the sysreg file should be sorted tools: arm64: Update sysreg.h header files arm64/sysreg/tools: Move TRFCR definitions to sysreg KVM: arm64: Make vcpu flag macros more generic KVM: arm64: Move SPE and TRBE flags to host data KVM: arm64: Add flag for FEAT_TRF KVM: arm64: arm_spe: Give SPE enabled state to KVM KVM: arm64: Don't hit sysregs to see if SPE is enabled or not KVM: arm64: coresight: Give TRBE enabled state to KVM KVM: arm64: Don't hit sysregs to see if TRBE is enabled or not KVM: arm64: Swap TRFCR on guest switch coresight: Pass guest TRFCR value to KVM arch/arm64/include/asm/kvm_host.h | 123 +++--- arch/arm64/include/asm/kvm_hyp.h | 2 +- arch/arm64/include/asm/sysreg.h | 12 - arch/arm64/kvm/arm.c | 3 - arch/arm64/kvm/debug.c | 97 ++++- arch/arm64/kvm/hyp/exception.c | 12 +- arch/arm64/kvm/hyp/nvhe/debug-sr.c | 118 +++-- arch/arm64/kvm/hyp/nvhe/switch.c | 2 +- arch/arm64/kvm/inject_fault.c | 4 +- arch/arm64/kvm/mmio.c | 10 +- arch/arm64/tools/sysreg | 38 ++ .../coresight/coresight-etm4x-core.c | 43 +- drivers/hwtracing/coresight/coresight-etm4x.h | 2 +- drivers/hwtracing/coresight/coresight-priv.h | 3 + drivers/hwtracing/coresight/coresight-trbe.c | 15 +- drivers/perf/arm_spe_pmu.c | 13 +- tools/arch/arm64/include/asm/sysreg.h | 410 +++++++++++++++++- tools/include/linux/kasan-tags.h | 15 + 18 files changed, 755 insertions(+), 167 deletions(-) create mode 100644 tools/include/linux/kasan-tags.h -- 2.34.1

7 months, 2 weeks

[PATCH v11 0/8] Coresight for Kernel panic and watchdog reset

by Linu Cherian

This patch series is rebased on coresight-next-v6.12.rc4 * Patches 1 & 2 adds support for allocation of trace buffer pages from reserved RAM * Patches 3 & 4 adds support for saving metadata at the time of kernel panic * Patch 5 adds support for reading trace data captured at the time of panic * Patches 6 & 7 adds support for disabling coresight blocks at the time of panic * Patch 8: Gives the full description about this feature as part of documentation V10 is posted here, https://lore.kernel.org/linux-arm-kernel/20240916103437.226816-1-lcherian@m… Changelog from v10: * Converted all csdev_access_* to readl functions in tmc_panic_sync_* * Added "tmc" prefix for register snapshots in struct tmc_crash_metadata * Converted dev_info to dev_dbg in panic handlers * Converted dsb to dmb in panic handlers * Fixed marking metadata as invalid when a user is trying to use the reserved buffer. Earlier this was wrongly set at the time of reading reserved trace buffer. * Moved common validation checks to is_tmc_crashdata_valid and minor code rearrangements for efficiency * Got rid of sink specific prepare/unprepare invocations * Got rid of full from struct tmc_resrv_buf * While reading crashdata, size is now calculated from metdata instead of relying on reserved buffer size populated by dtb * Minor documenation fixes Changelog from v9: * Add common helper function of_tmc_get_reserved_resource_by_name for better code reuse * Reserved buffer validity and crashdata validity has been separated to avoid interdependence * New fields added to crash metadata: version, ffcr, ffsr, mode * Version checks added for metadata validation * Special file /dev/crash_tmc_xxx would be available only when crash metadata is valid * Removed READ_CRASHDATA mode meant for special casing crashdata reads. Instead, dedicated read function added for crashdata reads from reserved buffer which is common for both ETR and ETF sinks as well. * Documentation added to Documentation/tracing/coresight/panic.rst Changelog from v8: * Added missing exit path on error in __tmc_probe. * Few whitespace fixes, checkpatch fixes. * With perf sessions honouring stop_on_flush sysfs attribute, removed redundant variable stop_on_flush_en. Changelog from v7: * Fixed breakage on perf test -vvvv "arm coresight". No issues seen with and without "resrv" buffer mode * Moved the crashdev registration into a separate function. * Removed redundant variable in tmc_etr_setup_crashdata_buf * Avoided a redundant memcpy in tmc_panic_sync_etf. * Tested kernel panic with trace session started uisng perf. Please see the title "Perf based testing" below for details. For this, stop_on_flush sysfs attribute is taken into consideration while starting perf sessions as well. Changelog from v6: * Added special device files for reading crashdata, so that read_prevboot mode flag is removed. * Added new sysfs TMC device attribute, stop_on_flush. Stop on flush trigger event is disabled by default. User need to explicitly enable this from sysfs for panic stop to work. * Address parameter for panicstop ETM configuration is chosen as kernel "panic" address by default. * Added missing tmc_wait_for_tmcready during panic handling * Few other misc code rearrangements. Changelog from v5: * Fixed issues reported by CONFIG_DEBUG_ATOMIC_SLEEP * Fixed a memory leak while reading data from /dev/tmc_etrx in READ_PREVBOOT mode * Tested reading trace data from crashdump kernel Changelog from v4: * Device tree binding - Description is made more explicit on the usage of reserved memory region - Mismatch in memory region names in dts binding and driver fixed - Removed "mem" suffix from the memory region names * Rename "struct tmc_register_snapshot" -> "struct tmc_crash_metadata", since it contains more than register snapshot. Related variables are named accordingly. * Rename struct tmc_drvdata members resrv_buf -> crash_tbuf metadata -> crash_mdata * Size field in metadata refers to RSZ register and hence indicates the size in 32 bit words. ETR metadata follows this convention, the same has been extended to ETF metadata as well. * Added crc32 for more robust metadata and tracedata validation. * Added/modified dev_dbg messages during metadata validation * Fixed a typo in patch 5 commit description Changelog from v3: * Converted the Coresight ETM driver change to a named configuration. RFC tag has been removed with this change. * Fixed yaml issues reported by "make dt_binding_check" * Added names for reserved memory regions 0 and 1 * Added prevalidation checks for metadata processing * Fixed a regression introduced in RFC v3 - TMC Status register was getting saved wrongly * Reverted memremap attribute changes from _WB to _WC to match with the dma map attributes * Introduced reserved buffer mode specific .sync op. This fixes a possible crash when reserved buffer mode was used in normal trace capture, due to unwanted dma maintenance operations. Linu Cherian (8): dt-bindings: arm: coresight-tmc: Add "memory-region" property coresight: tmc-etr: Add support to use reserved trace memory coresight: core: Add provision for panic callbacks coresight: tmc: Enable panic sync handling coresight: tmc: Add support for reading crash data coresight: tmc: Stop trace capture on FlIn coresight: config: Add preloaded configuration Documentation: coresight: Panic support .../bindings/arm/arm,coresight-tmc.yaml | 26 ++ Documentation/trace/coresight/panic.rst | 356 ++++++++++++++++++ drivers/hwtracing/coresight/Makefile | 2 +- .../coresight/coresight-cfg-preload.c | 2 + .../coresight/coresight-cfg-preload.h | 2 + .../hwtracing/coresight/coresight-cfg-pstop.c | 83 ++++ drivers/hwtracing/coresight/coresight-core.c | 42 +++ .../hwtracing/coresight/coresight-tmc-core.c | 326 +++++++++++++++- .../hwtracing/coresight/coresight-tmc-etf.c | 92 ++++- .../hwtracing/coresight/coresight-tmc-etr.c | 181 ++++++++- drivers/hwtracing/coresight/coresight-tmc.h | 104 +++++ include/linux/coresight.h | 12 + 12 files changed, 1216 insertions(+), 12 deletions(-) create mode 100644 Documentation/trace/coresight/panic.rst create mode 100644 drivers/hwtracing/coresight/coresight-cfg-pstop.c -- 2.34.1

7 months, 2 weeks

[PATCH V11 0/2] arm-cs-trace-disasm.py/perf must accommodate non-zero DSO text offset

by Steve Clevenger

Changes in V11: - Corrected prefix. - Fixed compile-time error for perf debug build by substituting in the map__pgoff macro (trace_event_python.c). Changes in V10: - Removed errant space in patch file 0002. Passed 'git apply --check' at perf-tools-next, 6.11.0-rc6. - Added back missing prefixes. Changes in V9: - Removed V8 patch files 1/4 and 2/4. - Modified set_sym_in_dict (trace-event-python.c) to add map_pgoff in dictionary as-is without regard to MAPPING_IDENTITY. This patch file is now patch 2/2. Changes in V8: - in arm-cs-trace-disasm.py, ensure map_pgoff is not converted to string. - Remove map_pgoff integer conversion in dso not found print message. Changes in V7: - In arm-cs-trace-disasm.py, fix print message core dump resulting from mixed type arithmetic. - Modify CS_ETM_TRACE_ON filter to filter zero start_addr. The CS_ETM_TRACE_ON message is changed to print only in verbose mode. - Removed verbose mode only notification for start_addr/stop_addr outside of dso address range. Changes in V6: - In arm-cs-trace-disasm.py, zero map_pgoff for kernel files. Add map_pgoff to start/end address for dso not found message. - Added "Reviewed-by" trailer for patches 1-3 previously reviewed by Leo Yan in V4 and V5. Changes in V5: - In symbol-elf.c, branch to exit_close label if open file. - In trace_event_python.c, correct indentation. set_sym_in_dict call parameter "map_pgoff" renamed as "addr_map_pgoff" to match local naming. Changes in V4: - In trace-event-python.c, fixed perf-tools-next merge problem. Changes in V3: - Rebased to linux-perf-tools branch. - Squash symbol-elf.c and symbol.h into same commit. - In map.c, merge dso__is_pie() call into existing if statement. - In arm-cs-trace-disasm.py, remove debug artifacts. Changes in V2: - In dso__is_pie() (symbol-elf.c), Decrease indentation, add null pointer checks per Leo Yan review. Steve Clevenger (2): perf script cs_etm: Add map_pgoff to python dictionary perf script python: Adjust objdump start/end per map pgoff parameter tools/perf/scripts/python/arm-cs-trace-disasm.py | 16 +++++++++++----- .../util/scripting-engines/trace-event-python.c | 9 ++++++--- 2 files changed, 17 insertions(+), 8 deletions(-) -- 2.44.0

7 months, 3 weeks

Re: [PATCH V10 RESEND 1/2] perf util scripting-engines cs-etm: Add map_pgoff to python dictionary

by Steve Clevenger

On 11/7/2024 10:51 AM, Namhyung Kim wrote: > On Wed, Nov 06, 2024 at 04:51:10PM -0700, Steve Clevenger wrote: >> Add map_pgoff parameter to python dictionary so it can be seen by the >> python script. >> >> Signed-off-by: Steve Clevenger <scclevenger(a)os.amperecomputing.com> >> Reviewed-by: Leo Yan <leo.yan(a)arm.com> >> --- >> tools/perf/util/scripting-engines/trace-event-python.c | 9 ++++++--- >> 1 file changed, 6 insertions(+), 3 deletions(-) >> >> diff --git a/tools/perf/util/scripting-engines/trace-event-python.c b/tools/perf/util/scripting-engines/trace-event-python.c >> index d7183134b669..367132b3a51a 100644 >> --- a/tools/perf/util/scripting-engines/trace-event-python.c >> +++ b/tools/perf/util/scripting-engines/trace-event-python.c >> @@ -793,7 +793,8 @@ static int set_regs_in_dict(PyObject *dict, >> static void set_sym_in_dict(PyObject *dict, struct addr_location *al, >> const char *dso_field, const char *dso_bid_field, >> const char *dso_map_start, const char *dso_map_end, >> - const char *sym_field, const char *symoff_field) >> + const char *sym_field, const char *symoff_field, >> + const char *map_pgoff) >> { >> char sbuild_id[SBUILD_ID_SIZE]; >> >> @@ -809,6 +810,8 @@ static void set_sym_in_dict(PyObject *dict, struct addr_location *al, >> PyLong_FromUnsignedLong(map__start(al->map))); >> pydict_set_item_string_decref(dict, dso_map_end, >> PyLong_FromUnsignedLong(map__end(al->map))); >> + pydict_set_item_string_decref(dict, map_pgoff, >> + PyLong_FromUnsignedLongLong(al->map->pgoff)); > > Please use map__pgoff(al->map) instead. Otherwise you'll get this in > the debug build: > > util/scripting-engines/trace-event-python.c: In function 'set_sym_in_dict': > util/scripting-engines/trace-event-python.c:814:60: error: 'struct map' has no member named 'pgoff' > 814 | PyLong_FromUnsignedLongLong(al->map->pgoff)); > | ^~ > > Thanks, > Namhyung > Hi Namhyung, I do not see this compile error, and I typically build perf with debug. This make command works through 6.11.0-rc6: $ make -C tools/perf DEBUG=1 VF=1 CORESIGHT=1 PYTHON=python3 CONFIG_LIBPYTHON=y CSLIBS=/usr/lib CSINCLUDES=/usr/include install I can substitute in the map__pgoff() macro in any case. Thanks, Steve > >> } >> if (al->sym) { >> pydict_set_item_string_decref(dict, sym_field, >> @@ -895,7 +898,7 @@ static PyObject *get_perf_sample_dict(struct perf_sample *sample, >> pydict_set_item_string_decref(dict, "comm", >> _PyUnicode_FromString(thread__comm_str(al->thread))); >> set_sym_in_dict(dict, al, "dso", "dso_bid", "dso_map_start", "dso_map_end", >> - "symbol", "symoff"); >> + "symbol", "symoff", "map_pgoff"); >> >> pydict_set_item_string_decref(dict, "callchain", callchain); >> >> @@ -920,7 +923,7 @@ static PyObject *get_perf_sample_dict(struct perf_sample *sample, >> PyBool_FromLong(1)); >> set_sym_in_dict(dict_sample, addr_al, "addr_dso", "addr_dso_bid", >> "addr_dso_map_start", "addr_dso_map_end", >> - "addr_symbol", "addr_symoff"); >> + "addr_symbol", "addr_symoff", "addr_map_pgoff"); >> } >> >> if (sample->flags) >> -- >> 2.44.0 >>

7 months, 3 weeks

[PATCH v1 RESEND 0/3] Add support to configure TPDM MCMB subunit

by Mao Jinlong

Introduction of TPDM MCMB(Multi-lane Continuous Multi Bit) subunit MCMB (Multi-lane CMB) is a special form of CMB dataset type. MCMB subunit has the same number and usage of registers as CMB subunit. Just like the CMB subunit, the MCMB subunit must be configured prior to enablement. This series adds support for TPDM to configure the MCMB subunit. Once this series patches are applied properly, the new tpdm nodes for should be observed at the tpdm path /sys/bus/coresight/devices/tpdm* which supports MCMB subunit. All sysfs files of CMB subunit TPDM are included in MCMB subunit TPDM. On this basis, MCMB subunit TPDM will have new sysfs files to select and enable the lane. Mao Jinlong (1): coresight-tpdm: Add MCMB dataset support Tao Zhang (2): coresight-tpdm: Add support to select lane coresight-tpdm: Add support to enable the lane for MCMB TPDM .../testing/sysfs-bus-coresight-devices-tpdm | 15 +++ drivers/hwtracing/coresight/coresight-tpda.c | 5 +- drivers/hwtracing/coresight/coresight-tpdm.c | 121 +++++++++++++++++- drivers/hwtracing/coresight/coresight-tpdm.h | 32 ++++- 4 files changed, 164 insertions(+), 9 deletions(-) -- 2.46.0

8 months

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