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Re: [PATCH v3 00/12] perf cs-etm/arm-spe: Remove hard coded config fields

by Arnaldo Carvalho de Melo

On Tue, Dec 16, 2025 at 01:00:32PM -0800, Ian Rogers wrote: > On Fri, Dec 12, 2025 at 7:32 AM James Clark <james.clark(a)linaro.org> wrote: > > > > The specific config field that an event format attribute is in is > > consistently hard coded, even though the API is supposed to be that the > > driver publishes the config field name. To stop this pattern from being > > copy pasted and causing problems in the future, replace them all with > > calls to a new helper that returns the value that a user set. > > > > This reveals some issues in evsel__set_config_if_unset(). It doesn't > > work with sparse bitfields, which are an unused but documented feature. > > And it also only writes to the attr.config field. To fix it we need to > > start tracking user changes for all config fields and then use existing > > helper functions that support sparse bitfields. Some other refactoring > > was also required and a test was added. > > > > Signed-off-by: James Clark <james.clark(a)linaro.org> > > Outside of some nits, for the series: > Reviewed-by: Ian Rogers <irogers(a)google.com> Are you ok with v4? - Arnaldo

8 months, 3 weeks

Re: [PATCH v10 2/7] qcom-tgu: Add TGU driver

by Suzuki K Poulose

On 09/01/2026 02:11, Songwei Chai wrote: > Add driver to support device TGU (Trigger Generation Unit). > TGU is a Data Engine which can be utilized to sense a plurality of > signals and create a trigger into the CTI or generate interrupts to > processors. Add probe/enable/disable functions for tgu. > > Signed-off-by: Songwei Chai <songwei.chai(a)oss.qualcomm.com> > --- > .../ABI/testing/sysfs-bus-amba-devices-tgu | 9 + > drivers/Makefile | 1 + > drivers/hwtracing/Kconfig | 2 + > drivers/hwtracing/qcom/Kconfig | 18 ++ > drivers/hwtracing/qcom/Makefile | 3 + > drivers/hwtracing/qcom/tgu.c | 176 ++++++++++++++++++ > drivers/hwtracing/qcom/tgu.h | 51 +++++ > 7 files changed, 260 insertions(+) > create mode 100644 Documentation/ABI/testing/sysfs-bus-amba-devices-tgu > create mode 100644 drivers/hwtracing/qcom/Kconfig > create mode 100644 drivers/hwtracing/qcom/Makefile > create mode 100644 drivers/hwtracing/qcom/tgu.c > create mode 100644 drivers/hwtracing/qcom/tgu.h > > diff --git a/Documentation/ABI/testing/sysfs-bus-amba-devices-tgu b/Documentation/ABI/testing/sysfs-bus-amba-devices-tgu > new file mode 100644 > index 000000000000..56ec3f5ab5d6 > --- /dev/null > +++ b/Documentation/ABI/testing/sysfs-bus-amba-devices-tgu > @@ -0,0 +1,9 @@ > +What: /sys/bus/amba/devices/<tgu-name>/enable_tgu > +Date: January 2026 > +KernelVersion 6.19 It's a bit too late for v6.19, this should rather be 6.20/7.0 Suzuki > +Contact: Jinlong Mao <jinlong.mao(a)oss.qualcomm.com>, Songwei Chai <songwei.chai(a)oss.qualcomm.com> > +Description: > + (RW) Set/Get the enable/disable status of TGU > + Accepts only one of the 2 values - 0 or 1. > + 0 : disable TGU. > + 1 : enable TGU. > diff --git a/drivers/Makefile b/drivers/Makefile > index ccc05f1eae3e..9608a3debb1f 100644 > --- a/drivers/Makefile > +++ b/drivers/Makefile > @@ -177,6 +177,7 @@ obj-$(CONFIG_RAS) += ras/ > obj-$(CONFIG_USB4) += thunderbolt/ > obj-$(CONFIG_CORESIGHT) += hwtracing/coresight/ > obj-y += hwtracing/intel_th/ > +obj-y += hwtracing/qcom/ > obj-$(CONFIG_STM) += hwtracing/stm/ > obj-$(CONFIG_HISI_PTT) += hwtracing/ptt/ > obj-y += android/ > diff --git a/drivers/hwtracing/Kconfig b/drivers/hwtracing/Kconfig > index 911ee977103c..8a640218eed8 100644 > --- a/drivers/hwtracing/Kconfig > +++ b/drivers/hwtracing/Kconfig > @@ -7,4 +7,6 @@ source "drivers/hwtracing/intel_th/Kconfig" > > source "drivers/hwtracing/ptt/Kconfig" > > +source "drivers/hwtracing/qcom/Kconfig" > + > endmenu > diff --git a/drivers/hwtracing/qcom/Kconfig b/drivers/hwtracing/qcom/Kconfig > new file mode 100644 > index 000000000000..d6f6d4b0f28e > --- /dev/null > +++ b/drivers/hwtracing/qcom/Kconfig > @@ -0,0 +1,18 @@ > +# SPDX-License-Identifier: GPL-2.0-only > +# > +# QCOM specific hwtracing drivers > +# > +menu "Qualcomm specific hwtracing drivers" > + > +config QCOM_TGU > + tristate "QCOM Trigger Generation Unit driver" > + help > + This driver provides support for Trigger Generation Unit that is > + used to detect patterns or sequences on a given set of signals. > + TGU is used to monitor a particular bus within a given region to > + detect illegal transaction sequences or slave responses. It is also > + used to monitor a data stream to detect protocol violations and to > + provide a trigger point for centering data around a specific event > + within the trace data buffer. > + > +endmenu > diff --git a/drivers/hwtracing/qcom/Makefile b/drivers/hwtracing/qcom/Makefile > new file mode 100644 > index 000000000000..5a0a868c1ea0 > --- /dev/null > +++ b/drivers/hwtracing/qcom/Makefile > @@ -0,0 +1,3 @@ > +# SPDX-License-Identifier: GPL-2.0 > + > +obj-$(CONFIG_QCOM_TGU) += tgu.o > diff --git a/drivers/hwtracing/qcom/tgu.c b/drivers/hwtracing/qcom/tgu.c > new file mode 100644 > index 000000000000..c5b2b384e6ae > --- /dev/null > +++ b/drivers/hwtracing/qcom/tgu.c > @@ -0,0 +1,176 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. > + */ > + > +#include <linux/amba/bus.h> > +#include <linux/device.h> > +#include <linux/err.h> > +#include <linux/io.h> > +#include <linux/kernel.h> > +#include <linux/module.h> > +#include <linux/of.h> > +#include <linux/pm_runtime.h> > + > +#include "tgu.h" > + > +static void tgu_write_all_hw_regs(struct tgu_drvdata *drvdata) > +{ > + TGU_UNLOCK(drvdata->base); > + /* Enable TGU to program the triggers */ > + writel(1, drvdata->base + TGU_CONTROL); > + TGU_LOCK(drvdata->base); > +} > + > +static int tgu_enable(struct device *dev) > +{ > + struct tgu_drvdata *drvdata = dev_get_drvdata(dev); > + > + guard(spinlock)(&drvdata->lock); > + if (drvdata->enable) > + return -EBUSY; > + > + tgu_write_all_hw_regs(drvdata); > + drvdata->enable = true; > + > + return 0; > +} > + > +static void tgu_disable(struct device *dev) > +{ > + struct tgu_drvdata *drvdata = dev_get_drvdata(dev); > + > + guard(spinlock)(&drvdata->lock); > + if (drvdata->enable) { > + TGU_UNLOCK(drvdata->base); > + writel(0, drvdata->base + TGU_CONTROL); > + TGU_LOCK(drvdata->base); > + > + drvdata->enable = false; > + } > +} > + > +static ssize_t enable_tgu_show(struct device *dev, > + struct device_attribute *attr, char *buf) > +{ > + struct tgu_drvdata *drvdata = dev_get_drvdata(dev); > + bool enabled; > + > + guard(spinlock)(&drvdata->lock); > + enabled = drvdata->enable; > + > + return sysfs_emit(buf, "%d\n", enabled ? 1 : 0); > +} > + > +/* enable_tgu_store - Configure Trace and Gating Unit (TGU) triggers. */ > +static ssize_t enable_tgu_store(struct device *dev, > + struct device_attribute *attr, > + const char *buf, > + size_t size) > +{ > + unsigned long val; > + int ret = 0; > + > + ret = kstrtoul(buf, 0, &val); > + if (ret) > + return ret; > + > + if (val) { > + ret = pm_runtime_resume_and_get(dev); > + if (ret) > + return ret; > + ret = tgu_enable(dev); > + if (ret) { > + pm_runtime_put(dev); > + return ret; > + } > + } else { > + tgu_disable(dev); > + pm_runtime_put(dev); > + } > + > + return size; > +} > +static DEVICE_ATTR_RW(enable_tgu); > + > +static struct attribute *tgu_common_attrs[] = { > + &dev_attr_enable_tgu.attr, > + NULL, > +}; > + > +static const struct attribute_group tgu_common_grp = { > + .attrs = tgu_common_attrs, > + NULL, > +}; > + > +static const struct attribute_group *tgu_attr_groups[] = { > + &tgu_common_grp, > + NULL, > +}; > + > +static int tgu_probe(struct amba_device *adev, const struct amba_id *id) > +{ > + struct device *dev = &adev->dev; > + struct tgu_drvdata *drvdata; > + int ret; > + > + drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL); > + if (!drvdata) > + return -ENOMEM; > + > + drvdata->dev = &adev->dev; > + dev_set_drvdata(dev, drvdata); > + > + drvdata->base = devm_ioremap_resource(dev, &adev->res); > + if (IS_ERR(drvdata->base)) > + return PTR_ERR(drvdata->base); > + > + spin_lock_init(&drvdata->lock); > + > + ret = sysfs_create_groups(&dev->kobj, tgu_attr_groups); > + if (ret) { > + dev_err(dev, "failed to create sysfs groups: %d\n", ret); > + return ret; > + } > + > + drvdata->enable = false; > + > + pm_runtime_put(&adev->dev); > + return 0; > +} > + > +static void tgu_remove(struct amba_device *adev) > +{ > + struct device *dev = &adev->dev; > + > + sysfs_remove_groups(&dev->kobj, tgu_attr_groups); > + > + tgu_disable(dev); > +} > + > +static const struct amba_id tgu_ids[] = { > + { > + .id = 0x000f0e00, > + .mask = 0x000fffff, > + }, > + { 0, 0, NULL }, > +}; > + > +MODULE_DEVICE_TABLE(amba, tgu_ids); > + > +static struct amba_driver tgu_driver = { > + .drv = { > + .name = "qcom-tgu", > + .suppress_bind_attrs = true, > + }, > + .probe = tgu_probe, > + .remove = tgu_remove, > + .id_table = tgu_ids, > +}; > + > +module_amba_driver(tgu_driver); > + > +MODULE_AUTHOR("Songwei Chai <songwei.chai(a)oss.qualcomm.com>"); > +MODULE_AUTHOR("Jinlong Mao <jinlong.mao(a)oss.qualcomm.com>"); > +MODULE_DESCRIPTION("Qualcomm Trigger Generation Unit driver"); > +MODULE_LICENSE("GPL"); > diff --git a/drivers/hwtracing/qcom/tgu.h b/drivers/hwtracing/qcom/tgu.h > new file mode 100644 > index 000000000000..b11cfb28261d > --- /dev/null > +++ b/drivers/hwtracing/qcom/tgu.h > @@ -0,0 +1,51 @@ > +/* SPDX-License-Identifier: GPL-2.0 */ > +/* > + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. > + */ > + > +#ifndef _QCOM_TGU_H > +#define _QCOM_TGU_H > + > +/* Register addresses */ > +#define TGU_CONTROL 0x0000 > +#define TGU_LAR 0xfb0 > +#define TGU_UNLOCK_OFFSET 0xc5acce55 > + > +static inline void TGU_LOCK(void __iomem *addr) > +{ > + do { > + /* Wait for things to settle */ > + mb(); > + writel_relaxed(0x0, addr + TGU_LAR); > + } while (0); > +} > + > +static inline void TGU_UNLOCK(void __iomem *addr) > +{ > + do { > + writel_relaxed(TGU_UNLOCK_OFFSET, addr + TGU_LAR); > + /* Make sure everyone has seen this */ > + mb(); > + } while (0); > +} > + > +/** > + * struct tgu_drvdata - Data structure for a TGU (Trigger Generator Unit) > + * @base: Memory-mapped base address of the TGU device > + * @dev: Pointer to the associated device structure > + * @lock: Spinlock for handling concurrent access > + * @enable: Flag indicating whether the TGU device is enabled > + * > + * This structure defines the data associated with a TGU device, > + * including its base address, device pointers, clock, spinlock for > + * synchronization, trigger data pointers, maximum limits for various > + * trigger-related parameters, and enable status. > + */ > +struct tgu_drvdata { > + void __iomem *base; > + struct device *dev; > + spinlock_t lock; > + bool enable; > +}; > + > +#endif

9 months

Re: [PATCH v9 7/7] qcom-tgu: Add reset node to initialize

by Suzuki K Poulose

On 19/12/2025 06:59, Songwei Chai wrote: > Add reset node to initialize the value of > priority/condition_decode/condition_select/timer/counter nodes. > > Signed-off-by: Songwei Chai <songwei.chai(a)oss.qualcomm.com> > --- > .../ABI/testing/sysfs-bus-amba-devices-tgu | 7 ++ > drivers/hwtracing/qcom/tgu.c | 74 +++++++++++++++++++ > 2 files changed, 81 insertions(+) > > diff --git a/Documentation/ABI/testing/sysfs-bus-amba-devices-tgu b/Documentation/ABI/testing/sysfs-bus-amba-devices-tgu > index 010eade0a1c5..0733b3e07b45 100644 > --- a/Documentation/ABI/testing/sysfs-bus-amba-devices-tgu > +++ b/Documentation/ABI/testing/sysfs-bus-amba-devices-tgu > @@ -42,3 +42,10 @@ KernelVersion 6.19 > Contact: Jinlong Mao <jinlong.mao(a)oss.qualcomm.com>, Songwei Chai <songwei.chai(a)oss.qualcomm.com> > Description: > (RW) Set/Get the counter value with specific step for TGU. > + > +What: /sys/bus/amba/devices/<tgu-name>/reset_tgu > +Date: December 2025 > +KernelVersion 6.19 > +Contact: Jinlong Mao <jinlong.mao(a)oss.qualcomm.com>, Songwei Chai <songwei.chai(a)oss.qualcomm.com> > +Description: > + (Write) Write 1 to reset the dataset for TGU. > diff --git a/drivers/hwtracing/qcom/tgu.c b/drivers/hwtracing/qcom/tgu.c > index d4210869556e..5a8c6af9b719 100644 > --- a/drivers/hwtracing/qcom/tgu.c > +++ b/drivers/hwtracing/qcom/tgu.c > @@ -425,8 +425,82 @@ static ssize_t enable_tgu_store(struct device *dev, > + > + dev_dbg(dev, "Coresight-TGU reset complete\n"); Qualcomm-TGU ? Suzuki

9 months

Re: [PATCH v8 0/4] add sysfs nodes to configure TPDA's registers

by Suzuki K Poulose

On Tue, 23 Dec 2025 18:09:49 +0800, Jie Gan wrote: > Patchset 1 introduces configuration of the global control register with > appropriate values to enable proper generation of cross-trigger packets. > > Patchset 2 introduces a sysfs node for triggering global flush for all > ports. > > Patchset 3 introduces a logic to configure the TPDA_SYNCR register, > which determines the frequency of ASYNC packet generation. These packets > assist userspace tools in accurately identifying each valid packet. > > [...] Applied, thanks! [1/4] coresight: tpda: add sysfs nodes for tpda cross-trigger configuration https://git.kernel.org/coresight/c/f9cc5b5a9e9a [2/4] coresight: tpda: add global_flush_req sysfs node https://git.kernel.org/coresight/c/8e1c358a3b0e [3/4] coresight: tpda: add logic to configure TPDA_SYNCR register https://git.kernel.org/coresight/c/33f04ead7c49 [4/4] coresight: tpda: add sysfs node to flush specific port https://git.kernel.org/coresight/c/a089d585a7f4 Best regards, -- Suzuki K Poulose <suzuki.poulose(a)arm.com>

9 months

[PATCH v8 00/13] coresight: Update timestamp attribute to be an interval instead of bool

by James Clark

Do some cleanups then expand the timestamp format attribute from 1 bit to 4 bits for ETMv4 in Perf mode. The current interval is too high for most use cases, and particularly on the FVP the number of timestamps generated is excessive. This change not only still allows disabling or enabling timestamps, but also allows the interval to be configured. The old bit is kept deprecated and undocumented for now. There are known broken versions of Perf that don't read the format attribute positions from sysfs and instead hard code the timestamp bit. We can leave the old bit in the driver until we need the bit for another feature or enough time has passed that these old Perfs are unlikely to be used. The interval option is added as an event format attribute, rather than a Coresight config because it's something that the driver is already configuring automatically in Perf mode using any unused counter, so it's not possible to modify this with a config. Applies to coresight/next Signed-off-by: James Clark <james.clark(a)linaro.org> --- Changes in v8: - Handle ts_level attribute outside etm4_config_timestamp_event() (Mike) - Flip commits 11 and 12 so that the new attribute works as soon as it's published to sysfs for bisecting (Suzuki) - Remove some spurious header includes - Link to v7: https://lore.kernel.org/r/20251126-james-cs-syncfreq-v7-0-7fae5e0e5e16@lina… Changes in v7: - Change TRCCNTCTLRn and TRCTSCTLR register definitions to use a combined field for TYPE and SEL (EVENT) so that they can be used with the new utilities. - Add utility functions for creating resource selectors that do compile and runtime checking of the resource selector ID. - Link to v6: https://lore.kernel.org/r/20251119-james-cs-syncfreq-v6-0-740d24a29e51@lina… Changes in v6: - #ifdef out format attributes for ETMv3 instead of using is_visible(). Then the same block can be used to define format_attr_contextid_show() which avoids an awkward WARN_ONCE() and comments in arm32 for a function that's never called. - Link to v5: https://lore.kernel.org/r/20251118-james-cs-syncfreq-v5-0-82efd7b1a751@lina… Changes in v5: - Add parens to interval calculation in docs (Randy) - Swap "minimum interval" and "maximum interval" in docs. (Leo) - Add TRCSYNCPR.PERIOD to docs (Leo) - Use CONFIG_ARM64 to avoid is_kernel_in_hyp_mode() (Leo) - Add a comment for hidden ETMv3 format attributes (Leo) - Hide configid for ETMv3 (Leo) - Link to v4: https://lore.kernel.org/r/20251112-james-cs-syncfreq-v4-0-165ba21401dc@lina… Changes in v4: - Add #defines for true and false resources ETM_RES_SEL_TRUE/FALSE - Reword comment about finding a counter to say if there are no resources there are no counters. - Extend existing timestamp format attribute instead of adding a new one - Refactor all the config definitions and parsing to use GEN_PMU_FORMAT_ATTR()/ATTR_CFG_GET_FLD() so we can see where the unused bits are. - Link to v3: https://lore.kernel.org/r/20251002-james-cs-syncfreq-v3-0-fe5df2bf91d1@lina… Changes in v3: - Move the format attr definitions to coresight-etm-perf.h we can compile on arm32 without #ifdefs - (Leo) - Convert the new #ifdefs to a single one in an is_visible() function so that the code is cleaner - (Leo) - Drop the change to remove the holes in struct etmv4_config as they were grouped by function - (Mike) - Link to v2: https://lore.kernel.org/r/20250814-james-cs-syncfreq-v2-0-c76fcb87696d@lina… Changes in v2: - Only show the attribute for ETMv4 to improve usability and fix the arm32 build error. Wrapping everything in IS_ENABLED(CONFIG_CORESIGHT_SOURCE_ETM4X) isn't ideal, but the -perf.c file is shared between ETMv3 and ETMv4, and there is already precedent for doing it this way. - Link to v1: https://lore.kernel.org/r/20250811-james-cs-syncfreq-v1-0-b001cd6e3404@lina… --- James Clark (13): coresight: Change syncfreq to be a u8 coresight: Repack struct etmv4_drvdata coresight: Refactor etm4_config_timestamp_event() coresight: Hide unused ETMv3 format attributes coresight: Define format attributes with GEN_PMU_FORMAT_ATTR() coresight: Interpret ETMv3 config with ATTR_CFG_GET_FLD() coresight: Don't reject unrecognized ETMv3 format attributes coresight: Interpret perf config with ATTR_CFG_GET_FLD() coresight: Interpret ETMv4 config with ATTR_CFG_GET_FLD() coresight: Remove misleading definitions coresight: Prepare to allow setting the timestamp interval coresight: Extend width of timestamp format attribute coresight: docs: Document etm4x timestamp interval option Documentation/trace/coresight/coresight.rst | 16 +- drivers/hwtracing/coresight/coresight-etm-perf.c | 68 ++++---- drivers/hwtracing/coresight/coresight-etm-perf.h | 38 +++++ drivers/hwtracing/coresight/coresight-etm3x-core.c | 39 +++-- drivers/hwtracing/coresight/coresight-etm4x-core.c | 175 ++++++++++++--------- drivers/hwtracing/coresight/coresight-etm4x.h | 92 ++++++++--- include/linux/coresight-pmu.h | 24 --- 7 files changed, 279 insertions(+), 173 deletions(-) --- base-commit: 9e9182cab5ebc3ee7544e60ef08ba19fdf216920 change-id: 20250724-james-cs-syncfreq-7c2257a38ed3 Best regards, -- James Clark <james.clark(a)linaro.org>

9 months

[PATCH] MAINTAINERS: Change of email address

by Mike Leach

My e-mail address for linux work is changing to mike.leach(a)arm.com from 1st Jan 2026. Update MAINTAINERS file accordingly Signed-off-by: Mike Leach <mike.leach(a)linaro.org> --- MAINTAINERS | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index 5b11839cba9d..e3974f9f300a 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2657,7 +2657,7 @@ N: digicolor ARM/CORESIGHT FRAMEWORK AND DRIVERS M: Suzuki K Poulose <suzuki.poulose(a)arm.com> -R: Mike Leach <mike.leach(a)linaro.org> +R: Mike Leach <mike.leach(a)arm.com> R: James Clark <james.clark(a)linaro.org> L: coresight(a)lists.linaro.org (moderated for non-subscribers) L: linux-arm-kernel(a)lists.infradead.org (moderated for non-subscribers) @@ -20476,7 +20476,7 @@ PERFORMANCE EVENTS TOOLING ARM64 R: John Garry <john.g.garry(a)oracle.com> R: Will Deacon <will(a)kernel.org> R: James Clark <james.clark(a)linaro.org> -R: Mike Leach <mike.leach(a)linaro.org> +R: Mike Leach <mike.leach(a)arm.com> R: Leo Yan <leo.yan(a)linux.dev> L: linux-arm-kernel(a)lists.infradead.org (moderated for non-subscribers) S: Supported -- 2.32.0

9 months

[PATCH v4 0/3] Coresight TMC-ETR: refactor the tmc-etr mode and some cleanups

by Junhao He

This patchset builds upon Yicong's previous patches [1]. Patch 2 introducing fix race issues found by using TMC-ETR. Patch 1 & 3 introducing two cleanups found when debugging the issues. [1] https://lore.kernel.org/linux-arm-kernel/20241202092419.11777-1-yangyicong@… --- Changes in v4: - a) Add comment at the context of set etr to sysfs mode. - b) Move the check on drvdata->read to the start of enable etr. - c) Add checks to prevent multiple sysfs processes from simultaneously competing to enable ETR. - d) Fix the issue with the guard used. Link: https://lore.kernel.org/linux-arm-kernel/20250818080600.418425-1-hejunhao3@… --- Changes in v3: - Patches 1: Additional comment for tmc_drvdata::etr_mode. Update comment for tmc_drvdata::reading with Jonathan's Tag. - Patches 2: Replace scoped_guard with guard with Jonathan's Tag. - Patches 2: Fix spinlock to raw_spinlock, and refactor this code based on Leo's suggested solution. - Patches 3: change the size's type to ssize_t and use max_t to simplify the code with Leo's Tag. Link: https://lore.kernel.org/linux-arm-kernel/20250620075412.952934-1-hejunhao3@… Changes in v2: - Updated the commit of patch2. - Rebase to v6.16-rc1 Junhao He (1): coresight: tmc: refactor the tmc-etr mode setting to avoid race conditions Yicong Yang (2): coresight: tmc: Add missing doc including reading and etr_mode of struct tmc_drvdata coresight: tmc: Decouple the perf buffer allocation from sysfs mode .../hwtracing/coresight/coresight-tmc-etr.c | 136 +++++++++--------- drivers/hwtracing/coresight/coresight-tmc.h | 2 + 2 files changed, 66 insertions(+), 72 deletions(-) -- 2.33.0

9 months, 1 week

Re: [PATCH v7 3/4] coresight: tpda: add logic to configure TPDA_SYNCR register

by Suzuki K Poulose

On 23/12/2025 08:41, Jie Gan wrote: > From: Tao Zhang <tao.zhang(a)oss.qualcomm.com> > > The TPDA_SYNC counter tracks the number of bytes transferred from the > aggregator. When this count reaches the value programmed in the > TPDA_SYNCR register, an ASYNC request is triggered, allowing userspace > tools to accurately parse each valid packet. > > Signed-off-by: Tao Zhang <tao.zhang(a)oss.qualcomm.com> > Reviewed-by: James Clark <james.clark(a)linaro.org> > Co-developed-by: Jie Gan <jie.gan(a)oss.qualcomm.com> > Signed-off-by: Jie Gan <jie.gan(a)oss.qualcomm.com> > --- > .../ABI/testing/sysfs-bus-coresight-devices-tpda | 18 +++++ > drivers/hwtracing/coresight/coresight-tpda.c | 90 ++++++++++++++++++++++ > drivers/hwtracing/coresight/coresight-tpda.h | 10 +++ > 3 files changed, 118 insertions(+) > > diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpda b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpda > index c8bc7b19ab25..c989eea1ef59 100644 > --- a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpda > +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpda > @@ -41,3 +41,21 @@ Contact: Jinlong Mao <jinlong.mao(a)oss.qualcomm.com>, Tao Zhang <tao.zhang(a)oss.qu > Description: > (RW) Set global (all ports) flush request bit. The bit remains set until a > global flush request sequence completes. > + > +What: /sys/bus/coresight/devices/<tpda-name>/syncr_mode > +Date: December 2025 > +KernelVersion: 6.19 > +Contact: Jinlong Mao <jinlong.mao(a)oss.qualcomm.com>, Tao Zhang <tao.zhang(a)oss.qualcomm.com>, Jie Gan <jie.gan(a)oss.qualcomm.com> > +Description: > + (RW) Set mode the of the syncr counter. > + mode 0 - COUNT[11:0] value represents the approximate number of bytes moved between two ASYNC packet requests > + mode 1 - the bits COUNT[11:7] are used as a power of 2. for example, we could insert an async packet every 8K > + data by writing a value 13 to the COUNT[11:7] field. > + > +What: /sys/bus/coresight/devices/<tpda-name>/syncr_count > +Date: December 2025 > +KernelVersion: 6.19 > +Contact: Jinlong Mao <jinlong.mao(a)oss.qualcomm.com>, Tao Zhang <tao.zhang(a)oss.qualcomm.com>, Jie Gan <jie.gan(a)oss.qualcomm.com> > +Description: > + (RW) Set value the of the syncr counter. > + Range: 0-4095 > diff --git a/drivers/hwtracing/coresight/coresight-tpda.c b/drivers/hwtracing/coresight/coresight-tpda.c > index d24a9098f1b1..8283e16ec400 100644 > --- a/drivers/hwtracing/coresight/coresight-tpda.c > +++ b/drivers/hwtracing/coresight/coresight-tpda.c > @@ -163,6 +163,20 @@ static void tpda_enable_pre_port(struct tpda_drvdata *drvdata) > */ > if (drvdata->trig_flag_ts) > writel_relaxed(0x0, drvdata->base + TPDA_FPID_CR); > + > + /* Initialize with a value of 0 */ > + val = 0; > + if (drvdata->syncr_mode) > + val |= TPDA_SYNCR_MODE_CTRL_MASK; > + > + if (drvdata->syncr_count > 0 && > + drvdata->syncr_count < TPDA_SYNCR_COUNT_MASK) > + val |= drvdata->syncr_count; > + else > + /* Program the count to its MAX value by default */ > + val |= TPDA_SYNCR_COUNT_MASK; > + > + writel_relaxed(val, drvdata->base + TPDA_SYNCR); > } > > static int tpda_enable_port(struct tpda_drvdata *drvdata, int port) > @@ -385,8 +399,84 @@ static ssize_t global_flush_req_store(struct device *dev, > } > static DEVICE_ATTR_RW(global_flush_req); > > +static ssize_t syncr_mode_show(struct device *dev, > + struct device_attribute *attr, > + char *buf) > +{ > + struct tpda_drvdata *drvdata = dev_get_drvdata(dev->parent); > + unsigned long val, syncr_val; > + > + if (!drvdata->csdev->refcnt) > + return -EINVAL; > + > + guard(spinlock)(&drvdata->spinlock); > + syncr_val = readl_relaxed(drvdata->base + TPDA_SYNCR); > + val = FIELD_GET(TPDA_SYNCR_MODE_CTRL_MASK, syncr_val); > + > + return sysfs_emit(buf, "%lu\n", val); > +} > + > +static ssize_t syncr_mode_store(struct device *dev, > + struct device_attribute *attr, > + const char *buf, > + size_t size) > +{ > + struct tpda_drvdata *drvdata = dev_get_drvdata(dev->parent); > + unsigned long val; > + > + if (kstrtoul(buf, 0, &val)) > + return -EINVAL; > + > + guard(spinlock)(&drvdata->spinlock); > + /* set the mode when first enabling the device */ > + drvdata->syncr_mode = !!val; > + > + return size; > +} > +static DEVICE_ATTR_RW(syncr_mode); > + > +static ssize_t syncr_count_show(struct device *dev, > + struct device_attribute *attr, > + char *buf) > +{ > + struct tpda_drvdata *drvdata = dev_get_drvdata(dev->parent); > + unsigned long val; > + > + if (!drvdata->csdev->refcnt) > + return -EINVAL; > + > + guard(spinlock)(&drvdata->spinlock); > + val = readl_relaxed(drvdata->base + TPDA_SYNCR); > + val &= TPDA_SYNCR_COUNT_MASK; > + > + return sysfs_emit(buf, "%lu\n", val); > +} > + > +static ssize_t syncr_count_store(struct device *dev, > + struct device_attribute *attr, > + const char *buf, > + size_t size) > +{ > + struct tpda_drvdata *drvdata = dev_get_drvdata(dev->parent); > + unsigned long val; > + > + if (kstrtoul(buf, 0, &val)) > + return -EINVAL; > + > + if (val < 0 || val > TPDA_SYNCR_COUNT_MASK) Checking "val < 0" for an unsigned type is invalid. Simply keep the second part. Suzuki > + return -EINVAL; > + > + guard(spinlock)(&drvdata->spinlock); > + drvdata->syncr_count = val; > + > + return size; > +} > +static DEVICE_ATTR_RW(syncr_count); > + > static struct attribute *tpda_attrs[] = { > &dev_attr_global_flush_req.attr, > + &dev_attr_syncr_mode.attr, > + &dev_attr_syncr_count.attr, > tpda_trig_sysfs_rw(freq_ts_enable, FREQTS), > tpda_trig_sysfs_rw(trig_freq_enable, FRIE), > tpda_trig_sysfs_rw(trig_flag_ts_enable, FLRIE), > diff --git a/drivers/hwtracing/coresight/coresight-tpda.h b/drivers/hwtracing/coresight/coresight-tpda.h > index 1cc9253293ec..56d35697303a 100644 > --- a/drivers/hwtracing/coresight/coresight-tpda.h > +++ b/drivers/hwtracing/coresight/coresight-tpda.h > @@ -9,6 +9,7 @@ > #define TPDA_CR (0x000) > #define TPDA_Pn_CR(n) (0x004 + (n * 4)) > #define TPDA_FPID_CR (0x084) > +#define TPDA_SYNCR (0x08C) > > /* Cross trigger global (all ports) flush request bit */ > #define TPDA_CR_FLREQ BIT(0) > @@ -36,6 +37,11 @@ > /* Aggregator port DSB data set element size bit */ > #define TPDA_Pn_CR_DSBSIZE BIT(8) > > +/* TPDA_SYNCR count mask */ > +#define TPDA_SYNCR_COUNT_MASK GENMASK(11, 0) > +/* TPDA_SYNCR mode control bit */ > +#define TPDA_SYNCR_MODE_CTRL_MASK GENMASK(12, 12) > + > #define TPDA_MAX_INPORTS 32 > > /** > @@ -52,6 +58,8 @@ > * @trig_freq: Enable/disable cross trigger FREQ packet request interface. > * @freq_ts: Enable/disable the timestamp for all FREQ packets. > * @cmbchan_mode: Configure the CMB/MCMB channel mode. > + * @syncr_mode: Setting the mode for counting packets. > + * @syncr_count: Setting the value of the count. > */ > struct tpda_drvdata { > void __iomem *base; > @@ -66,6 +74,8 @@ struct tpda_drvdata { > bool trig_freq; > bool freq_ts; > bool cmbchan_mode; > + bool syncr_mode; > + u32 syncr_count; > }; > > /* Enumerate members of global control register(cr) */ >

9 months, 2 weeks

Re: [PATCH v6 4/4] coresight: tpda: add sysfs node to flush specific port

by Suzuki K Poulose

On 23/12/2025 02:16, Jie Gan wrote: > > > On 12/22/2025 9:12 PM, Suzuki K Poulose wrote: >> On 22/12/2025 06:02, Jie Gan wrote: >>> From: Tao Zhang <tao.zhang(a)oss.qualcomm.com> >>> >>> Setting bit i in the TPDA_FLUSH_CR register initiates a flush request >>> for port i, forcing the data to synchronize and be transmitted to the >>> sink device. >>> >>> Signed-off-by: Tao Zhang <tao.zhang(a)oss.qualcomm.com> >>> Reviewed-by: James Clark <james.clark(a)linaro.org> >>> Co-developed-by: Jie Gan <jie.gan(a)oss.qualcomm.com> >>> Signed-off-by: Jie Gan <jie.gan(a)oss.qualcomm.com> >>> --- >>> .../ABI/testing/sysfs-bus-coresight-devices-tpda | 7 ++++ >>> drivers/hwtracing/coresight/coresight-tpda.c | 40 +++++++++++ >>> + ++++++++++ >>> drivers/hwtracing/coresight/coresight-tpda.h | 1 + >>> 3 files changed, 48 insertions(+) >>> >>> diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices- >>> tpda b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpda >>> index d359d90dca72..df8f03d4b573 100644 >>> --- a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpda >>> +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpda >>> @@ -51,3 +51,10 @@ Description: >>> mode 0 - COUNT[11:0] value represents the approximate >>> number of bytes moved between two ASYNC packet requests >>> mode 1 - the bits COUNT[11:7] are used as a power of 2. for >>> example, we could insert an async packet every 8K >>> data by writing a value 13 to the COUNT[11:7] field. >>> + >>> +What: /sys/bus/coresight/devices/<tpda-name>/port_flush_req >>> +Date: December 2025 >>> +KernelVersion: 6.19 >>> +Contact: Jinlong Mao <jinlong.mao(a)oss.qualcomm.com>, Tao Zhang >>> <tao.zhang(a)oss.qualcomm.com>, Jie Gan <jie.gan(a)oss.qualcomm.com> >>> +Description: >>> + (RW) Configure the bit i to requests a flush operation of >>> port i on the TPDA. >> >> Does this have similar semantics as the "global_flush_req" for "Read" ? > > Yes, global_flush_req triggers all ports at once, whereas this node > initiates a flush request for specific port(s). > > For reading, we can check whether the flush request has completed. Please document it as such. Suzuki > > Thanks, > Jie > >> i.e., the bit stays set until the request completes ? Otherwise, why >> isn't this Write only ? >> >> I don't see the point of "Reading" this value back. >> >> Suzuki >> >>> diff --git a/drivers/hwtracing/coresight/coresight-tpda.c b/drivers/ >>> hwtracing/coresight/coresight-tpda.c >>> index 7baa8a0965d3..f79fea4fbb2c 100644 >>> --- a/drivers/hwtracing/coresight/coresight-tpda.c >>> +++ b/drivers/hwtracing/coresight/coresight-tpda.c >>> @@ -430,9 +430,49 @@ static ssize_t syncr_mode_store(struct device *dev, >>> } >>> static DEVICE_ATTR_RW(syncr_mode); >>> +static ssize_t port_flush_req_show(struct device *dev, >>> + struct device_attribute *attr, >>> + char *buf) >>> +{ >>> + struct tpda_drvdata *drvdata = dev_get_drvdata(dev->parent); >>> + unsigned long val; >>> + >>> + if (!drvdata->csdev->refcnt) >>> + return -EINVAL; >>> + >>> + guard(spinlock)(&drvdata->spinlock); >>> + val = readl_relaxed(drvdata->base + TPDA_FLUSH_CR); >>> + >>> + return sysfs_emit(buf, "0x%lx\n", val); >>> +} >>> + >>> +static ssize_t port_flush_req_store(struct device *dev, >>> + struct device_attribute *attr, >>> + const char *buf, >>> + size_t size) >>> +{ >>> + struct tpda_drvdata *drvdata = dev_get_drvdata(dev->parent); >>> + u32 val; >>> + >>> + if (kstrtou32(buf, 0, &val)) >>> + return -EINVAL; >>> + >>> + if (!drvdata->csdev->refcnt || !val) >>> + return -EINVAL; >>> + >>> + guard(spinlock)(&drvdata->spinlock); >>> + CS_UNLOCK(drvdata->base); >>> + writel_relaxed(val, drvdata->base + TPDA_FLUSH_CR); >>> + CS_LOCK(drvdata->base); >>> + >>> + return size; >>> +} >>> +static DEVICE_ATTR_RW(port_flush_req); >>> + >>> static struct attribute *tpda_attrs[] = { >>> &dev_attr_global_flush_req.attr, >>> &dev_attr_syncr_mode.attr, >>> + &dev_attr_port_flush_req.attr, >>> tpda_trig_sysfs_rw(freq_ts_enable, FREQTS), >>> tpda_trig_sysfs_rw(trig_freq_enable, FRIE), >>> tpda_trig_sysfs_rw(trig_flag_ts_enable, FLRIE), >>> diff --git a/drivers/hwtracing/coresight/coresight-tpda.h b/drivers/ >>> hwtracing/coresight/coresight-tpda.h >>> index 1d2de50bb9f9..ef1ce2ce36a9 100644 >>> --- a/drivers/hwtracing/coresight/coresight-tpda.h >>> +++ b/drivers/hwtracing/coresight/coresight-tpda.h >>> @@ -10,6 +10,7 @@ >>> #define TPDA_Pn_CR(n) (0x004 + (n * 4)) >>> #define TPDA_FPID_CR (0x084) >>> #define TPDA_SYNCR (0x08C) >>> +#define TPDA_FLUSH_CR (0x090) >>> /* Cross trigger global (all ports) flush request bit */ >>> #define TPDA_CR_FLREQ BIT(0) >>> >> >

9 months, 2 weeks

Re: [PATCH v6 4/4] coresight: tpda: add sysfs node to flush specific port

by Suzuki K Poulose

On 22/12/2025 06:02, Jie Gan wrote: > From: Tao Zhang <tao.zhang(a)oss.qualcomm.com> > > Setting bit i in the TPDA_FLUSH_CR register initiates a flush request > for port i, forcing the data to synchronize and be transmitted to the > sink device. > > Signed-off-by: Tao Zhang <tao.zhang(a)oss.qualcomm.com> > Reviewed-by: James Clark <james.clark(a)linaro.org> > Co-developed-by: Jie Gan <jie.gan(a)oss.qualcomm.com> > Signed-off-by: Jie Gan <jie.gan(a)oss.qualcomm.com> > --- > .../ABI/testing/sysfs-bus-coresight-devices-tpda | 7 ++++ > drivers/hwtracing/coresight/coresight-tpda.c | 40 ++++++++++++++++++++++ > drivers/hwtracing/coresight/coresight-tpda.h | 1 + > 3 files changed, 48 insertions(+) > > diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpda b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpda > index d359d90dca72..df8f03d4b573 100644 > --- a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpda > +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpda > @@ -51,3 +51,10 @@ Description: > mode 0 - COUNT[11:0] value represents the approximate number of bytes moved between two ASYNC packet requests > mode 1 - the bits COUNT[11:7] are used as a power of 2. for example, we could insert an async packet every 8K > data by writing a value 13 to the COUNT[11:7] field. > + > +What: /sys/bus/coresight/devices/<tpda-name>/port_flush_req > +Date: December 2025 > +KernelVersion: 6.19 > +Contact: Jinlong Mao <jinlong.mao(a)oss.qualcomm.com>, Tao Zhang <tao.zhang(a)oss.qualcomm.com>, Jie Gan <jie.gan(a)oss.qualcomm.com> > +Description: > + (RW) Configure the bit i to requests a flush operation of port i on the TPDA. Does this have similar semantics as the "global_flush_req" for "Read" ? i.e., the bit stays set until the request completes ? Otherwise, why isn't this Write only ? I don't see the point of "Reading" this value back. Suzuki > diff --git a/drivers/hwtracing/coresight/coresight-tpda.c b/drivers/hwtracing/coresight/coresight-tpda.c > index 7baa8a0965d3..f79fea4fbb2c 100644 > --- a/drivers/hwtracing/coresight/coresight-tpda.c > +++ b/drivers/hwtracing/coresight/coresight-tpda.c > @@ -430,9 +430,49 @@ static ssize_t syncr_mode_store(struct device *dev, > } > static DEVICE_ATTR_RW(syncr_mode); > > +static ssize_t port_flush_req_show(struct device *dev, > + struct device_attribute *attr, > + char *buf) > +{ > + struct tpda_drvdata *drvdata = dev_get_drvdata(dev->parent); > + unsigned long val; > + > + if (!drvdata->csdev->refcnt) > + return -EINVAL; > + > + guard(spinlock)(&drvdata->spinlock); > + val = readl_relaxed(drvdata->base + TPDA_FLUSH_CR); > + > + return sysfs_emit(buf, "0x%lx\n", val); > +} > + > +static ssize_t port_flush_req_store(struct device *dev, > + struct device_attribute *attr, > + const char *buf, > + size_t size) > +{ > + struct tpda_drvdata *drvdata = dev_get_drvdata(dev->parent); > + u32 val; > + > + if (kstrtou32(buf, 0, &val)) > + return -EINVAL; > + > + if (!drvdata->csdev->refcnt || !val) > + return -EINVAL; > + > + guard(spinlock)(&drvdata->spinlock); > + CS_UNLOCK(drvdata->base); > + writel_relaxed(val, drvdata->base + TPDA_FLUSH_CR); > + CS_LOCK(drvdata->base); > + > + return size; > +} > +static DEVICE_ATTR_RW(port_flush_req); > + > static struct attribute *tpda_attrs[] = { > &dev_attr_global_flush_req.attr, > &dev_attr_syncr_mode.attr, > + &dev_attr_port_flush_req.attr, > tpda_trig_sysfs_rw(freq_ts_enable, FREQTS), > tpda_trig_sysfs_rw(trig_freq_enable, FRIE), > tpda_trig_sysfs_rw(trig_flag_ts_enable, FLRIE), > diff --git a/drivers/hwtracing/coresight/coresight-tpda.h b/drivers/hwtracing/coresight/coresight-tpda.h > index 1d2de50bb9f9..ef1ce2ce36a9 100644 > --- a/drivers/hwtracing/coresight/coresight-tpda.h > +++ b/drivers/hwtracing/coresight/coresight-tpda.h > @@ -10,6 +10,7 @@ > #define TPDA_Pn_CR(n) (0x004 + (n * 4)) > #define TPDA_FPID_CR (0x084) > #define TPDA_SYNCR (0x08C) > +#define TPDA_FLUSH_CR (0x090) > > /* Cross trigger global (all ports) flush request bit */ > #define TPDA_CR_FLREQ BIT(0) >

9 months, 2 weeks

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