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2782 discussions

Re: [PATCH v4 13/13] coresight: docs: Document etm4x timestamp interval option

by James Clark

On 14/11/2025 5:02 am, Randy Dunlap wrote: > > > On 11/12/25 7:22 AM, James Clark wrote: >> Document how the new field is used, maximum value and the interaction >> with SYNC timestamps. >> >> Signed-off-by: James Clark <james.clark(a)linaro.org> >> --- >> Documentation/trace/coresight/coresight.rst | 15 +++++++++++++-- >> 1 file changed, 13 insertions(+), 2 deletions(-) >> >> diff --git a/Documentation/trace/coresight/coresight.rst b/Documentation/trace/coresight/coresight.rst >> index 806699871b80..80b5ed09d69b 100644 >> --- a/Documentation/trace/coresight/coresight.rst >> +++ b/Documentation/trace/coresight/coresight.rst >> @@ -613,8 +613,19 @@ They are also listed in the folder /sys/bus/event_source/devices/cs_etm/format/ >> - Session local version of the system wide setting: :ref:`ETM_MODE_RETURNSTACK >> <coresight-return-stack>` >> * - timestamp >> - - Session local version of the system wide setting: :ref:`ETMv4_MODE_TIMESTAMP >> - <coresight-timestamp>` >> + - Controls generation and interval of timestamps. >> + >> + 0 = off, 1 = maximum interval .. 15 = minimum interval. >> + >> + Values 1 - 14 use a counter that decrements every cycle to generate a >> + timestamp on underflow. The reload value for the counter is 2 raised to >> + the power of timestamp interval - 1. If the value is 1 then the reload >> + value is 1, if the value is 11 then the reload value is 1024 etc. > > value = 11: 2^11-1 = 2047 > > Maybe add some parens? > > Will do. I had them but I removed them because it was in a sentence so it made it look like a side note. I think I'll change from words to symbols: The reload value for the counter is 2 ^ (interval - 1). Thanks James

7 months, 2 weeks

[PATCH v5 0/3] coresight-tnoc: Add support for Interconnect TNOC

by Yuanfang Zhang

This patch series adds support for the Qualcomm CoreSight Interconnect TNOC (Trace Network On Chip) block, which acts as a CoreSight graph link forwarding trace data from subsystems to the Aggregator TNOC. Unlike the Aggregator TNOC, this block does not support aggregation or ATID assignment. Signed-off-by: Yuanfang Zhang <yuanfang.zhang(a)oss.qualcomm.com> --- Changes in v5: - Add the missing review-by tag for patch 3. - Link to v4: https://lore.kernel.org/r/20250831-itnoc-v4-0-f0fb0ef822a5@oss.qualcomm.com Changes in v4: - Fix unintended blank line removals in trace_noc_enable_hw. - Link to v3: https://lore.kernel.org/r/20250828-itnoc-v3-0-f1b55dea7a27@oss.qualcomm.com Changes in v3: - Add detail for changes in V2. - Remove '#address-cells' and '#size-cells' properties from in-ports field. - Fix comment indentation for packet description. - Link to v2: https://lore.kernel.org/r/20250819-itnoc-v2-0-2d0e6be44e2f@oss.qualcomm.com Changes in v2: - Removed the trailing '|' after the description in qcom,coresight-itnoc.yaml. - Dropped the 'select' section from the YAML file. - Updated node name to use a more generic naming convention. - Removed the 'items' property from the compatible field. - Deleted the description for the reg property. - Dropped clock-names and adjusted the order of clock-names and clocks. - Moved additionalProperties to follow the $ref of out-ports. - Change "atid" type from u32 to int, set it as "-EOPNOTSUPP" for non-AMBA device. - Link to v1: https://lore.kernel.org/r/20250815-itnoc-v1-0-62c8e4f7ad32@oss.qualcomm.com --- Yuanfang Zhang (3): dt-bindings: arm: qcom: Add Coresight Interconnect TNOC coresight-tnoc: add platform driver to support Interconnect TNOC coresight-tnoc: Add runtime PM support for Interconnect TNOC .../bindings/arm/qcom,coresight-itnoc.yaml | 90 ++++++++++++++ drivers/hwtracing/coresight/coresight-tnoc.c | 136 +++++++++++++++++++-- 2 files changed, 215 insertions(+), 11 deletions(-) --- base-commit: 2b52cf338d39d684a1c6af298e8204902c026aca change-id: 20250815-itnoc-460273d1b80c Best regards, -- Yuanfang Zhang <yuanfang.zhang(a)oss.qualcomm.com>

7 months, 2 weeks

[PATCH v6 00/11] CoreSight: Refactor power management for ETMv3/4

by Leo Yan

This series is extracted from the CoreSight power management fixes and refactoring [1], focusing on ETMv3/4 power management. This series has been verified on Juno-r2 platform. [1] https://lore.kernel.org/linux-arm-kernel/20250915-arm_coresight_power_manag… --- Changes in v6: - Added a 'retain_ss_status' flag to indicate if need to restain single-shot status (Suzuki). - Introduced __etm4_disable_hw() without calling etm4_cs_{unlock|lock}() pairs, which is convenient for the save callback (Suzuki). - Link to v5: https://lore.kernel.org/r/20251103-arm_coresight_power_management_fix-v5-0-… Changes in v5: - Added more info for removing redundant DSB in etm4_{enable|disable}_trace_unit() (Suzuki/Levi). - Dropped moving isb() out from etm4_{enable|disable}_trace_unit() (Suzuki). - Reordered patches to move fixes earlier. - Link to v4: https://lore.kernel.org/r/20251024-arm_coresight_power_management_fix-v4-0-… Changes in v4: - Added patch 10 for retaining sequencer state in ETMv4 driver (Mike). - Added Mike's review tags. - Added James' test tags. - Link to v3: https://lore.kernel.org/r/20250915-arm_coresight_power_management_fix-v3-0-… Changes in v3: - Fixed building failure in ETMv3 driver (kernel test robot). - Refactoring ETMv3 change for checking CPU ID (Levi). - Fixed NULL pointer issue during CPU idle (James). - Fixed lockdep complaint for HARDIRQ-safe and HARDIRA-unsafe (James). - Fixed acquiring mutex in atomic context (James). - Rebased on the latest coresight-next branch. - Link to v2: https://lore.kernel.org/r/20250701-arm_cs_pm_fix_v3-v2-0-23ebb864fcc1@arm.c… Changes in v2: - Refactored ETMv4 suspend and resume for reusing the normal enabling and disabling flows (James). - Used a per-CPU structure to maintain path pointers (James). - Supported helpers in CPU PM flows (James). - Fixed the SMP-safe access to device mode. - Fixed the context synchronization in ETMv4x driver. - Link to v1: https://lore.kernel.org/linux-arm-kernel/20250516160742.1200904-1-leo.yan@a… Signed-off-by: Leo Yan <leo.yan(a)arm.com> --- Leo Yan (11): coresight: Change device mode to atomic type coresight: etm4x: Always set tracer's device mode on target CPU coresight: etm3x: Always set tracer's device mode on target CPU coresight: etm4x: Correct polling IDLE bit coresight: etm4x: Add context synchronization before enabling trace coresight: etm4x: Properly control filter in CPU idle with FEAT_TRF coresight: etm4x: Remove the redundant DSB coresight: etm4x: Remove the state_needs_restore flag coresight: etm4x: Add flag to retain single-shot status coresight: etm4x: Retain sequencer state coresight: etm4x: Reuse normal enable and disable logic in CPU idle drivers/hwtracing/coresight/coresight-etm3x-core.c | 59 ++-- drivers/hwtracing/coresight/coresight-etm4x-core.c | 358 +++++++-------------- drivers/hwtracing/coresight/coresight-etm4x.h | 64 +--- include/linux/coresight.h | 25 +- 4 files changed, 172 insertions(+), 334 deletions(-) --- base-commit: b139702a889692ec30702534ebb1ae2b11ed1cbf change-id: 20250909-arm_coresight_power_management_fix-139873f942e8 Best regards, -- Leo Yan <leo.yan(a)arm.com>

7 months, 2 weeks

Re: [PATCH v2] coresight: etm-perf: Fix reference count leak in etm_setup_aux

by Leo Yan

On 11/12/25 01:24, Ma Ke wrote: > @@ -454,6 +454,11 @@ static void *etm_setup_aux(struct perf_event *event, void **pages, > goto err; > > out: > + if (user_sink) { > + put_device(&user_sink->dev); > + user_sink = NULL; > + } After searched kernel, I prefer to put device in coresight_get_sink_by_id(). Please refer acpi_dev_present() how to do that. I would like Suzuki's confirmation in case I introduce noise. Thanks, Leo

7 months, 2 weeks

[PATCH v7 00/11] CoreSight: Refactor power management for ETMv3/4

by Leo Yan

This series is extracted from the CoreSight power management fixes and refactoring [1], focusing on ETMv3/4 power management. This series has been verified on Juno-r2 platform. [1] https://lore.kernel.org/linux-arm-kernel/20250915-arm_coresight_power_manag… --- Changes in v7: - Updated the commit log in patch 11 (Mike). - Link to v6: https://lore.kernel.org/r/20251111-arm_coresight_power_management_fix-v6-0-… Changes in v6: - Added a 'retain_ss_status' flag to indicate if need to restain single-shot status (Suzuki). - Introduced __etm4_disable_hw() without calling etm4_cs_{unlock|lock}() pairs, which is convenient for the save callback (Suzuki). - Link to v5: https://lore.kernel.org/r/20251103-arm_coresight_power_management_fix-v5-0-… Changes in v5: - Added more info for removing redundant DSB in etm4_{enable|disable}_trace_unit() (Suzuki/Levi). - Dropped moving isb() out from etm4_{enable|disable}_trace_unit() (Suzuki). - Reordered patches to move fixes earlier. - Link to v4: https://lore.kernel.org/r/20251024-arm_coresight_power_management_fix-v4-0-… Changes in v4: - Added patch 10 for retaining sequencer state in ETMv4 driver (Mike). - Added Mike's review tags. - Added James' test tags. - Link to v3: https://lore.kernel.org/r/20250915-arm_coresight_power_management_fix-v3-0-… Changes in v3: - Fixed building failure in ETMv3 driver (kernel test robot). - Refactoring ETMv3 change for checking CPU ID (Levi). - Fixed NULL pointer issue during CPU idle (James). - Fixed lockdep complaint for HARDIRQ-safe and HARDIRA-unsafe (James). - Fixed acquiring mutex in atomic context (James). - Rebased on the latest coresight-next branch. - Link to v2: https://lore.kernel.org/r/20250701-arm_cs_pm_fix_v3-v2-0-23ebb864fcc1@arm.c… Changes in v2: - Refactored ETMv4 suspend and resume for reusing the normal enabling and disabling flows (James). - Used a per-CPU structure to maintain path pointers (James). - Supported helpers in CPU PM flows (James). - Fixed the SMP-safe access to device mode. - Fixed the context synchronization in ETMv4x driver. - Link to v1: https://lore.kernel.org/linux-arm-kernel/20250516160742.1200904-1-leo.yan@a… Signed-off-by: Leo Yan <leo.yan(a)arm.com> --- Leo Yan (11): coresight: Change device mode to atomic type coresight: etm4x: Always set tracer's device mode on target CPU coresight: etm3x: Always set tracer's device mode on target CPU coresight: etm4x: Correct polling IDLE bit coresight: etm4x: Add context synchronization before enabling trace coresight: etm4x: Properly control filter in CPU idle with FEAT_TRF coresight: etm4x: Remove the redundant DSB coresight: etm4x: Remove the state_needs_restore flag coresight: etm4x: Add flag to retain single-shot status coresight: etm4x: Retain sequencer state coresight: etm4x: Reuse normal enable and disable logic in CPU idle drivers/hwtracing/coresight/coresight-etm3x-core.c | 59 ++-- drivers/hwtracing/coresight/coresight-etm4x-core.c | 358 +++++++-------------- drivers/hwtracing/coresight/coresight-etm4x.h | 64 +--- include/linux/coresight.h | 25 +- 4 files changed, 172 insertions(+), 334 deletions(-) --- base-commit: b139702a889692ec30702534ebb1ae2b11ed1cbf change-id: 20250909-arm_coresight_power_management_fix-139873f942e8 Best regards, -- Leo Yan <leo.yan(a)arm.com>

7 months, 2 weeks

Re: [PATCH] coresight: etm-perf: Fix reference count leak in etm_setup_aux

by Suzuki K Poulose

Hi On 11/11/2025 14:42, Ma Ke wrote: > In etm_setup_aux(), when a user sink is obtained via > coresight_get_sink_by_id(), it increments the reference count of the > sink device. However, if the sink is used in path building, the path > holds a reference, but the initial reference from > coresight_get_sink_by_id() is not released, causing a reference count > leak. We should release the initial reference after the path is built. > > Found by code review. > > Cc: stable(a)vger.kernel.org > Fixes: 0e6c20517596 ("coresight: etm-perf: Allow an event to use different sinks") > Signed-off-by: Ma Ke <make24(a)iscas.ac.cn> > --- > drivers/hwtracing/coresight/coresight-etm-perf.c | 5 +++++ > 1 file changed, 5 insertions(+) > > diff --git a/drivers/hwtracing/coresight/coresight-etm-perf.c b/drivers/hwtracing/coresight/coresight-etm-perf.c > index f677c08233ba..6584f6aa87bf 100644 > --- a/drivers/hwtracing/coresight/coresight-etm-perf.c > +++ b/drivers/hwtracing/coresight/coresight-etm-perf.c > @@ -453,6 +453,11 @@ static void *etm_setup_aux(struct perf_event *event, void **pages, > if (!event_data->snk_config) > goto err; > > + if (user_sink) { > + put_device(&user_sink->dev); > + user_sink = NULL; > + } > + I would recommend moving this to the out: label below, to make sure we drop the refcount even in the error path. Otherwise looks good to me. Suzuki > out: > return event_data; >

7 months, 2 weeks

[PATCH v4 0/6] Refactoring finding CPU phandles in DT

by Alireza Sanaee

This series refactor the way CPU IDs are retrieved from the device tree. Usually, there is a for loop that goes over every single CPU that can be avoided. This also reduces the amount of NULL pointer checks in drivers. I have abstracted away that loop and introduced a new function (of_cpu_node_to_id) for this. This patchset is a subset of [1], where I removed content and patches relevant to hyper-threaded cores for DT. Based on the discussion, the code refactor is still useful, hence this patchset. [1] https://lore.kernel.org/all/20250512080715.82-1-alireza.sanaee@huawei.co Changes since v3: - Rebased to d69eb204c255c35abd9e8cb621484e8074c75eaa Changes since v2: - Addressed Jonathan Cameron's comments. - Added reviewed-by tags. - Added a new commit where I suggest simplfing the code in arch_topology.c to remove the use of cpu_node on failure path. - Improve documentation. - Caught a bug in patch 1. - Commit message fixed for patch 2. Changes since v1: - Rebased on top of the latest mainline. - Addressed Krzysztof Kozlowski's comments -- Hopefully :-) - Addressed Jonathan Cameron's comments. Alireza Sanaee (6): of: add infra for finding CPU id from phandle arch_topology: drop the use of cpu_node in the pr_info arch_topology: update CPU map to use of_cpu_phandle_to_id coresight: cti: Use of_cpu_phandle_to_id for grabbing CPU id coresight: Use of_cpu_phandle_to_id for grabbing CPU ID perf/arm-dsu: refactor cpu id retrieval via new API of_cpu_phandle_to_id drivers/base/arch_topology.c | 22 ++++----- .../coresight/coresight-cti-platform.c | 13 +---- .../hwtracing/coresight/coresight-platform.c | 15 +----- drivers/of/cpu.c | 48 +++++++++++++++++++ drivers/perf/arm_dsu_pmu.c | 7 +-- include/linux/of.h | 9 ++++ 6 files changed, 71 insertions(+), 43 deletions(-) -- 2.43.0

7 months, 2 weeks

[PATCH v5 00/11] CoreSight: Refactor power management for ETMv3/4

by Leo Yan

This series is extracted from the CoreSight power management fixes and refactoring [1], focusing on ETMv3/4 power management. This series has been verified on Juno-r2 platform. [1] https://lore.kernel.org/linux-arm-kernel/20250915-arm_coresight_power_manag… --- Changes in v5: - Added more info for removing redundant DSB in etm4_{enable|disable}_trace_unit() (Suzuki/Levi). - Dropped moving isb() out from etm4_{enable|disable}_trace_unit() (Suzuki). - Reordered patches to move fixes earlier. - Link to v4: https://lore.kernel.org/r/20251024-arm_coresight_power_management_fix-v4-0-… Changes in v4: - Added patch 10 for retaining sequencer state in ETMv4 driver (Mike). - Added Mike's review tags. - Added James' test tags. - Link to v3: https://lore.kernel.org/r/20250915-arm_coresight_power_management_fix-v3-0-… Changes in v3: - Fixed building failure in ETMv3 driver (kernel test robot). - Refactoring ETMv3 change for checking CPU ID (Levi). - Fixed NULL pointer issue during CPU idle (James). - Fixed lockdep complaint for HARDIRQ-safe and HARDIRA-unsafe (James). - Fixed acquiring mutex in atomic context (James). - Rebased on the latest coresight-next branch. - Link to v2: https://lore.kernel.org/r/20250701-arm_cs_pm_fix_v3-v2-0-23ebb864fcc1@arm.c… Changes in v2: - Refactored ETMv4 suspend and resume for reusing the normal enabling and disabling flows (James). - Used a per-CPU structure to maintain path pointers (James). - Supported helpers in CPU PM flows (James). - Fixed the SMP-safe access to device mode. - Fixed the context synchronization in ETMv4x driver. - Link to v1: https://lore.kernel.org/linux-arm-kernel/20250516160742.1200904-1-leo.yan@a… Signed-off-by: Leo Yan <leo.yan(a)arm.com> --- Leo Yan (11): coresight: Change device mode to atomic type coresight: etm4x: Always set tracer's device mode on target CPU coresight: etm3x: Always set tracer's device mode on target CPU coresight: etm4x: Correct polling IDLE bit coresight: etm4x: Add context synchronization before enabling trace coresight: etm4x: Properly control filter in CPU idle with FEAT_TRF coresight: etm4x: Remove the redundant DSB coresight: etm4x: Remove the state_needs_restore flag coresight: etm4x: Add flag to control single-shot restart coresight: etm4x: Retain sequencer state coresight: etm4x: Reuse normal enable and disable logic in CPU idle drivers/hwtracing/coresight/coresight-etm3x-core.c | 59 ++-- drivers/hwtracing/coresight/coresight-etm4x-core.c | 347 +++++++-------------- drivers/hwtracing/coresight/coresight-etm4x.h | 62 ---- include/linux/coresight.h | 25 +- 4 files changed, 157 insertions(+), 336 deletions(-) --- base-commit: 6146a0f1dfae5d37442a9ddcba012add260bceb0 change-id: 20250909-arm_coresight_power_management_fix-139873f942e8 Best regards, -- Leo Yan <leo.yan(a)arm.com>

7 months, 2 weeks

Re: [PATCH v2 0/3] coresight: replace the void pointer with coresight_path pointer

by Suzuki K Poulose

On Thu, 25 Sep 2025 18:42:30 +0800, Jie Gan wrote: > Patch 1: > Fix the issue that the catu cannot correctly read the handle of the AUX > event which is caused by the commit[1]. > > [1] 080ee83cc361 ("Coresight: Change functions to accept the coresight_path") > > Exeception call trace: > tmc_etr_get_buffer+0x30/0x80 [coresight_tmc] (P) > catu_enable_hw+0xbc/0x3d0 [coresight_catu] > catu_enable+0x70/0xe0 [coresight_catu] > coresight_enable_path+0xb0/0x258 [coresight] > > [...] Applied, thanks! [1/3] coresight: tmc: add the handle of the event to the path https://git.kernel.org/coresight/c/aaa5abcc9d44 [2/3] coresight: change helper_ops to accept coresight_path https://git.kernel.org/coresight/c/94baedb51dea [3/3] coresight: change the sink_ops to accept coresight_path https://git.kernel.org/coresight/c/b139702a8896 Best regards, -- Suzuki K Poulose <suzuki.poulose(a)arm.com>

7 months, 3 weeks

Re: [PATCH v3] coresight: ETR: Fix ETR buffer use-after-free issue

by Suzuki K Poulose

On Tue, 21 Oct 2025 16:45:25 +0800, Xiaoqi Zhuang wrote: > When ETR is enabled as CS_MODE_SYSFS, if the buffer size is changed > and enabled again, currently sysfs_buf will point to the newly > allocated memory(buf_new) and free the old memory(buf_old). But the > etr_buf that is being used by the ETR remains pointed to buf_old, not > updated to buf_new. In this case, it will result in a memory > use-after-free issue. > > [...] Applied, thanks! [1/1] coresight: ETR: Fix ETR buffer use-after-free issue https://git.kernel.org/coresight/c/35501ac3c7d4 Best regards, -- Suzuki K Poulose <suzuki.poulose(a)arm.com>

7 months, 3 weeks

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