CoreSight

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2762 discussions

[PATCHv2 0/4] Add support for replicators which loses context on clock removal

by Sai Prakash Ranjan

This series is mainly to add support for replicators which lose context on removing AMBA clock like on SC7180 SoC where replicator in AOSS domain loses context. Patch 1 and 2 are minor cleanups to use macros. Patch 3 and 4 adds support for replicators which loses context on removing AMBA clock. Previous version is here - https://lore.kernel.org/patchwork/patch/1239923/ More discussion is found here - https://lore.kernel.org/patchwork/patch/1231182/ There were no patch 1 and patch 2 in v1. Sai Prakash Ranjan (4): coresight: replicator: Use CS_AMBA_ID macro for id table coresight: catu: Use CS_AMBA_ID macro for id table coresight: replicator: Reset replicator if context is lost dt-bindings: arm: coresight: Add optional property to replicators .../devicetree/bindings/arm/coresight.txt | 6 ++ drivers/hwtracing/coresight/coresight-catu.c | 5 +- .../coresight/coresight-replicator.c | 66 +++++++++++-------- 3 files changed, 46 insertions(+), 31 deletions(-) -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation

6 years

libopencsd in debian: new git repos and 0.14.1-1 now in 'testing'

by Wookey

I updated debian to 0.14.1. I am also trying out a dgit-based workflow for the package, so the package uploaded to the archive is also available as https://browse.dgit.debian.org/libopencsd.git/ You can pull down the latest version with: From the archive, as tarball+diff: apt From the archive, as git repo: dgit From a URL, as tarball+diff: dget None of this should make much difference to any of you, but this does make it much easier for people used to a git workflow to contribute to the debian package if need be. It should also mean that the debian package matches the git history of upstream much more closely. In case anyone cares I have chosen the dgit 'merge' workflow about of about 11 possible schemes (https://wiki.debian.org/GitPackagingSurvey) (debian never has just one way of doing anything :-) For those not familiar: dgit is a tool to provide bi-direcitonal translation between the debian archive format (.dsc, tarball and debian diff) and git repositories. Package maintainers can continue to use either system and the git/tarball views of the world are synchonised at upload. I've also added a development view of the package on debian's gitlab instance: https://salsa.debian.org/wookey/libopencsd I would prefer patches as patches in bug reports, but I have left the 'merge request' thingy turned on so I guess people can use that too (but I don't know how to drive it yet :-). I reserve the right to give up with all this complicated fancy stuff and go back to uploading debianised tarballs, which is quick, simple and I understand it properly :-) but this stuff should make things a little more accessible. I'd be interested to hear if anyone actually finds it useful (nearly everyone on this list will be working with upstream primarily so rarely/never fiddle with the debian packages, I presume). ----- Forwarded message from Debian testing watch <noreply(a)release.debian.org> ----- Date: Tue, 19 May 2020 04:39:06 +0000 From: Debian testing watch <noreply(a)release.debian.org> To: libopencsd(a)packages.debian.org Subject: libopencsd 0.14.1-1 MIGRATED to testing FYI: The status of the libopencsd source package in Debian's testing distribution has changed. Previous version: 0.14.0-1 Current version: 0.14.1-1 -- This email is automatically generated once a day. As the installation of new packages into testing happens multiple times a day you will receive later changes on the next day. See https://release.debian.org/testing-watch/ for more information. ----- End forwarded message ----- Wookey -- Principal hats: Linaro, Debian, Wookware, ARM http://wookware.org/

6 years

Re: Coresight enablement on NXP ARMv8 device

by Mathieu Poirier

Hi Poonam, Please CC the coresight mailing list (as I did) when asking questions - there is a lot of well informed people on there that can also help you. On Thu, 23 Jan 2020 at 22:33, Poonam Aggrwal <poonam.aggrwal(a)nxp.com> wrote: > > Hello Mathieu > > > > Greetings! > > > > I have started to take a look at the Linux coresight framework, and get this enabled on a NXP ARMv8 device. > > > > Can you share some documentation on the configs required to be enabled and the device tree nodes? For V8 we have to reference implementation - ARM Juno and the dragonboard 410c. I highly recommend purchasing the latter (because it is very cheap) in order to get an understanding of what a working coresight system look like. It is much easier to start from a working example than nothing at all. Other than that the coresight bindings [1] are full of good examples. I would also have a look at the DT for Juno [2] and the dragonboard[3]. The HOWTO.md [4] on github is a really good starting point when you'll get to test things out. [1]. https://elixir.bootlin.com/linux/latest/source/Documentation/devicetree/bin… [2]. https://elixir.bootlin.com/linux/latest/source/arch/arm64/boot/dts/arm/juno… [3]. https://elixir.bootlin.com/linux/latest/source/arch/arm64/boot/dts/qcom/msm… [4]. https://github.com/Linaro/OpenCSD/blob/master/HOWTO.md > > To start I am looking to enable the ARMv8 ETM tracing. Before going further I advise you to look at the source and sink configuration on your platform. Up to now we've been working with configurations where sources share a single sink (N:1 topology). Newer SoC will have one source per sink (1:1 topology). At this time only the former is supported by the framework. Supporting 1:1 topologies would require a fair amount of refactoring, something we haven't had the opportunity to do for lack of HW platform to work with. Regards, Mathieu > > Is there a reference which I can check in Linux for device tree and config. > > > > Many Thanks > > Poonam

6 years

Postdated Check cleared receipt for 2020/15/May

by Sales

Please confirm payment made May 14 2020.

6 years

COVID-19: Face Masks & Hand Sanitizer

by Leanne Szymczak

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6 years

[PATCH] coresight: etm4x: Add support to disable trace unit power up

by Sai Prakash Ranjan

From: Tingwei Zhang <tingwei(a)codeaurora.org> On some Qualcomm Technologies Inc. SoCs like SC7180, there exists a hardware errata where the APSS (Application Processor SubSystem)/CPU watchdog counter is stopped when ETM register TRCPDCR.PU=1. Since the ETMs share the same power domain as that of respective CPU cores, they are powered on when the CPU core is powered on. So we can disable powering up of the trace unit after checking for this errata via new property called "qcom,tupwr-disable". Signed-off-by: Tingwei Zhang <tingwei(a)codeaurora.org> Co-developed-by: Sai Prakash Ranjan <saiprakash.ranjan(a)codeaurora.org> Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan(a)codeaurora.org> --- .../devicetree/bindings/arm/coresight.txt | 6 ++++ drivers/hwtracing/coresight/coresight-etm4x.c | 29 ++++++++++++------- 2 files changed, 25 insertions(+), 10 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/coresight.txt b/Documentation/devicetree/bindings/arm/coresight.txt index 846f6daae71b..d2030128fe46 100644 --- a/Documentation/devicetree/bindings/arm/coresight.txt +++ b/Documentation/devicetree/bindings/arm/coresight.txt @@ -108,6 +108,12 @@ its hardware characteristcs. * arm,cp14: must be present if the system accesses ETM/PTM management registers via co-processor 14. + * qcom,tupwr-disable: boolean. Indicates that trace unit power up can + be disabled on Qualcomm Technologies Inc. systems where ETMs are in + the same power domain as their CPU cores. This property is required + to identify such systems with hardware errata where the CPU watchdog + counter is stopped when TRCPDCR.PU=1. + * Optional property for TMC: * arm,buffer-size: size of contiguous buffer space for TMC ETR diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c index fb0f5f4f3a91..6886b44f6947 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.c +++ b/drivers/hwtracing/coresight/coresight-etm4x.c @@ -104,6 +104,11 @@ struct etm4_enable_arg { int rc; }; +static inline bool etm4_can_disable_tupwr(struct device *dev) +{ + return fwnode_property_present(dev_fwnode(dev), "qcom,tupwr-disable"); +} + static int etm4_enable_hw(struct etmv4_drvdata *drvdata) { int i, rc; @@ -196,12 +201,14 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata) writel_relaxed(config->vmid_mask0, drvdata->base + TRCVMIDCCTLR0); writel_relaxed(config->vmid_mask1, drvdata->base + TRCVMIDCCTLR1); - /* - * Request to keep the trace unit powered and also - * emulation of powerdown - */ - writel_relaxed(readl_relaxed(drvdata->base + TRCPDCR) | TRCPDCR_PU, - drvdata->base + TRCPDCR); + if (!etm4_can_disable_tupwr(etm_dev)) { + /* + * Request to keep the trace unit powered and also + * emulation of powerdown + */ + writel_relaxed(readl_relaxed(drvdata->base + TRCPDCR) | TRCPDCR_PU, + drvdata->base + TRCPDCR); + } /* Enable the trace unit */ writel_relaxed(1, drvdata->base + TRCPRGCTLR); @@ -476,10 +483,12 @@ static void etm4_disable_hw(void *info) CS_UNLOCK(drvdata->base); - /* power can be removed from the trace unit now */ - control = readl_relaxed(drvdata->base + TRCPDCR); - control &= ~TRCPDCR_PU; - writel_relaxed(control, drvdata->base + TRCPDCR); + if (!etm4_can_disable_tupwr(etm_dev)) { + /* power can be removed from the trace unit now */ + control = readl_relaxed(drvdata->base + TRCPDCR); + control &= ~TRCPDCR_PU; + writel_relaxed(control, drvdata->base + TRCPDCR); + } control = readl_relaxed(drvdata->base + TRCPRGCTLR); -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation

6 years

[PATCH] dt-bindings: hisilicon: Add CTI bindings for hi-6220

by Mike Leach

Adds in CTI device tree information for the Hikey620 board. Tested on Linux 5.7-rc1. Signed-off-by: Mike Leach <mike.leach(a)linaro.org> Reviewed-by: Mathieu Poirier <mathieu.poirier(a)linaro.org> Tested-by: Leo Yan <leo.yan(a)linaro.org> --- .../boot/dts/hisilicon/hi6220-coresight.dtsi | 130 ++++++++++++++++-- 1 file changed, 122 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/hisilicon/hi6220-coresight.dtsi b/arch/arm64/boot/dts/hisilicon/hi6220-coresight.dtsi index 651771a73ed6..27f067e87601 100644 --- a/arch/arm64/boot/dts/hisilicon/hi6220-coresight.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi6220-coresight.dtsi @@ -213,7 +213,7 @@ }; }; - etm@f659c000 { + etm0: etm@f659c000 { compatible = "arm,coresight-etm4x", "arm,primecell"; reg = <0 0xf659c000 0 0x1000>; @@ -232,7 +232,7 @@ }; }; - etm@f659d000 { + etm1: etm@f659d000 { compatible = "arm,coresight-etm4x", "arm,primecell"; reg = <0 0xf659d000 0 0x1000>; @@ -251,7 +251,7 @@ }; }; - etm@f659e000 { + etm2: etm@f659e000 { compatible = "arm,coresight-etm4x", "arm,primecell"; reg = <0 0xf659e000 0 0x1000>; @@ -270,7 +270,7 @@ }; }; - etm@f659f000 { + etm3: etm@f659f000 { compatible = "arm,coresight-etm4x", "arm,primecell"; reg = <0 0xf659f000 0 0x1000>; @@ -289,7 +289,7 @@ }; }; - etm@f65dc000 { + etm4: etm@f65dc000 { compatible = "arm,coresight-etm4x", "arm,primecell"; reg = <0 0xf65dc000 0 0x1000>; @@ -308,7 +308,7 @@ }; }; - etm@f65dd000 { + etm5: etm@f65dd000 { compatible = "arm,coresight-etm4x", "arm,primecell"; reg = <0 0xf65dd000 0 0x1000>; @@ -327,7 +327,7 @@ }; }; - etm@f65de000 { + etm6: etm@f65de000 { compatible = "arm,coresight-etm4x", "arm,primecell"; reg = <0 0xf65de000 0 0x1000>; @@ -346,7 +346,7 @@ }; }; - etm@f65df000 { + etm7: etm@f65df000 { compatible = "arm,coresight-etm4x", "arm,primecell"; reg = <0 0xf65df000 0 0x1000>; @@ -364,5 +364,119 @@ }; }; }; + + /* System CTIs */ + /* CTI 0 - TMC and TPIU connections */ + cti@f6403000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0 0xf6403000 0 0x1000>; + + clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>; + clock-names = "apb_pclk"; + }; + + /* CTI - CPU-0 */ + cti@f6598000 { + compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti", + "arm,primecell"; + reg = <0 0xf6598000 0 0x1000>; + + clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>; + clock-names = "apb_pclk"; + + cpu = <&cpu0>; + arm,cs-dev-assoc = <&etm0>; + }; + + /* CTI - CPU-1 */ + cti@f6599000 { + compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti", + "arm,primecell"; + reg = <0 0xf6599000 0 0x1000>; + + clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>; + clock-names = "apb_pclk"; + + cpu = <&cpu1>; + arm,cs-dev-assoc = <&etm1>; + }; + + /* CTI - CPU-2 */ + cti@f659a000 { + compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti", + "arm,primecell"; + reg = <0 0xf659a000 0 0x1000>; + + clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>; + clock-names = "apb_pclk"; + + cpu = <&cpu2>; + arm,cs-dev-assoc = <&etm2>; + }; + + /* CTI - CPU-3 */ + cti@f659b000 { + compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti", + "arm,primecell"; + reg = <0 0xf659b000 0 0x1000>; + + clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>; + clock-names = "apb_pclk"; + + cpu = <&cpu3>; + arm,cs-dev-assoc = <&etm3>; + }; + + /* CTI - CPU-4 */ + cti@f65d8000 { + compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti", + "arm,primecell"; + reg = <0 0xf65d8000 0 0x1000>; + + clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>; + clock-names = "apb_pclk"; + + cpu = <&cpu4>; + arm,cs-dev-assoc = <&etm4>; + }; + + /* CTI - CPU-5 */ + cti@f65d9000 { + compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti", + "arm,primecell"; + reg = <0 0xf65d9000 0 0x1000>; + + clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>; + clock-names = "apb_pclk"; + + cpu = <&cpu5>; + arm,cs-dev-assoc = <&etm5>; + }; + + /* CTI - CPU-6 */ + cti@f65da000 { + compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti", + "arm,primecell"; + reg = <0 0xf65da000 0 0x1000>; + + clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>; + clock-names = "apb_pclk"; + + cpu = <&cpu6>; + arm,cs-dev-assoc = <&etm6>; + }; + + /* CTI - CPU-7 */ + cti@f65db000 { + compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti", + "arm,primecell"; + reg = <0 0xf65db000 0 0x1000>; + + clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>; + clock-names = "apb_pclk"; + + cpu = <&cpu7>; + arm,cs-dev-assoc = <&etm7>; + }; }; }; -- 2.17.1

6 years

[PATCHv2 0/2] coresight: etm4x: Add support to skip trace unit power up

by Sai Prakash Ranjan

This series adds support to skip powering up of trace unit on systems with an errata which stops CPU watchdog counter when power up bit is set (TRCPDCR.PU = 1). Setting this bit is not required on Qualcomm Technologies Inc. chipsets where this errata exists since the ETMs are in the same power domain as their respective CPU cores. Tingwei Zhang (2): coresight: etm4x: Add support to skip trace unit power up dt-bindings: arm: coresight: Add support to skip trace unit power up .../devicetree/bindings/arm/coresight.txt | 7 +++++ drivers/hwtracing/coresight/coresight-etm4x.c | 27 ++++++++++++------- drivers/hwtracing/coresight/coresight-etm4x.h | 3 +++ 3 files changed, 27 insertions(+), 10 deletions(-) -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation

6 years

[PATCH v3 0/2] Add CPU power management for CPU bound CTI devices.

by Mike Leach

Adds in power management for CPU bound CTI devices: i) CPU Hotplug - registers a new notifier for CPU start and stop events. ii) CPU idle PM event notifier to handle PM_ENTER, PM_ENTER_FAILED and PM_EXIT events. Tested with DB410c on coresight/next tree (Linux 5.7-rc1) Changes since v2: 1) removed helper functions filtering on CONFIG_CPU_PM to call cpu_pm fns directly. 2) add check for return value from cpuhp_remove_state_nocalls(). Changes since V1: (requested by Mathieu). 1) Split into separate patches for CPU pm and CPU hotplug handling. 2) Enable on hotplug has a specific function to enable the hardware, while leaving the enable reference counts unchanged. Mike Leach (2): coresight: cti: Add CPU Hotplug handling to CTI driver. coresight: cti: Add CPU idle pm notifer to CTI devices. drivers/hwtracing/coresight/coresight-cti.c | 160 ++++++++++++++++++++ include/linux/cpuhotplug.h | 1 + 2 files changed, 161 insertions(+) -- 2.17.1

6 years

RE: Order Confirmation #PO710526***

by Sales Accountant, LLC

6 years

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