CoreSight

coresight@lists.linaro.org
  • 5 participants
  • 2463 discussions

[PATCH 1/1] coresight: etm4x: Configure EL2 exception level when kernel is running in HYP
by Tomasz Nowicki
7 years

[PATCH v2] perf: Support for Arm A32/T32 instruction sets in CoreSight trace
by Robert Walker
7 years

Enabling Coresight in atomic context.
by Mike Bazov
7 years

Coresight with Perf need ETR ?
by Christophe ROULLIER
7 years

Failed for ETM decoding with db410c snapshot mode
by leo.yan@linaro.org
7 years

Decoding STM traces with OpenCSD test programs
by Mathieu Poirier
7 years

[PATCH] perf: Support for Arm A32/T32 instruction sets in CoreSight trace
by Robert Walker
7 years

хпфн
by всэ
7 years

[PATCH v3 00/13] coresight: perf: Support for TMC ETR backend
by Suzuki K Poulose
7 years, 1 month

New Version of OpenCSD Library 0.9.1
by Mike Leach
7 years, 1 month
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