CoreSight

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4 participants
2721 discussions

[PATCH v2] coresight: core: Fix typo in coresight-core.c

by Qi Liu

Fix the following checkpatch warning: WARNING: 'compoment' may be misspelled - perhaps 'component'? Fixes: 8e264c52e1da ("coresight: core: Allow the coresight core driver to be built as a module") Signed-off-by: Qi Liu <liuqi115(a)huawei.com> --- drivers/hwtracing/coresight/coresight-core.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/hwtracing/coresight/coresight-core.c b/drivers/hwtracing/coresight/coresight-core.c index 0062c89..b57bea1 100644 --- a/drivers/hwtracing/coresight/coresight-core.c +++ b/drivers/hwtracing/coresight/coresight-core.c @@ -86,7 +86,7 @@ static int coresight_id_match(struct device *dev, void *data) i_csdev->type != CORESIGHT_DEV_TYPE_SOURCE) return 0; - /* Get the source ID for both compoment */ + /* Get the source ID for both components */ trace_id = source_ops(csdev)->trace_id(csdev); i_trace_id = source_ops(i_csdev)->trace_id(i_csdev); -- 2.8.1

5 years, 7 months

Missing cs-trace-disasm.py

by Szymanski, Pawel

Hello, I am trying to run trace capturing from Coresight on N1 SDP using perf as described here: https://github.com/Linaro/OpenCSD/blob/master/HOWTO.md I was able to gather the traces, but when I wanted to get the python script to get more human readable output as described in section https://github.com/Linaro/OpenCSD/blob/master/HOWTO.md#trace-decoding-with-…, I found that the cs-trace-disasm.py Is missing in my system. Do you know where I can find the file? Regards Pawel Intel Technology Poland sp. z o.o. ul. Sowackiego 173 | 80-298 Gdask | Sd Rejonowy Gdask Pnoc | VII Wydzia Gospodarczy Krajowego Rejestru Sdowego - KRS 101882 | NIP 957-07-52-316 | Kapita zakadowy 200.000 PLN. Ta wiadomo wraz z zacznikami jest przeznaczona dla okrelonego adresata i moe zawiera informacje poufne. W razie przypadkowego otrzymania tej wiadomoci, prosimy o powiadomienie nadawcy oraz trwae jej usunicie; jakiekolwiek przegldanie lub rozpowszechnianie jest zabronione. This e-mail and any attachments may contain confidential material for the sole use of the intended recipient(s). If you are not the intended recipient, please contact the sender and delete all copies; any review or distribution by others is strictly prohibited.

5 years, 7 months

[PATCH] arm64: dts: msm8916: Enable CoreSight STM component

by Leo Yan

From: Georgi Djakov <georgi.djakov(a)linaro.org> Add DT binding for CoreSight System Trace Macrocell (STM) on msm8916, which can benefit the CoreSight development on DB410c. Signed-off-by: Georgi Djakov <georgi.djakov(a)linaro.org> Signed-off-by: Leo Yan <leo.yan(a)linaro.org> --- arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi | 1 + arch/arm64/boot/dts/qcom/msm8916.dtsi | 27 +++++++++++++++++++++++ 2 files changed, 28 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi b/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi index 3a9538e1ec97..dd87e5d739ab 100644 --- a/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi +++ b/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi @@ -406,6 +406,7 @@ &wcd_codec { &etm1 { status = "okay"; }; &etm2 { status = "okay"; }; &etm3 { status = "okay"; }; +&stm { status = "okay"; }; &etr { status = "okay"; }; &funnel0 { status = "okay"; }; &funnel1 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index 402e891a84ab..892f1772e53c 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -562,6 +562,13 @@ funnel0_in4: endpoint { remote-endpoint = <&funnel1_out>; }; }; + + port@7 { + reg = <7>; + funnel0_in7: endpoint { + remote-endpoint = <&stm_out>; + }; + }; }; out-ports { @@ -882,6 +889,26 @@ etm3_out: endpoint { }; }; + stm: stm@802000 { + compatible = "arm,coresight-stm", "arm,primecell"; + reg = <0x802000 0x1000>, + <0x9280000 0x180000>; + reg-names = "stm-base", "stm-stimulus-base"; + + clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; + + status = "disabled"; + + out-ports { + port { + stm_out: endpoint { + remote-endpoint = <&funnel0_in7>; + }; + }; + }; + }; + msmgpio: pinctrl@1000000 { compatible = "qcom,msm8916-pinctrl"; reg = <0x01000000 0x300000>; -- 2.25.1

5 years, 7 months

[PATCH -next] coresight: etm-perf: Mark format_attr_contextid with static keyword

by Zou Wei

Fix the following sparse warning: drivers/hwtracing/coresight/coresight-etm-perf.c:61:25: warning: symbol 'format_attr_contextid' was not declared. Should it be static? Signed-off-by: Zou Wei <zou_wei(a)huawei.com> --- drivers/hwtracing/coresight/coresight-etm-perf.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/hwtracing/coresight/coresight-etm-perf.c b/drivers/hwtracing/coresight/coresight-etm-perf.c index 0f603b4094f2..bdbb77334329 100644 --- a/drivers/hwtracing/coresight/coresight-etm-perf.c +++ b/drivers/hwtracing/coresight/coresight-etm-perf.c @@ -58,7 +58,7 @@ static ssize_t format_attr_contextid_show(struct device *dev, return sprintf(page, "config:%d\n", pid_fmt); } -struct device_attribute format_attr_contextid = +static struct device_attribute format_attr_contextid = __ATTR(contextid, 0444, format_attr_contextid_show, NULL); static struct attribute *etm_config_formats_attr[] = { -- 2.17.1

5 years, 7 months

[PATCH] coresight: core: Fix typo in coresight-core.c

by Qi Liu

Fix up one typo: compoment->component. Fixes: 8e264c52e1da ("coresight: core: Allow the coresight core driver to be built as a module") Signed-off-by: Qi Liu <liuqi115(a)huawei.com> --- drivers/hwtracing/coresight/coresight-core.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/hwtracing/coresight/coresight-core.c b/drivers/hwtracing/coresight/coresight-core.c index 0062c89..bc397a7 100644 --- a/drivers/hwtracing/coresight/coresight-core.c +++ b/drivers/hwtracing/coresight/coresight-core.c @@ -86,7 +86,7 @@ static int coresight_id_match(struct device *dev, void *data) i_csdev->type != CORESIGHT_DEV_TYPE_SOURCE) return 0; - /* Get the source ID for both compoment */ + /* Get the source ID for both component */ trace_id = source_ops(csdev)->trace_id(csdev); i_trace_id = source_ops(i_csdev)->trace_id(i_csdev); -- 2.8.1

5 years, 7 months

[PATCH v2] arm64: dts: msm8916: Enable CoreSight STM component

by Leo Yan

Add DT binding for CoreSight System Trace Macrocell (STM) on msm8916, which can benefit the CoreSight development on DB410c. Signed-off-by: Georgi Djakov <georgi.djakov(a)linaro.org> Signed-off-by: Leo Yan <leo.yan(a)linaro.org> --- Changes from v1: * alphabetically and address ordering for DT node; pad addresses with * zeroes (Stephan Gerhold). arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi | 1 + arch/arm64/boot/dts/qcom/msm8916.dtsi | 27 +++++++++++++++++++++++ 2 files changed, 28 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi b/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi index 3a9538e1ec97..2165b7415add 100644 --- a/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi +++ b/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi @@ -410,6 +410,7 @@ &wcd_codec { &funnel0 { status = "okay"; }; &funnel1 { status = "okay"; }; &replicator { status = "okay"; }; +&stm { status = "okay"; }; &tpiu { status = "okay"; }; &smd_rpm_regulators { diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index 402e891a84ab..f02b976480d5 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -489,6 +489,26 @@ snoc: interconnect@580000 { <&rpmcc RPM_SMD_SNOC_A_CLK>; }; + stm: stm@802000 { + compatible = "arm,coresight-stm", "arm,primecell"; + reg = <0x00802000 0x1000>, + <0x09280000 0x180000>; + reg-names = "stm-base", "stm-stimulus-base"; + + clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; + + status = "disabled"; + + out-ports { + port { + stm_out: endpoint { + remote-endpoint = <&funnel0_in7>; + }; + }; + }; + }; + /* System CTIs */ /* CTI 0 - TMC connections */ cti0: cti@810000 { @@ -562,6 +582,13 @@ funnel0_in4: endpoint { remote-endpoint = <&funnel1_out>; }; }; + + port@7 { + reg = <7>; + funnel0_in7: endpoint { + remote-endpoint = <&stm_out>; + }; + }; }; out-ports { -- 2.25.1

5 years, 7 months

Testing STM on the dragonboard 410c

by Enes Göktaş

Hello, I would like to test the System Trace Macrocell (STM) on db410c and tried following the steps at [1]. I am using linux kernel version 5.9.0-qcomlt-arm64 and I believe the steps described in the linked post are for an earlier version of the kernel. I tried those steps (but slightly adjusted so it is conform to the sysfs path on 5.9.0-qcomlt-arm64) and it fails when trying to link: *$ echo 802000.stm > **/sys/class/stm_source/ftrace/stm_source_link* bash: echo: write error: Invalid argument *$ echo stm > **/sys/class/stm_source/ftrace/stm_source_link* bash: echo: write error: Invalid argument *$ echo stm0 > **/sys/class/stm_source/ftrace/stm_source_link* bash: echo: write error: Invalid argument I'd be happy to test the steps on a working version of the kernel. Does anyone know for which kernel version the steps in [1] are? I'd also be grateful if someone has the right steps to test STM with ftrace on the recent kernel versions. Thank you, Enes [1] https://lists.linaro.org/pipermail/coresight/2018-August/001653.html

5 years, 7 months

Re: [RFC PATCH v3 1/1] perf cs-etm: Set time value for samples

by James Clark

Hi Wojciech, Are you still working on this patchset here? https://lists.linaro.org/pipermail/coresight/2019-June/002871.html I'm asking because I was also looking to make a change related to timestamps, and I see there has been quite a bit of discussion on your one over the revisions. My change would be something like I've pasted below. This was suggested by Al Grant so that the synthesized samples have kernel timestamps that can be correlated (at least roughly) with MMAP and COMM records. The issue is that in your patchset, you are also setting the sample.time field, but with the decoded timestamp rather than the kernel one. I suppose this email is to re-start the discussion with the whole mailing list about what should be in that field. Thanks James --- diff --git a/tools/perf/util/cs-etm.c b/tools/perf/util/cs-etm.c index 7206c7f..7f7a68c 100644 --- a/tools/perf/util/cs-etm.c +++ b/tools/perf/util/cs-etm.c @@ -55,6 +55,7 @@ struct cs_etm_auxtrace { u8 sample_instructions; int num_cpu; + u64 latest_timestamp; u32 auxtrace_type; u64 branches_sample_type; u64 branches_id; @@ -1152,6 +1153,7 @@ static int cs_etm__synth_instruction_sample(struct cs_etm_queue *etmq, event->sample.header.misc = cs_etm__cpu_mode(etmq, addr); event->sample.header.size = sizeof(struct perf_event_header); + sample.time = etm->latest_timestamp; sample.ip = addr; sample.pid = tidq->pid; sample.tid = tidq->tid; @@ -1209,6 +1211,7 @@ static int cs_etm__synth_branch_sample(struct cs_etm_queue *etmq, event->sample.header.misc = cs_etm__cpu_mode(etmq, ip); event->sample.header.size = sizeof(struct perf_event_header); + sample.time = etm->latest_timestamp; sample.ip = ip; sample.pid = tidq->pid; sample.tid = tidq->tid; @@ -2367,8 +2370,10 @@ static int cs_etm__process_event(struct perf_session *session, return cs_etm__process_switch_cpu_wide(etm, event); if (!etm->timeless_decoding && - event->header.type == PERF_RECORD_AUX) + event->header.type == PERF_RECORD_AUX) { + etm->latest_timestamp = timestamp; return cs_etm__process_queues(etm); + } return 0; }

5 years, 7 months

[PATCH v4 00/10] CoreSight configuration management; ETM strobing

by Mike Leach

This patchset introduces initial concepts in CoreSight system configuration management support. to allow more detailed and complex programming to be applied to CoreSight systems during trace capture. Configurations consist of 2 elements:- 1) Features - programming combinations for devices, applied to a class of device on the system (all ETMv4), or individual devices. 2) Configurations - a set of programmed features used when the named configuration is selected. Features and configurations are declared as a data table, a set of register, resource and parameter requirements. Features and configurations are loaded into the system by the virtual cs_syscfg device. This then matches features to any registered devices and loads the feature into them. Individual device classes that support feature and configuration register with cs_syscfg. Once loaded a configuration can be enabled for a specific trace run. Configurations are registered with the perf cs_etm event as entries in cs_etm/cs_config. These can be selected on the perf command line as follows:- perf record -e cs_etm/<config_name>/ ... This patch set has one pre-loaded configuration and feature. A named "strobing" feature is provided for ETMv4. A named "autofdo" configuration is provided. This configuration enables strobing on any ETM in used. Thus the command: perf record -e cs_etm/autofdo/ ... will trace the supplied application while enabling the "autofdo" configuation on each ETM as it is enabled by perf. This in turn will enable strobing for the ETM - with default parameters. Parameters can be adjusted using configfs. The sink used in the trace run will be automatically selected. A configuation can supply up to 15 of preset parameter values, which will subsitute in parameter values for any feature used in the configuration. Selection of preset values as follows perf record -e cs_etm/autofdo,preset=1/ ... (valid presets 1-N, where N is the number supplied in the configuration, not exceeding 15. preset=0 is the same as not selecting a preset.) Applies to coresight/next (5.11-rc2 base) Changes since v3: (Primarily based on comments from Matthieu) 1) Locking mechanisms simplified. 2) Removed the possibility to enable features independently from configurations.Only configurations can be enabled now. Simplifies programming logic. 3) Configuration now uses an activate->enable mechanism. This means that perf will activate a selected configuration at the start of a session (during setup_aux), and disable at the end of a session (around free_aux) The active configuration and associated features will be programmed into the CoreSight device instances when they are enabled. This locks the configuration into the system while in use. Parameters cannot be altered while this is in place. This mechanism will be extended in future for dynamic load / unload of configurations to prevent removal while in use. 4) Removed the custom bus / driver as un-necessary. A single device is registered to own perf fs elements and configfs. 5) Various other minor issues addressed. Changes since v2: 1) Added documentation file. 2) Altered cs_syscfg driver to no longer be coresight_device based, and moved to its own custom bus to remove it from the main coresight bus. (Mathieu) 3) Added configfs support to inspect and control loaded configurations and features. Allows listing of preset values (Yabin Cui) 4) Dropped sysfs support for adjusting feature parameters on the per device basis, in favour of a single point adjustment in configfs that is pushed to all device instances. 5) Altered how the config and preset command line options are handled in perf and the drivers. (Mathieu and Suzuki). 6) Fixes for various issues and technical points (Mathieu, Yabin) Changes since v1: 1) Moved preloaded configurations and features out of individual drivers. 2) Added cs_syscfg driver to manage configurations and features. Individual drivers register with cs_syscfg indicating support for config, and provide matching information that the system uses to load features into the drivers. This allows individual drivers to be updated on an as needed basis - and removes the need to consider devices that cannot benefit from configuration - static replicators, funnels, tpiu. 3) Added perf selection of configuarations. 4) Rebased onto the coresight module loading set. To follow in future revisions / sets:- a) load of additional config and features by loadable module. b) load of additional config and features by configfs c) enhanced resource management for ETMv4 and checking features have sufficient resources to be enabled. d) ECT and CTI support for configuration and features. Mike Leach (10): coresight: syscfg: Initial coresight system configuration coresight: syscfg: Add registration and feature loading for cs devices coresight: config: Add configuration and feature generic functions coresight: etm-perf: update to handle configuration selection coresight: syscfg: Add API to activate and enable configurations coresight: etm-perf: Update to activate selected configuration coresight: etm4x: Add complex configuration handlers to etmv4 coresight: config: Add preloaded configurations coresight: syscfg: Add initial configfs support coresight: docs: Add documentation for CoreSight config .../trace/coresight/coresight-config.rst | 244 ++++++ Documentation/trace/coresight/coresight.rst | 16 + drivers/hwtracing/coresight/Makefile | 7 +- .../hwtracing/coresight/coresight-cfg-afdo.c | 154 ++++ .../coresight/coresight-cfg-preload.c | 25 + .../coresight/coresight-cfg-preload.h | 11 + .../hwtracing/coresight/coresight-config.c | 246 ++++++ .../hwtracing/coresight/coresight-config.h | 282 +++++++ drivers/hwtracing/coresight/coresight-core.c | 18 +- .../hwtracing/coresight/coresight-etm-perf.c | 180 ++++- .../hwtracing/coresight/coresight-etm-perf.h | 12 +- .../hwtracing/coresight/coresight-etm4x-cfg.c | 184 +++++ .../hwtracing/coresight/coresight-etm4x-cfg.h | 29 + .../coresight/coresight-etm4x-core.c | 38 +- .../coresight/coresight-etm4x-sysfs.c | 3 + .../coresight/coresight-syscfg-configfs.c | 399 +++++++++ .../coresight/coresight-syscfg-configfs.h | 45 ++ .../hwtracing/coresight/coresight-syscfg.c | 761 ++++++++++++++++++ .../hwtracing/coresight/coresight-syscfg.h | 90 +++ include/linux/coresight.h | 7 + 20 files changed, 2721 insertions(+), 30 deletions(-) create mode 100644 Documentation/trace/coresight/coresight-config.rst create mode 100644 drivers/hwtracing/coresight/coresight-cfg-afdo.c create mode 100644 drivers/hwtracing/coresight/coresight-cfg-preload.c create mode 100644 drivers/hwtracing/coresight/coresight-cfg-preload.h create mode 100644 drivers/hwtracing/coresight/coresight-config.c create mode 100644 drivers/hwtracing/coresight/coresight-config.h create mode 100644 drivers/hwtracing/coresight/coresight-etm4x-cfg.c create mode 100644 drivers/hwtracing/coresight/coresight-etm4x-cfg.h create mode 100644 drivers/hwtracing/coresight/coresight-syscfg-configfs.c create mode 100644 drivers/hwtracing/coresight/coresight-syscfg-configfs.h create mode 100644 drivers/hwtracing/coresight/coresight-syscfg.c create mode 100644 drivers/hwtracing/coresight/coresight-syscfg.h -- 2.17.1

5 years, 8 months

Re: Secure World Coresight Tracing - HiKey 960

by Mike Leach

Hi Daniel, The CoreSight mailing list is the best place to ask these questions - I've added it to the to: section of this mail. On Fri, 19 Feb 2021 at 13:43, Daniel Su <daniel.sun.su(a)gmail.com> wrote: > > Sorry I made a mistake, I need to switch those bits but those aren't in the ETM mode sysFS parameter. > > > On Feb 19, 2021, at 14:21, Daniel Su <daniel.sun.su(a)gmail.com> wrote: > > > > Thanks, > > > > To just give a bit of background I am doing an internship to improve tracing and debugging for secure world applications in TrustZone. Originally the idea was to come up with a software solution but I thought using the hardware tracing features might be very powerful as the secure world trusted execution environments typically have less debugging and tracing functionalities built into the trusted operating system. > > > > I have been doing further reading and I believe I need to configure the ETM mode sysFS parameter. > > > > To switch these bits: > > > > /* secure state access levels - TRCACATRn */ > > #define ETM_EXLEVEL_S_APP BIT(8) > > #define ETM_EXLEVEL_S_OS BIT(9) > > #define ETM_EXLEVEL_S_HYP BIT(10) > > #define ETM_EXLEVEL_S_MON BIT(11) > > /* non-secure state access levels - TRCACATRn */ > > #define ETM_EXLEVEL_NS_APP BIT(12) > > #define ETM_EXLEVEL_NS_OS BIT(13) > > #define ETM_EXLEVEL_NS_HYP BIT(14) > > #define ETM_EXLEVEL_NS_NA BIT(15) > > ns_exlevel_vinst and s_exlevel_vinst control these bits in the TRCVICTLR. addr_exlevel_s_ns sets both S and NS bits in the TRCACATRn register currently addressed by addr_idx. In the kernel tree - Documentation/trace/coresight/coresight-etm4x-reference.rst - has lots of information on programming these sysfs files. I would advise setting mode first - which will set up some default values for TRCVITLR, then make any further adjustments you want. > > Right now I am able to capture the traces and read them out thanks to Leo Yan's command examples and presentation. > > > > I still need to figure out how to only trace branching instructions, and also how to best decode the traces. Right now even though I can read out /dev/ec036000.etf , I am unsure how to best go about interpreting the raw trace data. > > Hardware trace will trace everything - subject to certain filters - such as address filtering, exception filtering etc. It is not possible to trace only branch instructions. You will need to capture trace, decode then run an analysis on that decode to determine what branches have been taken. ETMv4 is program flow trace - so all branches are marked as taken or not taken. Consider the program:- =============== 0x1000 start: < some code > ... 0x1100 B func1 0x1200 func1: <some code> .... 0x1240 mov r0, &func2 B r0 0x2000 func2: <some code> ================ This will result in trace as follows:- TRACE_ON ADDR(0x1000) ATOM(E) > > I believe ptm2human and OpenCSD are two open source libraries that allow for decoding of the ETMv4 trace data. I understand there are paid solutions as well such as the DS-5 and Trace32 from Lauterbach to decode. > > > > Do you have any recommendations on other decoders or any tips in general as to how to decode the raw trace data into human readable format? > > > > Best, > > Daniel > > > >> On Feb 18, 2021, at 18:38, Suzuki K Poulose <suzuki.poulose(a)arm.com> wrote: > >> > >> Hi Daniel > >> > >> On 2/18/21 4:12 PM, Daniel Su wrote: > >>> Hello, > >>> First of all I want to say thanks for your work on the Coresight support as well as the presentation slides. Currently I am working with the Hikey960 which I see is supported and has been used as a reference platform in your slides. > >>> I believe it should be possible to setup self-hosted Coresight to trace only for branch instructions in the secure world. Currently I am investigating how to set this up on the Hikey960 without access to a hardware debugger. > >>> I am wondering if any of you have done this before, if there is additional documentation, or if there are any good support groups/chats/channels to ask questions. I have some experience with Coresight mainly from reading the ARM reference manuals but it is still a lot to parse. > >> > >> I haven't done anything similar. You should be able to imitate how the > >> CoreSight drivers program the components ( ETM, Funnels, Replicator and ETR). > >> > >> For ETM, you just need to make sure you don't filter out the Secure EL1/EL2/EL0. > >> You would need to read the manuals for the components or user the kernel driver > >> as the reference. > >> > >> Cheers > >> Suzuki > >> > >>> I believe in Linux I should be using `ns_exlevel_vinst` to filter out Non-Secure instructions. Also since the Hikey960 is multicore, I guess I would need to configure the top level Coresight in order to trace all cores? Would this be the ETR then? > >>> Best, > >>> Daniel > >> > > > -- Mike Leach Principal Engineer, ARM Ltd. Manchester Design Centre. UK

5 years, 8 months

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