CoreSight

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6 participants
2648 discussions

by Michael Petlan

Hello coresight-list! I have a question about the future of OpenCSD library API. How stable is it going to be? I see there's currently v1.0, so I understand it as that there's already some API version which is considered to be "mature". Could anyone please help estimating whether major API changes are planned/to be expected in upcoming years? Thank you! Michael

5 years, 8 months

opencsd in gdb: difference between etm parser report when hitting an exception between STM32MP1 and APQ 8016e

by Zied Guermazi

hi Mike I am compiling , running and debugging a program generated from the same source code on ARMv7 and ARMv8 processors. when a breakpoint is hit, I am using the traces to reconstruct the execution flow. I noticed that on stm32 the decoder emits the address of the breakpoint in an OCSD_GEN_TRC_ELEM_INSTR_RANGE twice (before and after the exception), whereas it emits it only once (after the exception). I need to have different handling according to the situation. what can I use to distinguish both cases and handle the traces properly: - the ETM version (v3.x vs v4.x) - the CPU architecture (Cortex A v7 vs cortex A v8) - the ISA of executed program (A64 vs (A32 or T32 )) - the exception number below are the logs on stm32MP1 (ARMv7, cortex A7) [btrace] ETM trace_element: index= 12, channel= 0x10, OCSD_GEN_TRC_ELEM_INSTR_RANGE(exec range=0x103f4:[0x103f6] num_i(1) last_sz(2) (ISA=T32) E --- ) [btrace] ETM trace_element: index= 13, channel= 0x10, OCSD_GEN_TRC_ELEM_EXCEPTION(excep num (0x09) ) [btrace] ETM trace_element: index= 54, channel= 0x10, OCSD_GEN_TRC_ELEM_TRACE_ON( [begin or filter]) [btrace] ETM trace_element: index= 54, channel= 0x10, OCSD_GEN_TRC_ELEM_PE_CONTEXT((ISA=T32) N; 32-bit; ) [btrace] ETM trace_element: index= 60, channel= 0x10, OCSD_GEN_TRC_ELEM_INSTR_RANGE(exec range=0x103f4:[0x103f6] num_i(1) last_sz(2) (ISA=T32) E --- ) on qcom APQ8016e(ARMv8, Cortex A53) [btrace] ETM trace_element: index= 38, channel= 0x12, OCSD_GEN_TRC_ELEM_INSTR_RANGE(exec range=0x4005b4:[0x4005b8] num_i(1) last_sz(4) (ISA=A64) E --- ) [btrace] ETM trace_element: index= 38, channel= 0x12, OCSD_GEN_TRC_ELEM_EXCEPTION(pref ret addr:0x4005b8; excep num (0x06) ) [btrace] ETM trace_element: index= 112, channel= 0x16, OCSD_GEN_TRC_ELEM_NO_SYNC( [init-decoder]) [btrace] ETM trace_element: index= 138, channel= 0x16, OCSD_GEN_TRC_ELEM_TRACE_ON( [begin or filter]) [btrace] ETM trace_element: index= 139, channel= 0x16, OCSD_GEN_TRC_ELEM_PE_CONTEXT((ISA=A64) EL0N; 64-bit; ) [btrace] ETM trace_element: index= 150, channel= 0x16, OCSD_GEN_TRC_ELEM_INSTR_RANGE(exec range=0x4005b8:[0x4005bc] num_i(1) last_sz(4) (ISA=A64) E BR ) Kind Regards Zied Guermazi -- *Zied Guermazi* founder Trande UG Leuschnerstraße 2 69469 Weinheim/Germany Mobile: +491722645127 mailto:zied.guermazi@trande.de *Trande UG* Leuschnerstraße 2, D-69469 Weinheim; Telefon: +491722645127 Sitz der Gesellschaft: Weinheim- Registergericht: AG Mannheim HRB 736209 - Geschäftsführung: Zied Guermazi *Confidentiality Note* This message is intended only for the use of the named recipient(s) and may contain confidential and/or privileged information. If you are not the intended recipient, please contact the sender and delete the message. Any unauthorized use of the information contained in this message is prohibited.

5 years, 8 months

[PATCH v1 0/7] coresight: etm-perf: Fix pid tracing with VHE

by Leo Yan

This patch series is a following up for the previous version which was delivered by Suzuki [1]. Below gives the background info for why we need this patch series, directly quotes the description in the cover letter of the previous version: "With the Virtualization Host Extensions, the kernel can run at EL2. In this case the pid is written to CONTEXTIDR_EL2 instead of the CONTEXTIDR_EL1. Thus the normal coresight tracing will be unable to detect the PID of the thread generating the trace by looking at the CONTEXTIDR_EL1. Thus, depending on the kernel EL, we must switch to tracing the correct CONTEXTIDR register. With VHE, we must set the TRCCONFIGR.VMID and TRCCONFIGR.VMID_OPT to include the CONTEXTIDR_EL2 as the VMID in the trace. This requires the perf tool to detect the changes in the TRCCONFIGR and use the VMID / CID field for the PID. The challenge here is for the perf tool to detect the kernel behavior. Instead of the previously proposed invasive approaches, this set implements a less intrusive mechanism, by playing with the perf_event.attribute.config bits." Same as the previous series, this series keeps the same implementation for two introduced format bits: - contextid_in_vmid -> Is only supported when the VMID tracing and CONTEXTIDR_EL2 both are supported. When requested the perf etm4x backend sets (TRCCONFIGR.VMID | TRCCONFIGR.VMID_OPT). As per ETMv4.4 TRM, when the core supports VHE, the CONTEXTIDR_EL2 tracing is mandatory. (See the field TRCID2.VMIDOPT) - pid -> Is an alias for the correct config to enable PID tracing on any kernel. i.e, in EL1 kernel -> pid == contextid EL2 kernel -> pid == contextid_in_vmid With this, the perf tool is also updated to request the "pid" tracing whenever available, falling back to "contextid" if it is unavailable. Comparing against the old version, this patch series uses the metadata to save PID format; after add new item into metadata, it introduces backward compatibility issue. To allow backward compatibility, this series calculates per CPU metadata array size and avoid to use the defined macro, so can always know the correct array size based on the info stored in perf data file. Finally, the PID format stored in metadata is passed to decoder and guide the decoder to set PID from CONTEXTIDR_EL1 or VMID. This patch series has been tested on Arm Juno-r2 board, with testing two perf data files: one data file is recorded by the latest perf tool after applied this patch series, and another data file is recorded by old perf tool without this patch series, so this can prove the tool is backward compatible. Changes from RFC: * Added comments to clarify cases requested (Leo); * Explain the change to generic flags for cs_etm_set_option() in the commit description; * Stored PID format in metadata and passed it to decoder (Leo); * Enhanced cs-etm for backward compatibility (Denis Nikitin). [1] https://archive.armlinux.org.uk/lurker/message/20201110.183310.24406f33.en.… Leo Yan (4): perf cs-etm: Calculate per CPU metadata array size perf cs-etm: Add PID format into metadata perf cs-etm: Fixup PID_FMT when it is zero perf cs-etm: Add helper cs_etm__get_pid_fmt() Suzuki K Poulose (3): coresight: etm-perf: Add support for PID tracing for kernel at EL2 perf cs_etm: Use pid tracing explicitly instead of contextid perf cs-etm: Detect pid in VMID for kernel running at EL2 .../hwtracing/coresight/coresight-etm-perf.c | 14 +++ .../coresight/coresight-etm4x-core.c | 9 ++ include/linux/coresight-pmu.h | 11 ++- tools/include/linux/coresight-pmu.h | 11 ++- tools/perf/arch/arm/util/cs-etm.c | 89 +++++++++++++++---- .../perf/util/cs-etm-decoder/cs-etm-decoder.c | 32 ++++++- tools/perf/util/cs-etm.c | 61 ++++++++++++- tools/perf/util/cs-etm.h | 3 + 8 files changed, 198 insertions(+), 32 deletions(-) -- 2.25.1

5 years, 8 months

[PATCH V2] coresight: etm4x: add AMBA id for Cortex-A55 and Cortex-A75

by Chunyan Zhang

From: Chunyan Zhang <chunyan.zhang(a)unisoc.com> Add AMBA UCI id to support Cortex-A55(Ananke) and Cortex-A75(Promethus). Signed-off-by: Bin Ji <bin.ji(a)unisoc.com> Signed-off-by: Chunyan Zhang <chunyan.zhang(a)unisoc.com> --- Changes since v1: * Addressed Mike's comments - changed to use CS_AMBA_UCI_ID(). --- drivers/hwtracing/coresight/coresight-etm4x-core.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c index b20b6ff17cf6..8c4b0c46c8f3 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c @@ -1713,6 +1713,8 @@ static const struct amba_id etm4_ids[] = { CS_AMBA_ID(0x000bb95a), /* Cortex-A72 */ CS_AMBA_ID(0x000bb959), /* Cortex-A73 */ CS_AMBA_UCI_ID(0x000bb9da, uci_id_etm4),/* Cortex-A35 */ + CS_AMBA_UCI_ID(0x000bbd05, uci_id_etm4),/* Cortex-A55 */ + CS_AMBA_UCI_ID(0x000bbd0a, uci_id_etm4),/* Cortex-A75 */ CS_AMBA_UCI_ID(0x000bbd0c, uci_id_etm4),/* Neoverse N1 */ CS_AMBA_UCI_ID(0x000f0205, uci_id_etm4),/* Qualcomm Kryo */ CS_AMBA_UCI_ID(0x000f0211, uci_id_etm4),/* Qualcomm Kryo */ -- 2.25.1

5 years, 8 months

[PATCH] coresight: etm4x: add AMBA id for Cortex-A55 and Cortex-A75

by Chunyan Zhang

From: Bin Ji <bin.ji(a)unisoc.com> Add ETM amba id to support Cortex-A55(Ananke) and Cortex-A75(Promethus). Signed-off-by: Bin Ji <bin.ji(a)unisoc.com> Signed-off-by: Chunyan Zhang <chunyan.zhang(a)unisoc.com> --- drivers/hwtracing/coresight/coresight-etm4x-core.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c index b20b6ff17cf6..66c6641c71ea 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c @@ -1709,9 +1709,11 @@ static int etm4_remove(struct amba_device *adev) static const struct amba_id etm4_ids[] = { CS_AMBA_ID(0x000bb95d), /* Cortex-A53 */ + CS_AMBA_ID(0x000bbd05), /* Cortex-A55 */ CS_AMBA_ID(0x000bb95e), /* Cortex-A57 */ CS_AMBA_ID(0x000bb95a), /* Cortex-A72 */ CS_AMBA_ID(0x000bb959), /* Cortex-A73 */ + CS_AMBA_ID(0x000bbd0a), /* Cortex-A75 */ CS_AMBA_UCI_ID(0x000bb9da, uci_id_etm4),/* Cortex-A35 */ CS_AMBA_UCI_ID(0x000bbd0c, uci_id_etm4),/* Neoverse N1 */ CS_AMBA_UCI_ID(0x000f0205, uci_id_etm4),/* Qualcomm Kryo */ -- 2.25.1

5 years, 8 months

[PATCH] perf tools: Update OpenCSD to v1.0.0

by James Clark

Replace the OCSD_INSTR switch statement with an if to fix compilation error about unhandled values and avoid this issue again in the future. Add new OCSD_GEN_TRC_ELEM_SYNC_MARKER and OCSD_GEN_TRC_ELEM_MEMTRANS enum values to fix unhandled value compilation error. Currently they are ignored. Increase the minimum version number to v1.0.0 now that new enum values are used that are only present in this version. Signed-off-by: James Clark <james.clark(a)arm.com> Cc: John Garry <john.garry(a)huawei.com> Cc: Will Deacon <will(a)kernel.org> Cc: Mathieu Poirier <mathieu.poirier(a)linaro.org> Cc: Leo Yan <leo.yan(a)linaro.org> Cc: Suzuki K Poulose <suzuki.poulose(a)arm.com> Cc: Mike Leach <mike.leach(a)linaro.org> Cc: Al Grant <al.grant(a)arm.com> Cc: Peter Zijlstra <peterz(a)infradead.org> Cc: Ingo Molnar <mingo(a)redhat.com> Cc: Arnaldo Carvalho de Melo <acme(a)kernel.org> Cc: Mark Rutland <mark.rutland(a)arm.com> Cc: Alexander Shishkin <alexander.shishkin(a)linux.intel.com> Cc: Jiri Olsa <jolsa(a)redhat.com> Cc: Namhyung Kim <namhyung(a)kernel.org> --- tools/build/feature/test-libopencsd.c | 4 ++-- tools/perf/util/cs-etm-decoder/cs-etm-decoder.c | 15 ++++----------- 2 files changed, 6 insertions(+), 13 deletions(-) diff --git a/tools/build/feature/test-libopencsd.c b/tools/build/feature/test-libopencsd.c index 1547bc2c0950..52c790b0317b 100644 --- a/tools/build/feature/test-libopencsd.c +++ b/tools/build/feature/test-libopencsd.c @@ -4,9 +4,9 @@ /* * Check OpenCSD library version is sufficient to provide required features */ -#define OCSD_MIN_VER ((0 << 16) | (14 << 8) | (0)) +#define OCSD_MIN_VER ((1 << 16) | (0 << 8) | (0)) #if !defined(OCSD_VER_NUM) || (OCSD_VER_NUM < OCSD_MIN_VER) -#error "OpenCSD >= 0.14.0 is required" +#error "OpenCSD >= 1.0.0 is required" #endif int main(void) diff --git a/tools/perf/util/cs-etm-decoder/cs-etm-decoder.c b/tools/perf/util/cs-etm-decoder/cs-etm-decoder.c index cd007cc9c283..3f4bc4050477 100644 --- a/tools/perf/util/cs-etm-decoder/cs-etm-decoder.c +++ b/tools/perf/util/cs-etm-decoder/cs-etm-decoder.c @@ -419,19 +419,10 @@ cs_etm_decoder__buffer_range(struct cs_etm_queue *etmq, packet->last_instr_subtype = elem->last_i_subtype; packet->last_instr_cond = elem->last_instr_cond; - switch (elem->last_i_type) { - case OCSD_INSTR_BR: - case OCSD_INSTR_BR_INDIRECT: + if (elem->last_i_type == OCSD_INSTR_BR || elem->last_i_type == OCSD_INSTR_BR_INDIRECT) packet->last_instr_taken_branch = elem->last_instr_exec; - break; - case OCSD_INSTR_ISB: - case OCSD_INSTR_DSB_DMB: - case OCSD_INSTR_WFI_WFE: - case OCSD_INSTR_OTHER: - default: + else packet->last_instr_taken_branch = false; - break; - } packet->last_instr_size = elem->last_instr_sz; @@ -572,6 +563,8 @@ static ocsd_datapath_resp_t cs_etm_decoder__gen_trace_elem_printer( case OCSD_GEN_TRC_ELEM_EVENT: case OCSD_GEN_TRC_ELEM_SWTRACE: case OCSD_GEN_TRC_ELEM_CUSTOM: + case OCSD_GEN_TRC_ELEM_SYNC_MARKER: + case OCSD_GEN_TRC_ELEM_MEMTRANS: default: break; } -- 2.28.0

5 years, 8 months

Re: Reading and Decoding Data From ETB Buffer

by Mathieu Poirier

Adding the coresight mailing list On Tue, 12 Jan 2021 at 04:17, Ajay Bharadwaj <ajayrbharadwaj(a)gmail.com> wrote: > > Hi, > > I'm working on enabling STM and ETB support on Texas Instruments' platforms. > > Currently, I can write directly to the STM device in sysfs and read back > the encoded data from the ETB's buffer. I am using the Trace Packet > Lister (trc_pkt_lister) from Linaro's OpenCSD [1] to decode the data > obtained from the ETB. The decoded data matches what was written to the > STM (Albeit the data is reversed in some cases, this seems to be > expected according to the ARM specification). > > However, when I use the STM Source Console [2] instead of writing > directly to the STM device, I can still read back the encoded data from > the ETB buffer but OpenCSD cannot find any trace data in it. > > Is there any other tool that I can use instead of OpenCSD or am I doing > something wrong? Here are the commands I am running (I've tried using > the p_sys-t STP policy as well with the same result): > > Enabling CoreSight and STM Source Console: > 1. mkdir -p /config > 2. mount -t configfs none /config > 3. mkdir /config/stp-policy/stm0.policy > 4. mkdir /config/stp-policy/stm0.policy/console > 5. echo 1 > /sys/bus/coresight/devices/etb0/enable_sink > 6. echo stm0 > /sys/class/stm_source/console/stm_source_link > > Reading decoded data from ETB buffer: > 1. dd if=/dev/etb0 of=test.bin > > OpenCSD Output: > Trace Packet Lister: CS Decode library testing > ----------------------------------------------- > > ** Library Version : 0.14.4 > > Test Command Line:- > ./tests/bin/linux64/dbg/trc_pkt_lister -ss_dir > tests/snapshots/stm_only/ -src_name ETB_1 > > Trace Packet Lister : reading snapshot from path tests/snapshots/stm_only/ > Using ETB_1 as trace source > Trace Packet Lister : Protocol printer STM on Trace ID 0x1 > ID:1 END OF TRACE DATA > Trace Packet Lister : Trace buffer done, processed 16384 bytes. > > [1] > https://github.com/Linaro/OpenCSD/blob/master/decoder/tests/source/trc_pkt_… > [2] Driver: hwtracing/stm/console.c > > Any help or guidance would be much appreciated. > > Regards, > Ajay Bharadwaj

5 years, 8 months

[PATCH] perf: cs-etm: update ETM metadata format

by Mike Leach

The current fixed metadata version format (version 0), means that adding metadata parameter items renders files from a previous version of perf unreadable. Per CPU parameters appear in a fixed order, but there is no field to indicate the number of ETM parameters per CPU. This patch updates the per CPU parameter blocks to include a NR_PARAMs value which indicates the number of parameters in the block. The header version is incremented to 1. Fixed ordering is retained, new ETM parameters are added to the end of the list. The reader code is updated to be able to read current version 0 files, For version 1, the reader will read the number of parameters in the per CPU block. This allows the reader to process older or newer files that may have different numbers of parameters than in use at the time perf was built. Signed-off-by: Mike Leach <mike.leach(a)linaro.org> --- tools/perf/arch/arm/util/cs-etm.c | 3 +- tools/perf/util/cs-etm.c | 171 ++++++++++++++++++++++++------ tools/perf/util/cs-etm.h | 22 +++- 3 files changed, 159 insertions(+), 37 deletions(-) diff --git a/tools/perf/arch/arm/util/cs-etm.c b/tools/perf/arch/arm/util/cs-etm.c index bd446aba64f7..1876cdf146a0 100644 --- a/tools/perf/arch/arm/util/cs-etm.c +++ b/tools/perf/arch/arm/util/cs-etm.c @@ -629,6 +629,7 @@ static void cs_etm_get_metadata(int cpu, u32 *offset, /* Build generic header portion */ info->priv[*offset + CS_ETM_MAGIC] = magic; info->priv[*offset + CS_ETM_CPU] = cpu; + info->priv[*offset + CS_ETM_NR_PARAMS] = increment - CS_ETM_NR_PARAMS - 1; /* Where the next CPU entry should start from */ *offset += increment; } @@ -674,7 +675,7 @@ static int cs_etm_info_fill(struct auxtrace_record *itr, /* First fill out the session header */ info->type = PERF_AUXTRACE_CS_ETM; - info->priv[CS_HEADER_VERSION_0] = 0; + info->priv[CS_HEADER_VERSION_0] = CS_HEADER_CURRENT_VERSION; info->priv[CS_PMU_TYPE_CPUS] = type << 32; info->priv[CS_PMU_TYPE_CPUS] |= nr_cpu; info->priv[CS_ETM_SNAPSHOT] = ptr->snapshot_mode; diff --git a/tools/perf/util/cs-etm.c b/tools/perf/util/cs-etm.c index a2a369e2fbb6..394331aa058a 100644 --- a/tools/perf/util/cs-etm.c +++ b/tools/perf/util/cs-etm.c @@ -2443,6 +2443,7 @@ static const char * const cs_etm_global_header_fmts[] = { static const char * const cs_etm_priv_fmts[] = { [CS_ETM_MAGIC] = " Magic number %llx\n", [CS_ETM_CPU] = " CPU %lld\n", + [CS_ETM_NR_PARAMS] = " NR_PARAMS %llx\n", [CS_ETM_ETMCR] = " ETMCR %llx\n", [CS_ETM_ETMTRACEIDR] = " ETMTRACEIDR %llx\n", [CS_ETM_ETMCCER] = " ETMCCER %llx\n", @@ -2452,6 +2453,7 @@ static const char * const cs_etm_priv_fmts[] = { static const char * const cs_etmv4_priv_fmts[] = { [CS_ETM_MAGIC] = " Magic number %llx\n", [CS_ETM_CPU] = " CPU %lld\n", + [CS_ETM_NR_PARAMS] = " NR_PARAMS %llx\n", [CS_ETMV4_TRCCONFIGR] = " TRCCONFIGR %llx\n", [CS_ETMV4_TRCTRACEIDR] = " TRCTRACEIDR %llx\n", [CS_ETMV4_TRCIDR0] = " TRCIDR0 %llx\n", @@ -2461,24 +2463,127 @@ static const char * const cs_etmv4_priv_fmts[] = { [CS_ETMV4_TRCAUTHSTATUS] = " TRCAUTHSTATUS %llx\n", }; +static const char * const param_unk_fmt = + " Unknown parameter [%d] %llx\n"; +static const char * const magic_unk_fmt = + " Magic number Unknown %llx\n"; + static void cs_etm__print_auxtrace_info(__u64 *val, int num) { - int i, j, cpu = 0; + int i, j, cpu = 0, version, nr_params; + __u64 magic; + fprintf(stdout, " Reader Header version %llx\n", + (__u64)CS_HEADER_CURRENT_VERSION); for (i = 0; i < CS_HEADER_VERSION_0_MAX; i++) fprintf(stdout, cs_etm_global_header_fmts[i], val[i]); + version = val[0]; for (i = CS_HEADER_VERSION_0_MAX; cpu < num; cpu++) { - if (val[i] == __perf_cs_etmv3_magic) - for (j = 0; j < CS_ETM_PRIV_MAX; j++, i++) - fprintf(stdout, cs_etm_priv_fmts[j], val[i]); - else if (val[i] == __perf_cs_etmv4_magic) - for (j = 0; j < CS_ETMV4_PRIV_MAX; j++, i++) - fprintf(stdout, cs_etmv4_priv_fmts[j], val[i]); - else + /* common header block */ + magic = val[i]; + fprintf(stdout, cs_etm_priv_fmts[0], val[i++]); + fprintf(stdout, cs_etm_priv_fmts[1], val[i++]); + + /* nr param only present in version 1 */ + if (version) { + nr_params = val[i]; + fprintf(stdout, cs_etm_priv_fmts[2], val[i++]); + } + + if (magic == __perf_cs_etmv3_magic) { + /* version 0 - fixed number of params */ + if (!version) + nr_params = CS_ETM_NR_PARAMS_V0; + + /* after common block */ + for (j = 3; j < nr_params + 3; j++, i++) { + /* if newer record - could be excess params */ + if (j >= CS_ETM_PRIV_MAX) + fprintf(stdout, param_unk_fmt, j, val[i]); + else + fprintf(stdout, cs_etm_priv_fmts[j], val[i]); + } + } else if (magic == __perf_cs_etmv4_magic) { + /* version 0 - fixed number of params */ + if (!version) + nr_params = CS_ETMV4_NR_PARAMS_V0; + + /* after common block */ + for (j = 3; j < nr_params + 3; j++, i++) { + /* if newer record - could be excess params */ + if (j >= CS_ETMV4_PRIV_MAX) + fprintf(stdout, param_unk_fmt, j, val[i]); + else + fprintf(stdout, cs_etmv4_priv_fmts[j], val[i]); + } + } else { /* failure.. return */ + fprintf(stdout, magic_unk_fmt, magic); return; + } + } +} + +/* + * Read a single cpu parameter block from the auxtrace_info priv block. + * + * For version 1 there is a per cpu nr_params entry. If we are handling + * version 1 file, then there may be less, the same, or more params + * indicated by this value than the compile time number we understand. + * + * For a version 0 info block, there are a fixed number, and we need to + * fill out the nr_param value in the metadata we create. + */ +static u64 *cs_etm__create_meta_blk(u64 *buff_in, int *buff_in_offset, + int out_blk_size, int nr_params_v0) +{ + u64 *metadata = NULL; + int hdr_version; + int nr_in_params, nr_out_params, nr_cmn_params; + int i, k; + + metadata = zalloc(sizeof(*metadata) * out_blk_size); + if (!metadata) + return NULL; + + /* read block current index & version */ + i = *buff_in_offset; + hdr_version = buff_in[CS_HEADER_VERSION_0]; + + if (!hdr_version) { + /* read version 0 info block into a version 1 metadata block */ + nr_in_params = nr_params_v0; + metadata[CS_ETM_MAGIC] = buff_in[i + CS_ETM_MAGIC]; + metadata[CS_ETM_CPU] = buff_in[i + CS_ETM_CPU]; + metadata[CS_ETM_NR_PARAMS] = nr_in_params; + /* remaining block params at offset +1 from source */ + for (k = 2; k < nr_in_params; k++) + metadata[k+1] = buff_in[i + k]; + /* version 0 has 2 common params */ + nr_cmn_params = 2; + } else { + /* read version 1 info block - input and output nr_params may differ */ + /* version 1 has 3 common params */ + nr_cmn_params = 3; + nr_in_params = buff_in[i + CS_ETM_NR_PARAMS]; + + /* if input has more params than output - skip excess */ + nr_out_params = nr_in_params + nr_cmn_params; + if (nr_out_params > out_blk_size) + nr_out_params = out_blk_size; + + for (k = 0; k < nr_out_params; k++) + metadata[k] = buff_in[i + k]; + + /* record the actual nr params we copied */ + metadata[CS_ETM_NR_PARAMS] = nr_out_params - nr_cmn_params; } + + /* adjust in offset by number of in params used */ + i += nr_in_params + nr_cmn_params; + *buff_in_offset = i; + return metadata; } int cs_etm__process_auxtrace_info(union perf_event *event, @@ -2492,11 +2597,12 @@ int cs_etm__process_auxtrace_info(union perf_event *event, int info_header_size; int total_size = auxtrace_info->header.size; int priv_size = 0; - int num_cpu; - int err = 0, idx = -1; - int i, j, k; + int num_cpu, trcidr_idx; + int err = 0; + int i, j; u64 *ptr, *hdr = NULL; u64 **metadata = NULL; + u64 hdr_version; /* * sizeof(auxtrace_info_event::type) + @@ -2512,8 +2618,9 @@ int cs_etm__process_auxtrace_info(union perf_event *event, /* First the global part */ ptr = (u64 *) auxtrace_info->priv; - /* Look for version '0' of the header */ - if (ptr[0] != 0) + /* Look for version of the header */ + hdr_version = ptr[0]; + if (hdr_version > CS_HEADER_CURRENT_VERSION) return -EINVAL; hdr = zalloc(sizeof(*hdr) * CS_HEADER_VERSION_0_MAX); @@ -2552,35 +2659,31 @@ int cs_etm__process_auxtrace_info(union perf_event *event, */ for (j = 0; j < num_cpu; j++) { if (ptr[i] == __perf_cs_etmv3_magic) { - metadata[j] = zalloc(sizeof(*metadata[j]) * - CS_ETM_PRIV_MAX); - if (!metadata[j]) { - err = -ENOMEM; - goto err_free_metadata; - } - for (k = 0; k < CS_ETM_PRIV_MAX; k++) - metadata[j][k] = ptr[i + k]; + metadata[j] = + cs_etm__create_meta_blk(ptr, &i, + CS_ETM_PRIV_MAX, + CS_ETM_NR_PARAMS_V0); /* The traceID is our handle */ - idx = metadata[j][CS_ETM_ETMTRACEIDR]; - i += CS_ETM_PRIV_MAX; + trcidr_idx = CS_ETM_ETMTRACEIDR; + } else if (ptr[i] == __perf_cs_etmv4_magic) { - metadata[j] = zalloc(sizeof(*metadata[j]) * - CS_ETMV4_PRIV_MAX); - if (!metadata[j]) { - err = -ENOMEM; - goto err_free_metadata; - } - for (k = 0; k < CS_ETMV4_PRIV_MAX; k++) - metadata[j][k] = ptr[i + k]; + metadata[j] = + cs_etm__create_meta_blk(ptr, &i, + CS_ETMV4_PRIV_MAX, + CS_ETMV4_NR_PARAMS_V0); /* The traceID is our handle */ - idx = metadata[j][CS_ETMV4_TRCTRACEIDR]; - i += CS_ETMV4_PRIV_MAX; + trcidr_idx = CS_ETMV4_TRCTRACEIDR; + } + + if (!metadata[j]) { + err = -ENOMEM; + goto err_free_metadata; } /* Get an RB node for this CPU */ - inode = intlist__findnew(traceid_list, idx); + inode = intlist__findnew(traceid_list, metadata[j][trcidr_idx]); /* Something went wrong, no need to continue */ if (!inode) { diff --git a/tools/perf/util/cs-etm.h b/tools/perf/util/cs-etm.h index 4ad925d6d799..fffc6b50beb9 100644 --- a/tools/perf/util/cs-etm.h +++ b/tools/perf/util/cs-etm.h @@ -24,16 +24,28 @@ enum { CS_HEADER_VERSION_0_MAX, }; +/* + * Update the version for new format. + * + * New version 1 format adds a param count to the per cpu metadata. + * This allows easy adding of new metadata parameters. + * Requires that new params always added after current ones. + * Also allows client reader to handle file versions that are different by + * checking the number of params in the file vs the number expected. + */ +#define CS_HEADER_CURRENT_VERSION 1 + /* Beginning of header common to both ETMv3 and V4 */ enum { CS_ETM_MAGIC, CS_ETM_CPU, + CS_ETM_NR_PARAMS, }; /* ETMv3/PTM metadata */ enum { /* Dynamic, configurable parameters */ - CS_ETM_ETMCR = CS_ETM_CPU + 1, + CS_ETM_ETMCR = CS_ETM_NR_PARAMS + 1, CS_ETM_ETMTRACEIDR, /* RO, taken from sysFS */ CS_ETM_ETMCCER, @@ -41,10 +53,13 @@ enum { CS_ETM_PRIV_MAX, }; +/* define fixed version 0 length - allow new format reader to read old files. */ +#define CS_ETM_NR_PARAMS_V0 (CS_ETM_ETMIDR - CS_ETM_ETMCR + 1) + /* ETMv4 metadata */ enum { /* Dynamic, configurable parameters */ - CS_ETMV4_TRCCONFIGR = CS_ETM_CPU + 1, + CS_ETMV4_TRCCONFIGR = CS_ETM_NR_PARAMS + 1, CS_ETMV4_TRCTRACEIDR, /* RO, taken from sysFS */ CS_ETMV4_TRCIDR0, @@ -55,6 +70,9 @@ enum { CS_ETMV4_PRIV_MAX, }; +/* define fixed version 0 length - allow new format reader to read old files. */ +#define CS_ETMV4_NR_PARAMS_V0 (CS_ETMV4_TRCAUTHSTATUS - CS_ETMV4_TRCCONFIGR + 1) + /* * ETMv3 exception encoding number: * See Embedded Trace Macrocell spcification (ARM IHI 0014Q) -- 2.17.1

5 years, 8 months

OpenCSD v1.0.0 release.

by Mike Leach

The latest version of OpenCSD has been released. This v1.0.0 release adds in support for ETE - an extended trace protocol, used by ARM PEs that have the FEAT_ETE architectural feature. (See ARM future architecture docs). The documentation 'man' file is added in this release. This release also adds a fix for github issue #33. Note: the protocol update results in additional output packet types, This requires an update to the perf cs-etm-decoder code to handle new enum values, and the makefile to ensure that perf builds with 1.0.0 using this extension. The patch for this can be seen here:- https://lists.linaro.org/pipermail/coresight/2021-January/005496.html Regards Mike -- Mike Leach Principal Engineer, ARM Ltd. Manchester Design Centre. UK

5 years, 8 months

[PATCH] coresight: etm-perf: Add support for PID tracing for kernel at EL2

by Suzuki K Poulose

When the kernel is running at EL2, the PID is stored in CONTEXTIDR_EL2. So, tracing CONTEXTIDR_EL1 doesn't give us the pid of the process. Thus we should trace the VMID with VMIDOPT set to trace CONTEXTIDR_EL2 instead of VMID. Given that we have an existing config option "contextid" and this will be useful for tracing virtual machines (when we get to support virtualization). So instead, this patch adds a new option, contextid_in_vmid as a separate config. Thus on an EL2 kernel, we will have two options available for the perf tool. However, to make it easier for the user to do pid tracing, we add a new format which will default to "contextid" (on EL1 kernel) or "contextid_in_vmid" (on EL2 kernel). So that the user doesn't have to bother which EL the kernel is running. i.e, perf record -e cs_etm/pid/u -- will always do the "pid" tracing, independent of the kernel EL. Also, the perf tool will be updated to automatically select "pid" config instead of the "contextid" for system wide/CPU wide mode. Cc: Mathieu Poirier <mathieu.poirier(a)linaro.org> Cc: Al Grant <al.grant(a)arm.com> Cc: Mike Leach <mike.leach(a)linaro.org> Cc: Leo Yan <leo.yan(a)linaro.org> Signed-off-by: Suzuki K Poulose <suzuki.poulose(a)arm.com> --- Changes since previous version: - Fix build break on 32bit kernel (kernel test robot <lkp(a)intel.com>) --- .../hwtracing/coresight/coresight-etm-perf.c | 18 ++++++++++++++++++ .../hwtracing/coresight/coresight-etm4x-core.c | 9 +++++++++ include/linux/coresight-pmu.h | 11 +++++++---- 3 files changed, 34 insertions(+), 4 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-etm-perf.c b/drivers/hwtracing/coresight/coresight-etm-perf.c index bdc34ca449f7..f13c3a7bbc84 100644 --- a/drivers/hwtracing/coresight/coresight-etm-perf.c +++ b/drivers/hwtracing/coresight/coresight-etm-perf.c @@ -30,14 +30,32 @@ static DEFINE_PER_CPU(struct coresight_device *, csdev_src); /* ETMv3.5/PTM's ETMCR is 'config' */ PMU_FORMAT_ATTR(cycacc, "config:" __stringify(ETM_OPT_CYCACC)); PMU_FORMAT_ATTR(contextid, "config:" __stringify(ETM_OPT_CTXTID)); +PMU_FORMAT_ATTR(contextid_in_vmid, "config:" __stringify(ETM_OPT_CTXTID_IN_VMID)); PMU_FORMAT_ATTR(timestamp, "config:" __stringify(ETM_OPT_TS)); PMU_FORMAT_ATTR(retstack, "config:" __stringify(ETM_OPT_RETSTK)); /* Sink ID - same for all ETMs */ PMU_FORMAT_ATTR(sinkid, "config2:0-31"); +static ssize_t format_attr_pid_show(struct device *dev, + struct device_attribute *attr, + char *page) +{ + int pid_fmt = ETM_OPT_CTXTID; + +#ifdef CONFIG_CORESIGHT_SOURCE_ETM4X + if (is_kernel_in_hyp_mode()) + pid_fmt = ETM_OPT_CTXTID_IN_VMID; +#endif + return sprintf(page, "config:%d\n", pid_fmt); +} + +struct device_attribute format_attr_pid = __ATTR(pid, 0444, format_attr_pid_show, NULL); + static struct attribute *etm_config_formats_attr[] = { &format_attr_cycacc.attr, &format_attr_contextid.attr, + &format_attr_contextid_in_vmid.attr, + &format_attr_pid.attr, &format_attr_timestamp.attr, &format_attr_retstack.attr, &format_attr_sinkid.attr, diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c index b20b6ff17cf6..8b7c7a8b2874 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c @@ -477,6 +477,15 @@ static int etm4_parse_event_config(struct etmv4_drvdata *drvdata, /* bit[6], Context ID tracing bit */ config->cfg |= BIT(ETM4_CFG_BIT_CTXTID); + /* Do not enable VMID tracing if we are not running in EL2 */ + if (attr->config & BIT(ETM_OPT_CTXTID_IN_VMID)) { + if (!is_kernel_in_hyp_mode()) { + ret = -EINVAL; + goto out; + } + config->cfg |= BIT(ETM4_CFG_BIT_VMID) | BIT(ETM4_CFG_BIT_VMID_OPT); + } + /* return stack - enable if selected and supported */ if ((attr->config & BIT(ETM_OPT_RETSTK)) && drvdata->retstack) /* bit[12], Return stack enable bit */ diff --git a/include/linux/coresight-pmu.h b/include/linux/coresight-pmu.h index b0e35eec6499..927c6285ce5d 100644 --- a/include/linux/coresight-pmu.h +++ b/include/linux/coresight-pmu.h @@ -11,16 +11,19 @@ #define CORESIGHT_ETM_PMU_SEED 0x10 /* ETMv3.5/PTM's ETMCR config bit */ -#define ETM_OPT_CYCACC 12 -#define ETM_OPT_CTXTID 14 -#define ETM_OPT_TS 28 -#define ETM_OPT_RETSTK 29 +#define ETM_OPT_CYCACC 12 +#define ETM_OPT_CTXTID 14 +#define ETM_OPT_CTXTID_IN_VMID 15 +#define ETM_OPT_TS 28 +#define ETM_OPT_RETSTK 29 /* ETMv4 CONFIGR programming bits for the ETM OPTs */ #define ETM4_CFG_BIT_CYCACC 4 #define ETM4_CFG_BIT_CTXTID 6 +#define ETM4_CFG_BIT_VMID 7 #define ETM4_CFG_BIT_TS 11 #define ETM4_CFG_BIT_RETSTK 12 +#define ETM4_CFG_BIT_VMID_OPT 15 static inline int coresight_get_trace_id(int cpu) { -- 2.24.1

5 years, 8 months

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