This series adds a feature to ETR-PERF that sync the ETR buffer to perf
periodically. This is really handy when the system wide trace is used
because in this case the perf won't sync during the trace. In a per-thread
setup the traced program might not go to the kernel frequvently enought
to collect trace. Polling helps in both usecases. Can be used with strobing.
Tuning polling period is challanging, I'm working on an additional patch
that adds some metrics to help tune the polling period.
Daniel Kiss (4):
coresight: tmc-etr: Advance buffer pointer in sync buffer.
coresight: tmc-etr: Track perf handler.
coresight: etm-perf: Export etm_event_cpu_path.
coresight: Add ETR-PERF polling.
.../testing/sysfs-bus-coresight-devices-tmc | 8 +
drivers/hwtracing/coresight/Makefile | 2 +-
.../hwtracing/coresight/coresight-etm-perf.c | 10 +-
.../hwtracing/coresight/coresight-etm-perf.h | 1 +
.../coresight/coresight-etr-perf-polling.c | 316 ++++++++++++++++++
.../coresight/coresight-etr-perf-polling.h | 42 +++
.../hwtracing/coresight/coresight-tmc-core.c | 2 +
.../hwtracing/coresight/coresight-tmc-etr.c | 22 +-
drivers/hwtracing/coresight/coresight-tmc.h | 2 +
9 files changed, 401 insertions(+), 4 deletions(-)
create mode 100644 drivers/hwtracing/coresight/coresight-etr-perf-polling.c
create mode 100644 drivers/hwtracing/coresight/coresight-etr-perf-polling.h
--
2.25.1
commit 6f755e85c332 ("coresight: Add helper for inserting synchronization
packets") removed trailing '\0' from barrier_pkt array and updated the
call sites like etb_update_buffer() to have proper checks for barrier_pkt
size before read but missed updating tmc_update_etf_buffer() which still
reads barrier_pkt past the array size resulting in KASAN out-of-bounds
bug. Fix this by adding a check for barrier_pkt size before accessing
like it is done in etb_update_buffer().
BUG: KASAN: global-out-of-bounds in tmc_update_etf_buffer+0x4b8/0x698
Read of size 4 at addr ffffffd05b7d1030 by task perf/2629
Call trace:
dump_backtrace+0x0/0x27c
show_stack+0x20/0x2c
dump_stack+0x11c/0x188
print_address_description+0x3c/0x4a4
__kasan_report+0x140/0x164
kasan_report+0x10/0x18
__asan_report_load4_noabort+0x1c/0x24
tmc_update_etf_buffer+0x4b8/0x698
etm_event_stop+0x248/0x2d8
etm_event_del+0x20/0x2c
event_sched_out+0x214/0x6f0
group_sched_out+0xd0/0x270
ctx_sched_out+0x2ec/0x518
__perf_event_task_sched_out+0x4fc/0xe6c
__schedule+0x1094/0x16a0
preempt_schedule_irq+0x88/0x170
arm64_preempt_schedule_irq+0xf0/0x18c
el1_irq+0xe8/0x180
perf_event_exec+0x4d8/0x56c
setup_new_exec+0x204/0x400
load_elf_binary+0x72c/0x18c0
search_binary_handler+0x13c/0x420
load_script+0x500/0x6c4
search_binary_handler+0x13c/0x420
exec_binprm+0x118/0x654
__do_execve_file+0x77c/0xba4
__arm64_compat_sys_execve+0x98/0xac
el0_svc_common+0x1f8/0x5e0
el0_svc_compat_handler+0x84/0xb0
el0_svc_compat+0x10/0x50
The buggy address belongs to the variable:
barrier_pkt+0x10/0x40
Memory state around the buggy address:
ffffffd05b7d0f00: fa fa fa fa 04 fa fa fa fa fa fa fa 00 00 00 00
ffffffd05b7d0f80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
>ffffffd05b7d1000: 00 00 00 00 00 00 fa fa fa fa fa fa 00 00 00 03
^
ffffffd05b7d1080: fa fa fa fa 00 02 fa fa fa fa fa fa 03 fa fa fa
ffffffd05b7d1100: fa fa fa fa 00 00 00 00 05 fa fa fa fa fa fa fa
==================================================================
Fixes: 6f755e85c332 ("coresight: Add helper for inserting synchronization packets")
Cc: stable(a)vger.kernel.org
Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan(a)codeaurora.org>
---
drivers/hwtracing/coresight/coresight-tmc-etf.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/hwtracing/coresight/coresight-tmc-etf.c b/drivers/hwtracing/coresight/coresight-tmc-etf.c
index 45b85edfc690..cd0fb7bfba68 100644
--- a/drivers/hwtracing/coresight/coresight-tmc-etf.c
+++ b/drivers/hwtracing/coresight/coresight-tmc-etf.c
@@ -530,7 +530,7 @@ static unsigned long tmc_update_etf_buffer(struct coresight_device *csdev,
buf_ptr = buf->data_pages[cur] + offset;
*buf_ptr = readl_relaxed(drvdata->base + TMC_RRD);
- if (lost && *barrier) {
+ if (lost && i < CORESIGHT_BARRIER_PKT_SIZE) {
*buf_ptr = *barrier;
barrier++;
}
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
Changes since v2:
* Fix typo in last commit message
* Add reviewed-by tags from Leo Yan
This patchset applies on top of "[PATCH v3 0/2] perf cs-etm: Set
time on synthesised samples to preserve ordering"
James Clark (3):
perf cs-etm: Move synth_opts initialisation
perf cs-etm: Start reading 'Z' --itrace option
perf cs-etm: Prevent and warn on underflows during timestamp
calculation.
.../perf/util/cs-etm-decoder/cs-etm-decoder.c | 45 ++++++++++++++-----
tools/perf/util/cs-etm.c | 20 +++++----
2 files changed, 46 insertions(+), 19 deletions(-)
--
2.28.0
The conversion tools used during DocBook/LaTeX/html/Markdown->ReST
conversion and some cut-and-pasted text contain some characters that
aren't easily reachable on standard keyboards and/or could cause
troubles when parsed by the documentation build system.
Replace the occurences of the following characters:
- U+00a0 (' '): NO-BREAK SPACE
as it can cause lines being truncated on PDF output
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei(a)kernel.org>
---
Documentation/trace/coresight/coresight-etm4x-reference.rst | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/trace/coresight/coresight-etm4x-reference.rst b/Documentation/trace/coresight/coresight-etm4x-reference.rst
index b64d9a9c79df..d25dfe86af9b 100644
--- a/Documentation/trace/coresight/coresight-etm4x-reference.rst
+++ b/Documentation/trace/coresight/coresight-etm4x-reference.rst
@@ -427,7 +427,7 @@ the ‘TRC’ prefix.
:Syntax:
``echo idx > vmid_idx``
- Where idx < numvmidc
+ Where idx < numvmidc
----
--
2.31.1
This patchset is an alternate solution to the original: "[RFC PATCH]
perf cs-etm: Handle valid-but-zero timestamps". It uses the existing
Z option to --itrace instead of modifying the behaviour of the
cs_etm__etmq_get_timestamp() function.
Using timeless mode is equivalent to ignoring 0 timestamps, as
suggested by Mike and Leo.
It applies on top of "[PATCH v3 0/2] perf cs-etm: Set time on
synthesised samples to preserve ordering"
James Clark (3):
perf cs-etm: Move synth_opts initialisation
perf cs-etm: Start reading 'Z' --itrace option
perf cs-etm: Prevent and warn on underflows during timestamp
calculation.
.../perf/util/cs-etm-decoder/cs-etm-decoder.c | 45 ++++++++++++++-----
tools/perf/util/cs-etm.c | 20 +++++----
2 files changed, 46 insertions(+), 19 deletions(-)
--
2.28.0