The Linaro Toolchain Working Group (TCWG) announces the 2014.07-1 release
of the Linaro GCC 4.9 source package. This is a respin of the 2014.07
release which
contained a backport of a revision that is only relevant to trunk.
Changes in this GCC source package release are:
* Updates to GCC 4.9.1 (svn212635)
* Revert backport of [AArch32] Fix PR target/61154.
Please find the original 2014.07 release notes below:
The Linaro Toolchain Working Group (TCWG) is pleased to announce the 2014.07
stable release of the Linaro GCC 4.9 source package.
Linaro GCC 4.9 2014.07 is the fourth Linaro GCC source package release in the
4.9 series. It is based on FSF GCC 4.9.1+svn212419 and includes performance
improvements and bug fixes.
With the imminent release of ARMv8 hardware and the recent release of the
GCC 4.9 compiler the Linaro TCWG will be focusing on stabilization and
performance of the compiler as the FSF GCC compiler approaches version 4.9.1.
The Linaro TCWG will provide monthly stable[1] source package releases until
FSF GCC 4.9.1 is released. At that point Linaro GCC 4.9 will merge in
FSF GCC 4.9.1 and, release Linaro GCC 4.9.1, and then return to a schedule of
stable quarterly releases and monthly engineering[2] releases.
Interesting changes in this GCC source package release include:
* Updates to GCC 4.9.1-pre+svn212419
* Backport of [AArch32] Wrap long literals in HOST_WIDE_INT_C in
aarch-common.c
* Backport of [AArch32] Rewrite TLC Intrinsics.
* Backport of [AArch32] Remove vzip, vuzp, vtrn builtins and cleanup
* Backport of [AArch32] Use enum name instead of integer value for
PARAM_SCHED_PRESSURE_ALGORITHM.
* Backport of [AArch32] Vectorise bswap*
* Backport of [AArch32] Fix PR/61331
* Backport of [AArch32] Fix PR target/61154
* Backport of [AArch32] Use mov_imm type for movw operations consistently
* Backport of [AArch32] Remove XFmode from ARM backend.
* Backport of [AArch64] Rewrite REV Intrinsics.
* Backport of [AArch64] Implement HARD_REGNO_CALLER_SAVE_MODE.
* Backport of [AArch64] Support tail indirect function call.
* Backport of [AArch64] Fix stack protector for ILP32
* Backport of [AArch64] ILP32 dynamic linker
* Backport of [AArch64] Correct signedness of builtins, remove casts from
arm_neon.h
* Backport of [AArch64] clarify stack layout diagram
* Backport of [AArch64] Implement movmem for the benefit of inline memcpy
* Backport of [AArch64] Fix REG_CFA_RESTORE mode.
* Backport of [AArch64] Fix layout of frame layout code.
* Backport of [AArch64] Fix some reg-to-reg move scheduler types.
* Backport of [AArch64] Implement CRC32 ACLE intrinsics + testsuite.
* Backport of [AArch64] Implement ADD in vector registers for 32-bit scalar
values.
* Backport of [AArch32/AArch64] TARGET_ATOMIC_ASSIGN_EXPAND_FENV AArch64
* Backport of [AArch32/AArch64] Use signed chars in gcc.dg/pr60114.c.
* Backport of [AArch32/AArch64] Rewrite UZP Intrinsics.
* Backport of [AArch32/AArch64] Rewrite TRN Intrinsics.
* Backport of [AArch32/AArch64] Rewrite EXT Intrinsics.
* Backport of [genattrtab] Fix memory corruption, allocate enough memory for all
bypassed reservations
* Backport of Fix PR c/60114
Feedback and Support
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[1] Stable source package releases are defined as releases where the full Linaro
Toolchain validation plan is executed.
[2] Engineering source package releases are defined as releases where the
compiler is only put through unit-testing and full validation is not
performed.
=Progress=
GNU Cauldron
TCWG Sprint [8/10]
* Really helpful to meet (almost) everybody
* Some useful discussion, too
memcpy on A15 - TCWG-390 [1/10]
* Should have let this lie but I had an odd 1/2 day and some data
begging to be looked at
* Turned out I'd fat-fingered the wrong data
* But I gained more evidence suggesting that cortex-strings
benchmark is too noisy
(Non-sprint) meetings/mail etc [1/10]
=Plan=
cbuild2 benchmarking
* Fit what I have into Rob's worldview
* Hopefully convert it into some reviewable patches
Follow up on some notes from Cauldron, sprint
== Progress ==
* GNU Cauldron (4/10)
- GCC+LLVM presentation had some positive reviews
- Discussed sanitizers roadmap
- Very interesting meeting with QuIC
* TCWG Sprint (4/10)
- Mostly about GNU tools
- Team Mission streamlined, looking good
- LLVM roadmap attracted some attention
- We could have some bite-sized work from other team members?
* Release 3.5 testing (TCWG-476 2/10)
- No test regressions
- Spotted some benchmark regressions
- ARMv7 is overall the same on EEMBC
- AArch64 is overall 10% faster on EEMBC
* Weekend working, Friday off
== Plan ==
* Release week!
- Investigate 3.5 performance regressions on v7
- Work around the lack of perf on v8?
- Run SPEC on both v7 and v8 and spot regressions
== Progress ==
* Attend GNU Cauldron.
* TCWG Sprint (8/10)
- Participated in Discussions about TCWG/GNU tools.
- Partcipated in Discussions with ARM mainatiners.
- Discussed about Connect plans.
- LLVM status.
- Attend Backport Demo by Yvan / some Bug fix Activity.
* Friday off traveling back home (2/10)
== Plan ==
* Continue LTO bootstrap issue
* Benchmark Core mark with LTO
* Upstream patch review.
== Issues ==
* Large Memory Model put on hold now.
* Waiting on ARM on Aarch64 SYS V ABI.
== This week ==
* TCWG Sprint (8/10)
- Validation process greatly clarified including roadmap
* Launchpad 1318831 - Invalid unpoisoning of stack redzones on ARM (2/10)
- Finished validating and working thru git review isses with Launchpad
== Next week ==
* Begin neon intrinsic testing
* I will be off on Monday and Tuesday
Hi all concerned:
this test code I given below: AARCH32
[https://email-cn04.huawei.com/owa/14.3.158.1/themes/base/pgrs-sm.gif]
Test function[X][X]
{
volatile unsigned int val0 = 0;
volatile unsigned int val1 = 0;
asm volatile(“mrrc p15, 1, %0, %1, c15” : “=r”(val0), “=r”(val1))
val0 &= ~(1<<6);
val1 &= ~(1<<6);
asm volatile(“mcrr p15, 1, %0, %1, c15” : “=r”(val0), “=r”(val1));
}
After compiling, the result is:
mrrc 15, 1, r2, r3, cr15
str r2, [fp, #-28]
str r3, [fp, #-24]
ldr r3, [fp, #-28]
bic r3, r3, #64;
str r3, [fp, #-28]
ldr r3, [fp, #-24]
bic r3, r3, #64
str r3, [fp, #-24]
mcrr 15, 1, r2, r3, cr15
obviously , it is not what I expect. I have val0 an vl1 two vars, but the compiling result is only one val takes effect.
especia I have to mention is AARCH32.
thanks.
Peter
Hi,
Do you happen to know the answer to the git/svn questions below? Thanks.
-----Original Message-----
From: LDTS [mailto:support@linaro.zendesk.com]
Sent: 25 July 2014 08:43
To: Scott Douglass
Subject: Request received: accessing toolchain source releases - Member user
Thank you for contacting Linaro.
Your request (#927 <https://support.linaro.org/requests/927> ) has been received and is being reviewed by Linaro Developer Technical Support (LDTS). One of our Support agents will be in contact with you as soon as possible. If you would like our agent to contact you via phone, please include your phone number in the comments.
To view your ticket and/or add additional comments, reply to this email or click the link below:
http://support.linaro.org/requests/927
Scott Douglass
Jul 25 16:43
Hi,
I’ve been looking at https://wiki.linaro.org/WorkingGroups/ToolChain (https://wiki.linaro.org/WorkingGroups/ToolChain) and I see the Tree links that give me the git repository and commit id for the current releases of the toolchains (for example, 4.9-2014.06-1 => https://git.linaro.org/toolchain/gcc.git/commit/56d9fd9281e8cef3ea35b7d9ad8… (https://git.linaro.org/toolchain/gcc.git/commit/56d9fd9281e8cef3ea35b7d9ad8…
My first question is: is there a straight-forward way (for example, a tag) to find the commit ids of older (4.9) releases? Or is searching the commit messages the best way?
Also, is there svn access as well or just git access? (Git access is enough, but svn access would be slightly easier for me.)
Also, I has a couple comments on that wiki page:
It says “Pre-built versions that run on generic Linux or Windows are available at http://launchpad.net/linaro-toolchain-binaries.”, but it looks like the that Launchpad project is no longer being maintained (no 4.9 and no recent 4.8). Perhaps the wiki page should be updated (and the Launchpad description updated).
The wiki page also links to https://wiki.linaro.org/Cycles/Next/Release/Status (https://wiki.linaro.org/Cycles/Next/Release/Status) which seems even more out-of-date than the Launchpad binaries; perhaps that link should be updated/removed, too.
Thanks.
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Hi all,
I'm working on booting Linaro LSK 3.10.40 kernel in be8 mode on our Cortex-A9 system.
There is an issue related to VFP instruction. It complain "vstmia" is an undefined instruction.
The VFP is supported in CPU and CONFIG_VFP and CONFIG_VFPv3 are enabled in kernel config.
Are there any patch need to be done for VFP in BE mode?
The booting log show as following:
call sys_access(/init)
Freeing unused kernel memory: 2832K (c0600000 - c08c4000)
kernel_init: try to execute '/init' (ramdisk_execute_command)
en->run_init_process(/init)
init (1): undefined instruction: pc=0000aab8
Code: f00f dff8 2a20 1268 (acec) 108b
Kernel panic - not syncing: Attempted to kill init! exitcode=0x00000004
The disassembly code show the undefined instruction is "vstmia".
armeb-linux-gnueabihf-objdump -D busybox_unstripped > busy.asm
0000aa90 <__sigsetjmp>:
...
aab6: 6812 ldr r2, [r2, #0]
aab8: ecac 8b10 vstmia ip!, {d8-d15}
aabc: f412 7f00 tst.w r2, #512 ; 0x200
The rootfs is busybox 1.22.1 compiled by Linaro BE hard floating toolchain.
https://releases.linaro.org/14.04/components/toolchain/binaries/gcc-linaro-…
Thanks,
Joel
== Progress ==
* On Holiday from 14th to 17th July 2014.
* Travel to Cambridge to attend TCWG Sprint and GNU Tools Cauldron on
Friday 18th July.
== Plan ==
* Attend GNU Tools Cauldron 18th to 20th July.
* Attend TCWG Sprint 21st to 24th July.
* Friday 18th July return back after attending TCWG Sprint and GNU
Tools Cauldron in UK.