== Progress ==
* Fixed aarch64_be-none-elf builds and cross tests. (2/10)
* Forked ancient RSH support in DejaGnu to be more SSH aware. SSH
is now takes 1/4 of the time it used to for each remote execution test
case. (TCWG 512 - 4/10)
* Stabilized new ZSSH protocol in DejaGnu, also much faster than the
current RSH/SSH support. (TCWG 512 - 3/10)
* Meetings and Misc. (1/10)
== Plan ==
* Get my D01 board working finally, since I killed my Odroid U2.
* Review benchmarking patches.
* Do more thorough testing of SSH performance improvements.
== Progress ==
* TCWG-180 Debugging - LTO bootstrap failure in Aarch64 with GCC 4.9. (6/10)
Tried to recompile object files that showed differences in GCC trunk
on amd64 machine.It turned out that GCC make system always builds LTO
files in “gcc” directory and uses prev-gcc/xg++ to build them.
No differences when building stage2 and stage3 objects under same
directory “gcc” in FSF trunk.
Doing the same experiment with gcc 4.9 branch shows failure both in
x86_64 and aarch64.
Communicated the issue to Richard Beiner. Got some feedback on
debugging from Honza and Richard.
Tried passing –save-temps to BOOT_CFLAGS using FSF trunk, getting
assembler errors. Need to come back to this problem after finding root
cause.
Read about LTO passes and wpa (partitioned ) vs non portioned mode.
* Others (2/10)
* Upstream patch review.
* 1-1 Meeting Christophe.
* Misc and internal meeting.
* setup LLVM.
* Friday off (2/10).
== Plan ==
* Continue LTO bootstrap issue.
* Benchmark Core mark with LTO.
* Upstream patch review.
== MISC ==
* National holiday on 15th August .
== Progress ==
TCWG-445 - AArch64 does not generate post-decrement stores.
* Issue resolved with Jiong's prologue/epilogue patch committed to trunk.
* Closed the card.
TCWG-291 - Zero/sign extensions (5/10)
* More review and posted patch based on that which was accepted
* Ran full set of validation (including s390x, aarch64 be, x86 and arm)
* Committed two outstanding patches
* Closed the card.
TCWG-413 - Release benchmarking (2/10)
* Benchmarking or release for a15 and a57
TCWG-468: Sha1 regress (2/10)
* Experimented with back-end patterns. Not much improvement for the
test-case.
- Misc (1/10)
* Looked at gcc bugs and closed old ones.
* Posted test-case patch.
== Plan ==
- Sha1 regressions
- Fixing assigned Bugs
== Issue ==
* None.
== Progress ==
* Refine and send the patch to fix pr61225 in Combine pass for review (2/10).
* Send out the ARM backend patch to keep some constant in register
(TCWG-486, 2/10).
* Rebase and test ccmp related patches (TCWG-488, 2/10).
* R/M toolchain related work (4/10).
== Plans ==
* Ping pending patches.
== Planed leaves ==
* Aug. 18 - 26.
* Benchmarks (CARD-716 3/10)
- Working on Linaro's SPEC scripts for LLVM
- Running SPEC2000 INT/FP (C/C++ only) on both ARMv7 and AArch64
- Re-writing some EEMBC scripts to be more stable
- EEMBC reported some regressions from 3.4.2
- But still same when compared with GCC 4.8 (all in Jira)
* Toolchain (CARD-862 3/10)
- Fixing bugs in the assembler/libc++abi
- http://llvm.org/PR20529
- http://llvm.org/PR20025
- Investigating other bugs in the assembler
- http://llvm.org/PR18926
- http://llvm.org/PR20422
* LLVM 3.5 Release (TCWG-476 1/10)
- Building and testing release candidate 2
* Background (3/10)
- Code review, meetings, discussions, etc.
- Buildbot failures
- Plan for 2014 H2
- Basic LLD AArch64 support landed upstream
== Plan ==
* Take actual holidays
* Work on more assembler fixes
* Finish SPEC runs, hopefully test last release candidate
* Have a look at the bots, libraries, CMake, NEON, etc
== Progress ==
* Upstream work (2/10, CARD-341)
- Patch review
- Submitted a fix for armeb-eabi configurations of binutils
- Tested and removed aarch64 lowlevellock.h
- Tidied up glibc patchwork
* Rewrote src-release as a shell script (4/10, TCWG-487)
- Allows building releases as xz
- 80% less evil than existing makefile
* Booting upstream kernel on Chromebook (2/10)
- Kernel configured and built
- I think I have a plan...
* Off Wednesday (2/10)
== Issues ==
* None
== Plan ==
* Upstream kernel on Chromebook
* malloc app benchmarks
* Potentially glibc 2.20 release week
--
Will Newton
Toolchain Working Group, Linaro
== Progress ==
BeagleBoard and Pandaboard setup for gdb testing [1/10]
* Got both alive and working with minimal os
* Trying ubuntu prebuilt binaries didnt work.
Out of office to get internet fixed and buy accessories for boards. [1/10]
Eid Public Holidays in Pakistan from 29th July till 1st August [8/10]
== Plan ==
BeagleBoard and Pandaboard setup
* Get linux running on both boards
* Run gdb test scripts on both boards
* Compare test results outputs with chromebook and x86
Update and Submit Aarch64 record replay patches.
Resume work on Aarch64 prologue analysis.
== Progress ==
GNU Tools Cauldron
* Some useful corridor meetings with various GNU tools developers
and maintainers.
TCWG Sprint [8/10]
* Got to meet the team and discuss TCWG roadmap.
* Some useful howtos specially back porting and patch review howtos.
* Sprint with ARM and useful discussions on gdb patch review.
Return travel from UK on Friday 25th July.[2/10]
== Plan ==
Get over travel fatigue and resume office.
Get missing components and set up pandaboard and beagle board for gdb testing.
Eid Public Holidays in Pakistan from 29th July till 1st August
== Progress ==
* Installed dmucs on the TCWG build slaves, which works in DejaGnu
to do cpu load based scheduling of executing cross tests
remotely. (TCWG 511 - 4/10)
* Spent some time trying to improve SSH performance for cross
testing by opening the SSH connection via expect, and keeping it
open. (TCWG 512 - 2/10)
* Attended GNU Tools Cauldron and Linaro Sprint. (13/10)
* Worked with Bernie on changes to the benchmarking branch.
* Installed a Jenkins instance on my home server which uses my own
build farm for testing Jenkins/Cbuildv2 changes without screwing
up validation. (TCWG 1378 - 1/10)
- Experimented with some new plugins that might be useful.
(TCWG 1378 - 1/10)
- Added command line options to jenkins.sh so it'll work on
different Jenkins installations.
* Fixed bare metal testing for arm*-none-eabi*. (2/10)
* Fixed several Cbuildv2 bugs in bugzilla (TCWG 1378 - 2/10)
- #167 - tcwgweb.sh not accurate.
- #183 - cbuild2 configure --enable-bootstrap sets
'enable_bootstrap' not 'bootstrap'.
- #249 - cbuild2.sh --help only works after configure is run
* Reviewed and approved patches:
- Add configure option to choose compiler languages
- Enable parallelism by default
- Add support for --march
- Add support for --enable and --disable make_docs in configure
and cbuild2.sh
- lib/checkout.sh: Make checkout() dryrun safe when repodir
doesn't yet exist
- lib/stamp.sh: check_stamp() --force and --dryrun should return 1
- cbuild2.sh: Make --dump a do_ option so it's position doesn't
matter
- lib/make.sh: hello_world() will now return 1 if the compilation
or link fails
* Experiment with Docker to see if it has any advantages over a
chroot, which it seems to. (2/10)
* Refactor building binary tarballs. Now it doesn't run the test
first, it assumes the branch has already been validated. (2/10)
* Fix aach64_be-none-elf builds.
== Plan ==
* Fix current breakage in cbuild2/master.
* Get back to SSH performance improvements (TCWG 512).
* Get my D01 board working finally, since I killed my Odroid U2.
* Work through more cbuildv2 bug reports (TCWG 1378).
== Issues ==
* Sorry, several weeks of status in one activity report, I need to
get back to doing these weekly...
== Progress ==
- Travelling from TCWG sprint (2/10)
- Zero/sign extension elimination (TCWG-291) 2/10
* Posted the modified patch and some discussions. Further testing.
-SHA1 regression (TCWG-468) 4/10
* Looked at IRA's uses of back end cost model. It might be a
limitation (See the notes below). Looking at the test-case from sha1
which also has inline asm whose constraints are causing further issues.
- Misc (2/10)
* Looked at bugs assigned (https://bugs.linaro.org/show_bug.cgi?id=85)
* Set-up LLVM
== Plan ==
- Sha1 regressions
- Fixing assigned Bugs
---------------------------------------------------------------------
In AArch64, some of the integer operations support “w” constraint
(FP_REGS). For example *addsi3_aarch64 pattern supports it. However, not
all of the integer operations supports it. In the cases where it is
supported, all the operands have to be in FP_REGS and it will not work
if we have one operand in FP_REGS and other in GENERAL_REGS.
If there is an allocno whose pseudo register is used only in
*addsi3_aarch64 insns, it will have low cost for register class FP_REGS
(as in the case of a28 below exacted from an example). If the other
pseudo register used in *addsi3_aarch64 (a27 in the example below) is
also used in instructions (rorsi3_insn in the exaple below) that does
not support “w” constraint, there is going to be a cost involved in
moving it from FP_REGS to GENERAL_REGS (or other way)
Currently IRA dosent seems to be considering this dependency in
considering this inter dependency in cost calculation.
