== Progress ==
* EuroLLVM trip [6/10]
* [GlobalISel] AArch64 test-suite and self-host [TCWG-1074][2/10]
- Apple wants to switch the default O0 to GlobalISel for AArch64, so
we need to run tests and gather metrics
- I'm running the test-suite and selfhost with GlobalISel to see how
it performs
* Misc [2/10]
- Mailing list, code reviews, meetings, herding GlobalISel cats
(we're trying to open more communication channels with Apple so we can
unblock progress)
== Plan ==
* Wrap up TCWG-1074
* Learn more TableGen and do more code review
Hello all,
I've been using GCC 4.9.4 for a while now (arm-linux-gnueabi-gcc (Linaro
GCC 4.9-2017.01) 4.9.4), and I found this strange behavior:
In the library header (libm5op.h):
-----
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
void warm_and_run_(int64_t intervals_warm, int64_t intervals_run);
#ifdef __cplusplus
}
#endif
-----
In the library C file (m5op_arm_.c):
-----
#include "stdio.h"
#include <stdlib.h>
#include "libm5op.h"
void warm_and_run_(int64_t intervals_warm, int64_t intervals_run)
{
// Code here using args
}
-----
The code above is in
/home/fernando/work/benchs/SPEC_CPU2006v1.1-aarch64/m5op/ and compiled as a
library with GCC 6.3.1 and is ok:
~/work/toolchains/gcc-linaro-6.3.1-2017.02-x86_64_arm-linux-gnueabi/bin/arm-linux-gnueabi-gcc
-march=armv7-a -mfpu=neon-vfpv4 -mfloat-abi=softfp -O3
-fno-optimize-sibling-calls -c m5op_arm_.c -o m5op_arm_.o
~/work/toolchains/gcc-linaro-6.3.1-2017.02-x86_64_arm-linux-gnueabi/bin/arm-linux-gnueabi-gcc
-c m5op_arm.S -o m5op_arm.o
~/work/toolchains/gcc-linaro-6.3.1-2017.02-x86_64_arm-linux-gnueabi/bin/arm-linux-gnueabi-ar
rcs libm5op32.a m5op_arm_.o m5op_arm.o
The library is used in a source code compiled with the GCC 4.9.4 describe
at the begining.
In the C file:
-----
#include <libm5op.h>
S_regmatch(pTHX_ regnode *prog)
{
warm_and_run_(161, 818);
// Code continues
}
------
This source is compile with:
~/work/toolchains/gcc-linaro-4.9.4-2017.01-x86_64_arm-linux-gnueabi/bin/arm-linux-gnueabi-gcc
-c -o regexec.o -DSPEC_CPU -DNDEBUG -DPERL_CORE -static -marm
-march=armv7-a - mtune=generic-armv7-a -mfpu=neon-vfpv4
-mfloat-abi=softfp -O3 -fno-strict-aliasing -std=gnu89
-I/home/fernando/work/benchs/SPEC_CPU2006v1.1-aarch64/m5op/
-L/home/fernando/work/benchs/ SPEC_CPU2006v1.1-aarch64/m5op/
-DGEM5_ARM32=1 -DSPEC_CPU_ILP32 -DSPEC_CPU_LINUX_IA32 regexec.c
~/work/toolchains/gcc-linaro-4.9.4-2017.01-x86_64_arm-linux-gnueabi/bin/arm-linux-gnueabi-gcc
-static -marm -march=armv7-a -mtune=generic-armv7-a -mfpu=neon-vfpv4
-mfloat- abi=softfp -O3 -fno-strict-aliasing -std=gnu89
-I/home/fernando/work/benchs/SPEC_CPU2006v1.1-aarch64/m5op/
-L/home/fernando/work/benchs/SPEC_CPU2006v1.1-aarch64/m5op/ -DGEM5_ARM32=1
-DSPEC_CPU_ILP32 -DSPEC_CPU_LINUX_IA32 av.o deb.o doio.o doop.o
dump.o globals.o gv.o hv.o locale.o mg.o numeric.o op.o pad.o perl.o
perlapi.o perlio.o perlmain.o perly.o pp.o pp_ctl.o pp_hot.o pp_pack.o
pp_sort.o pp_sys.o regcomp.o regexec.o run.o scope.o sv.o taint.o toke.o
universal.o utf8.o util.o xsutils.o Base64.o Cwd.o Dumper.o HiRes.o IO.o
Peek.o attrs.o poll.o stdio.o DynaLoader.o MD5.o Storable.o Parser.o
specrand.o Hostname.o Opcode.o -lm -lm5op32 -lm5op32 -o
perlbench
Finally, the assembled code of S_regmatch has:
-----
af2d0: e3a000a1 mov r0, #161 ; 0xa1
af2d4: e3001332 movw r1, #818 ; 0x332
af2d8: e58d3018 str r3, [sp, #24]
af2dc: e58d2028 str r2, [sp, #40] ; 0x28
af2e0: fa02615c blx 147858 <warm_and_run_>
-----
So, this means that warm_and_run_ is assumed by GCC 4.9.4 to have 32 bits
arguments, while they are indeed 64 bits. This seems to be a bug for me.
The code in the library is correctly allocating 2*32 bits regs for each
argument.
For now, I'm using int32_t, and I just thought it could be useful to
feedback you guys.
--
Fernando A. Endo, Post-doc
INRIA Rennes-Bretagne Atlantique
France
== Progress ==
* Validation
- finally merged most of work of the past weeks
- main jobs are now using start-container scripts
- helped with new llvm build scripts and jobs
- abe initial config for gcc7: need to investigate a binutils build
problem in a trusty container
- improved tcwg-regression tests, identified a regression for bug-2123
- many validation-related patches to review
* GCC
- reported a regresion upstream
* misc (conf-calls, meetings, emails, ....)
- started discussing benchmarking
== Next ==
* Validation:
- a few patches pending review (to improve reports, debug-ability of
containers, ...)
- work on a new proposal to upgrade our qemu
- probably more cleanup needed in the jobs (slaves, basedir scm option, ...)
- improve tcwg-regression
- boot kernel after build
* Benchmarking: start to contribute
== Progress ==
o Linaro GCC/Validation (6/10)
* Validation/Infra patch reviews
* Upstream monitoring job
* Release automation:
- Reworking tcwg-release.sh
o Misc (4/10)
* Various meetings and discussions.
== Plan ==
o Focusing on release automation and validation
Achievements:
[TCWG-614] Range extension Thunks
- About 3 hours in total of rebasing due to upstream refactoring
- Have finished the non-linkerscript tests and fixed all the bugs
detected by them
- Started the linkerscript tests, no problems found so far
[TLS]
- Some explanation to upstream of how ARM TLS works
- Discovered that upstream have broken TLS global-dynamic for
executables, I have a fix but will need to write a test case.
Plans for next week:
- Euro LLVM Monday, Tuesday
- Continue with TCWG-614
-- Try and link clang (> 30 Mb) to test range thunks on some real programs
-- Aim to get something ready for upstream review by end of week, may
slip to beginning of next week depending on if I find any hard to
debug problems.
~ Progress ~
* TCWG-1050, GDB 8.0 release. [6/10]
** Pushed a fix to AArch64 process record bug on PRFM instruction.
AArch64 native test looks good now.
** Start to look at ARM native test, triage the fails in
watch-bitfields.exp. Test doesn't fail on old Linux kernel, likely
a kernel bug. Further analysis is needed.
** Request reverting Intel btrace python interface before release, as
they are too btrace-specific.
** Fixing a bug about thread_info refcount issue. Testing the patch.
* Discussion on RTOS awareness in debugging. OpenOCD people want GDB
aware more about different RTOSes. [1/10]
* TCWG-1040, SVE patches review, [2/10]
* Misc, [1/10]
~ Plan ~
* Take a look at native ARM testing, and cross testing.
* Post my fix to thread_info refcount issue.
--
Yao Qi
== Progress ==
* [ARM GlobalISel] Use TableGen for inst selector [TCWG-1037] [3/10]
- Got some patches ready but they depend on the TableGen support for
predicates, which has not been committed upstream yet
* [GlobalISel] Use proper calling conv for calls [TCWG-1051] [1/10]
- Patch accepted upstream, will commit next week
* Migrate scripts to Python 3 [TCWG-896] [1/10]
- Started migrating tcwg-release-tools to Python 3, still in progress
* Misc [5/10]
- Mailing lists, code reviews, buildbot monitoring, catching up after Connect
- LLVM social in Stockholm
- Fiddling with the new container for our LLVM buildmasters
== Plan ==
* Commit TCWG-1051, maybe TCWG-1037 too depending on upstream progress
* More GlobalISel code reviews
* TCWG-896
* Out of office for EuroLLVM (24 - 29 March)
[TCWG-614] Range extension Thunks
Worked all week on this. I've got a prototype that is nearly feature
complete. It passes the existing tests when run in a single pass. I'm
now trying to get it to run in multiple passes.
Plans
[TCWG-614] Range extension Thunks
Start adding tests for the new functionality and doubtless spending a
lot of time fixing problems. If I'm lucky I may have something that I
can at least in part send upstream for review by the end of the week.
