Progress:
TCWG-985 PIE on ARM broken
- Now fixed
TCWG-911 Eglibc requires a .ARM.attributes section for dlopen
- Worked around this with a simple hack to retain the first build
attribute section seen. This should suffice for the majority of
use-cases on a host platform using the default compiler. More work is
needed later. Now upstreamed.
TCWG-919 Thunks to undefined symbols
- In upstream review, as expected got some push back, I had hoped to
have resolved this on Thursday and committed today, but no response
last night.
PR31332 X86 pic plt sequences broken
- Worked out a fix, but haven't sent upstream due to needing to spend
quite a bit of time writing tests.
Other:
About 3/4 way of writing up AArch64 Ifunc for possible inclusion in
some public facing documentation.
Got a new blank machine from IT with permission to install linux
myself. Have now built myself a 16.04 machine and got my environment
set up.
Planned absences:
- on holiday for two weeks, back on Tuesday 3rd December
Next year:
- Top priority is long range thunks in lld, followed by an ARM lld build bot.
== Progress ==
* [ARM GlobalISel] Add support for integers < 32 bits wide [TCWG-980] [4/10]
- A number of patches in upstream review
* [ARM] Refactor AddrMode3 [TCWG-989] [1/10]
- Did some preliminary investigations / tinkering for removing a
hack in the representation of LDRH
* Rewrite llvm-projs in Python [TCWG-833] [2/10]
- More refactoring etc
- It is finally done, yay
* Misc [3/10]
- Address review comments on outstanding patches (committed
TCWG-925, still waiting for TCWG-946)
- AArch64 3.9.1 release [TCWG-886]
- Meetings, mailing lists, code reviews
== Plan ==
* [ARM] Refactor AddrMode3 [TCWG-989]
* FOSDEM slides
* Vacation between December 24th and January 9th.
The Linaro Toolchain Working Group (TCWG) is pleased to announce the
2016.12 snapshot of both Linaro GCC 5 and Linaro GCC 6 source
packages.
Linaro GCC 6 monthly snapshot[1] is based on FSF GCC 6.2+svn243594 and
includes performance improvements and bug fixes backported from
mainline GCC. This snapshot contents will be part of the 2017.02
stable[2] quarterly release.
This snapshot tarball is available on:
http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.2-2016.12/
Interesting changes in this GCC source package snapshot include:
* Updates to GCC 6.2+svn243594
* Linaro BZ #2575: backport from trunk r239561, r242555.
* Backport of [Bugfix] [AArch32] PR target/78041
* Backport of [Bugfix] Fix test names for trad.exp tests PR testsuite/78136
* Backport of [Bugfix] PR middle-end/78201
* Backport of [Bugfix] PR tree-optimization/71636
* Backport of [AArch32] Implementing vmaxnmQ_ST and vminnmQ_ST intrinsincs
* Backport of [AArch64] aarch64-*-freebsd* support for gcc
* Backport of [AArch64] Add a SHA1H pattern
* Backport of [AArch64] Align FP callee-saves
* Backport of [AArch64] Improve stack adjustment
* Backport of [AArch64] Improve stack adjustment: add testcase
* Backport of [Cleanup] Fix typo in name
* Backport of [Cleanup] Remove all uses of
TARGET_FLT_EVAL_METHOD_NON_DEFAULT and poison it
* Backport of [Cleanup] Remove redundant TARGET_VFP
* Backport of [Misc] Optimize strchr to strlen (1/2)
* Backport of [Misc] Optimize strchr to strlen (2/2)
* Backport of [Testsuite] [AArch32] Fix failing vminnm/vmaxnm test on ARM
* Backport of [Testsuite] [AArch32] FP16 ARM Alternative format
variants of AAPCS tests
* Backport of [Testsuite] Fix traditional cpp test failure
* Backport of [Testsuite] Report DejaGnu ERROR messages in compare_tests
* Backport of [Testsuite] Report DejaGnu ERROR messages in dg-extract-results
* Backport of [Cleanup] [AArch32] Remove redundant model field from
FPU descriptions
* Backport of [Cleanup] [AArch32] Use VAR_P
* Backport of [Cleanup] [AArch64] aarch64-c.o should depend on TARGET_H
* Backport of [Cleanup] [AArch64] Add a comment before each set of cores
* Backport of [Cleanup] [AArch64] Add function comments to some
prologue/epilogue helpers
* Backport of [Cleanup] [AArch64] Cleanup add expander
Linaro GCC 5 monthly snapshot[1] is based on FSF GCC 5.4+svn243604 and
includes performance improvements and bug fixes backported from
mainline GCC. This snapshot contents will be part of the next
maintenance release.
This snapshot tarball is available on:
http://snapshots.linaro.org/components/toolchain/gcc-linaro/5.4-2016.12/
Interesting changes in this GCC source package snapshot include:
* Updates to GCC 5.4+svn243604
* Linaro BZ #2575: backport from trunk r232812.
Subscribe to the important Linaro mailing lists and join our IRC
channels to stay on top of Linaro development.
** Linaro Toolchain Development "mailing list":
http://lists.linaro.org/mailman/listinfo/linaro-toolchain
** Linaro Toolchain IRC channel on irc.freenode.net at @#linaro-tcwg@
* Bug reports should be filed in bugzilla against GCC product:
http://bugs.linaro.org/enter_bug.cgi?product=GCC
* Interested in commercial support? inquire at "Linaro support":
mailto:support@linaro.org
Progress:
TCWG-829 Ifunc support
- Refactored implementation using synthetic sections upstreamed. Found
out that x86 ifunc was broken and probably hadn't ever worked so I
fixed that while I was there.
PR31332 x86 pic plt sequences broken
- Found out that x86 pic and pie is broken in lld, the implementation
assumes that .got is immediately followed by .got.plt with no gap. As
lld makes no such guarantees it is easy to break with a trivial
example. Raised PR31332 after investigating the root cause. Spent
quite a bit of time on this, even though it is x86 specific, I wanted
to make sure I hadn't broken it.
Fosdem-2017
- Submitted a llvm-devroom talk on lld to Fosdem (post deadline, but
probably still up for consideration)
Plans for this week:
TCWG-985 PIE on ARM broken
- I have a simple fix that should be simple to upstream
TCWG-919 Thunks to undefined symbols
- I have a downstream patch, but there is risk I'll be asked to refactor
TCWG-911 Eglibc requires a .ARM.attributes section for dlopen
- There is a trivial hack to make this work; just use the first ARM
attributes section and throw away the rest. A proper solution to
support ARM attributes merging will take some time.
PR31332 x86 pic plt sequences broken
- I think I can fix this fairly cheaply which while not directly
relevant to ARM, it does give me another easily accessible target to
test on my desk top and has some community benefits.
Ifuncs
- LLD doesn't support taking the address of ifuncs for any
architecture. I don't think that this is common practice, but it is a
latent problem that it might be good to fix now when ifunc is in my
head.
Planned holidays:
19th December till end of the year, back on Tuesday 3rd January
* TCWG-971 (6/10)
- Resolved ICE's in couple of cases.
- Got stuck on the case when split_point->entry_bb has phi whose one
of the arguments is defined
outside split region. This caused ICE for isl_schedule_node.c. For
now, the patch refuses to split
in this case, which "fixes" the ICE. Need to think more about this case.
- Working through other failures with bootstrap :/
* GCC bugs (3/10)
- TCWG-701: Patch iteration based on upstream reviews by Jakub.
* Misc (1/10)
- Meetings
== This Week ==
- TCWG-701
- Holidays till 2nd Jan 2017.
== Progress ==
* [ARM GlobalISel] Use CC support for lowering args/return [TCWG-946] [2/10]
- Committed patch extracting target-independent functionality from
AArch64 GlobalISel
- Submitted patch using that functionality to lower any number of
i32 arguments
- Refactored [ARM GlobalISel] Select add instructions [TCWG-925] to
also use the extracted functionality
* [ARM GlobalISel] Add support for integers < 32 bits wide [TCWG-980] [4/10]
- Support for lowering i8 and i16 arguments / returns through
registers is ready, including the ABI signext / zeroext
- Currently brushing up i1
* Rewrite llvm-projs in Python [TCWG-833] [2/10]
- Refactored patch a bit based on feedback from reviews, still have
some refactoring left to do
- Fixed a bug related to worktree detection
* Misc [2/10]
- Meetings, mailing lists, code reviews
== Plan ==
* Ping / rebase upstream patches
* [ARM GlobalISel] Add support for integers < 32 bits wide [TCWG-980]
- Finish i1 through registers
- Implement i1, i8, i16 through the stack
* Rewrite llvm-projs in Python [TCWG-833]
- Finish refactoring
~ Progress ~
* TCWG-979, Use code cache in prologue analyzer. [3/10]. Done.
Prologue analyser improvement patches are pushed in. Performance
improvement is measured on both ARM and AArch64 with and without
-fstack-protector. Wall time is reduced from 34s to 10s in one case!
* TCWG-984, Handle exception/error in disassembly. [5/10]
Need to fixed it before 7.12.1 release (Jan 2017).
Find other issues during the investigation, and fixed them. PR 20953,
PR 20954, PR 20955. Two opcodes patches are posted to binutils.
Write a unit test for disassembly on memory error. Exposes some
issues in opcodes. Whether upstream needs this unit test depends
on the decision on how to fix foreign frame problem in disassembly.
* TCWG-333, Fix gdb.base/func-ptrs.exp fails in thumb mode. No progress.
* upstream patches review. [1/10]
* Misc, meeting, [1/10]
~ Plan ~
* TCWG-984, Post the RFC and list three approaches fixing this problem.
* TCWG-333
--
Yao Qi
-- Progress --
TCWG-829 IFunc support
I have a downstream implementation of ifunc using synthetic sections
that handles x86_64, ARM and AArch64. I think it may be a bit too
complex to upstream in its current form but I think it is illustrative
enough to post upstream for comment.
TCWG-828 Static TLS support
Implemented using new GOT structure and successfully upstreamed.
Took up an opportunity to get involved with progressing some AArch64
documentation back at ARM.
-- Plans --
Will post current state of TCWG-829 (ifunc) for feedback on whether
the design is right.
- Write more tests for TCWG-829.
- Work on TCWG-911 eglibc insists on .ARM.attributes section for
dlopen to work and TCWG-919 Thunks to undefined symbols for shared
libraries that call back to the application.
- Spend some time reviewing and updating AArch64 documents back at ARM.
