Use traploop's EL0 read of ID_AA64ISAR0_EL1 to check an emulated instruction. The kernel emulates MRS and advances the return PC by four bytes.
Select MRS entries by instruction encoding because page faults also appear as int/iret pairs but return to the same PC. Reuse the common FIFO recorder and pair checker.
For example, an expected int/iret pair is:
int 5cc808 => ffff800080010c00 insn: 00 06 38 d5 ... iret ffff800080012284 => 5cc80c insn: e0 03 9f d6
The entry instruction is MRS X0, ID_AA64ISAR0_EL1. After emulating the read at 0x5cc808, the kernel returns via ERET to the next instruction at 0x5cc80c.
Assisted-by: Codex:gpt-6 Signed-off-by: Leo Yan leo.yan@arm.com --- .../perf/tests/shell/coresight/trap_entry_exit.sh | 24 ++++++++++++++++++++++ 1 file changed, 24 insertions(+)
diff --git a/tools/perf/tests/shell/coresight/trap_entry_exit.sh b/tools/perf/tests/shell/coresight/trap_entry_exit.sh new file mode 100755 index 0000000000000000000000000000000000000000..3ebd4033b247a1a43e0139868972afd41ba905ba --- /dev/null +++ b/tools/perf/tests/shell/coresight/trap_entry_exit.sh @@ -0,0 +1,24 @@ +#!/bin/bash +# SPDX-License-Identifier: GPL-2.0 +# CoreSight emulated instruction entry and exit (exclusive) + +# shellcheck source=../lib/coresight_exception.sh +. "$(dirname "$0")/../lib/coresight_exception.sh" + +test_trap_entry_exit() +{ + # traploop reads ID_AA64ISAR0_EL1 from EL0. The kernel emulates MRS and + # advances the saved PC, so IRET must resume four bytes after the trap. + if ! record_trace traploop 256; then + cat "$tmpdir/record.log" + echo "Failed to record the traploop workload" + return 1 + fi + decode_trace || return 1 + # Page faults also appear as "int", but retry the same PC. Select MRS + # Xt, ID_AA64ISAR0_EL1 by its encoding; the low five bits select Xt. + check_exception_pairs "int.*insn: [01][[:xdigit:]] 06 38 d5" "iret" 4 || return 1 +} + +setup_exception_test || exit $? +test_trap_entry_exit