Re: [PATCH v6 02/13] coresight: etm4x: fix underflow for nrseqstate

On Wed, Apr 22, 2026 at 02:21:52PM +0100, Yeoreum Yun wrote:

TCRSEQEVR<n> is implemented only when TCRIDR5.NUMSEQSTATE is 0b100, in which case n ranges from 0 to 2; otherwise, TCRIDR5.NUMSEQSTATE is 0b000.

Therefore, drvdata->nrseqstate should be checked before entering the loop.

Since TRCSEQEVRn (n=0~2), to avoid confusion, we also need to rename ETM_MAX_SEQ_STATES to ETM_MAX_SEQ_TRANSITIONS and define it as 3:

#define ETM_MAX_SEQ_TRANSITIONS 3

Then we don't allocate 4 items but use only 3 of them.

Thanks, Leo