Changes since v2:
* Rename prev_thread -> prev_packet_thread and prev_el ->
prev_packet_el
* Add a comment about tracking the previous packet's thread
Changes since v1:
* Always assume host kernel when the trace was captured at EL1 (nVHE)
* Fix EL validation to work with ETMv3
* Add a commit to make PID format accessible from struct
cs_etm_auxtrace
======
Some fixes to support an issue reported by Denis Nikitin where decoding
trace that contains different EL1 and EL2 kernels can crash or go into
an infinite loop because the wrong kernel maps are used for the decode.
This still doesn't support distinguishing guest and host userspace,
we'd still have to fix the timestamps and do a bit more work to
correlate that. And I've removed PERF_RECORD_MISC_HYPERVISOR as a
possible outcome of cs_etm__cpu_mode(). As far as I know this could
never have been returned anyway because machine__is_host(machine) was
always true due to session.machines.host being hard coded. And I'm not
sure of the relevance of the difference between PERF_RECORD_MISC_KERNEL
and PERF_RECORD_MISC_HYPERVISOR in this scenario.
The first commit is a tidy up, second fixes a bug that I found when
comparing the exception level and thread of branch records, the third
is the main fix, and the last commit is some extra error checking.
Applies to acme/perf-tools-next (42713dafc)
James Clark (5):
perf cs-etm: Only track threads instead of PID and TIDs
perf cs-etm: Use previous thread for branch sample source IP
perf cs-etm: Make PID format accessible from struct cs_etm_auxtrace
perf cs-etm: Track exception level
perf cs-etm: Add exception level consistency check
.../perf/util/cs-etm-decoder/cs-etm-decoder.c | 33 +-
.../perf/util/cs-etm-decoder/cs-etm-decoder.h | 4 +-
tools/perf/util/cs-etm.c | 282 ++++++++++--------
tools/perf/util/cs-etm.h | 13 +-
4 files changed, 184 insertions(+), 148 deletions(-)
--
2.34.1
On 6/8/23 23:09, Catalin Marinas wrote:
> Hi Anshuman,
>
> On Fri, Jun 02, 2023 at 11:55:38AM +0530, Anshuman Khandual wrote:
>> Changes in V2:
>>
>> - Renamed each individual TRBE register fields as per auto-gen tools
>> - Converted each individual TRBE registers as per auto-gen tools
>> - Added new register fields as per DDI0601 2023-03
>
> Mark had some comments about using Enum for some bitfields. While not
> essential, it would be nice to have those fixed. It's probably easier to
> do an incremental patch fixing those, so please post one (or repost the
> whole series, whatever is easier for you).
Sure, will fold in those suggested changes and re-post the series soon.
On 6/2/23 17:42, Mark Brown wrote:
> On Fri, Jun 02, 2023 at 11:55:52AM +0530, Anshuman Khandual wrote:
>> This converts TRBIDR_EL1 register to automatic generation without
>> causing any functional change.
>
>> +Sysreg TRBIDR_EL1 3 0 9 11 7
>> +Res0 63:12
>> +Field 11:8 EA
>
> EA is another field which looks like it should be an enum, as with the
> others this shouldn't be a blocker and could be done incrementally.
Will fold the following changes in this patch.
--- a/arch/arm64/tools/sysreg
+++ b/arch/arm64/tools/sysreg
@@ -2267,7 +2267,11 @@ EndSysreg
Sysreg TRBIDR_EL1 3 0 9 11 7
Res0 63:12
-Field 11:8 EA
+Enum 11:8 EA
+ 0b0000 NON_DESC
+ 0b0001 IGNORE
+ 0b0010 SERROR
+EndEnum
Res0 7:6
Field 5 F
Field 4 P
>
>> +Res0 7:6
>> +Field 5 F
>> +Field 4 P
>> +Field 3:0 Align
>
> Align arguably too though really it's just encoding the relevant power
> of 2 with the enum coming from the fact that it's limited to at most 2KB
> alignment so a Field may well make more sense.
Can fold the following changes in this patch (if required) unless the Field
looks better than Enum.
--- a/arch/arm64/tools/sysreg
+++ b/arch/arm64/tools/sysreg
@@ -2275,5 +2275,18 @@ EndEnum
Res0 7:6
Field 5 F
Field 4 P
-Field 3:0 Align
+Enum 3:0 Align
+ 0b0000 BYTE
+ 0b0001 HALF_WORD
+ 0b0010 WORD
+ 0b0011 DOUBLE_WORD
+ 0b0100 16_BYTES
+ 0b0101 32_BYTES
+ 0b0110 64_BYTES
+ 0b0111 128_BYTES
+ 0b1000 156_BYTES
+ 0b1001 512_BYTES
+ 0b1010 1_KB
+ 0b1011 2_KB
+EndEnum
EndSysreg
>
> Reviewed-by: Mark Brown <broonie(a)kernel.org>
On 6/2/23 17:35, Mark Brown wrote:
> On Fri, Jun 02, 2023 at 11:55:50AM +0530, Anshuman Khandual wrote:
>
>> +Sysreg TRBMAR_EL1 3 0 9 11 4
>> +Res0 63:12
>> +Field 11:10 PAS
>> +Field 9:8 SH
>> +Field 7:0 Attr
>> +EndSysreg
>
> PAS and SH look like they should be enums, Attr is a bit more complex so
> Field is probably a good fit there. Adding the enum information could
> be done incrementally though so:
Will fold the following changes in this patch.
--- a/arch/arm64/tools/sysreg
+++ b/arch/arm64/tools/sysreg
@@ -2246,8 +2246,17 @@ EndSysreg
Sysreg TRBMAR_EL1 3 0 9 11 4
Res0 63:12
-Field 11:10 PAS
-Field 9:8 SH
+Enum 11:10 PAS
+ 0b00 SECURE
+ 0b01 NON_SECURE
+ 0b10 ROOT
+ 0b11 REALM
+EndEnum
+Enum 9:8 SH
+ 0b00 NON_SHAREABLE
+ 0b10 OUTER_SHAREABLE
+ 0b11 INNER_SHAREABLE
+EndEnum
Field 7:0 Attr
EndSysreg
>
> Reviewed-by: Mark Brown <broonie(a)kernel.org>
James has made significant contributions to the CoreSight subsystem
both with code and reviews. Add James to the Reviewer for the subsystem.
Cc: James Clark <james.clark(a)arm.com>
Signed-off-by: Suzuki K Poulose <suzuki.poulose(a)arm.com>
---
MAINTAINERS | 1 +
1 file changed, 1 insertion(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 250518fc70ff..c01a70ed2a36 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -2097,6 +2097,7 @@ N: digicolor
ARM/CORESIGHT FRAMEWORK AND DRIVERS
M: Suzuki K Poulose <suzuki.poulose(a)arm.com>
R: Mike Leach <mike.leach(a)linaro.org>
+R: James Clark <james.clark(a)arm.com>
R: Leo Yan <leo.yan(a)linaro.org>
L: coresight(a)lists.linaro.org (moderated for non-subscribers)
L: linux-arm-kernel(a)lists.infradead.org (moderated for non-subscribers)
--
2.34.1
Changes since v1:
* Always assume host kernel when the trace was captured at EL1 (nVHE)
* Fix EL validation to work with ETMv3
* Add a commit to make PID format accessible from struct
cs_etm_auxtrace
======
Some fixes to support an issue reported by Denis Nikitin where decoding
trace that contains different EL1 and EL2 kernels can crash or go into
an infinite loop because the wrong kernel maps are used for the decode.
This still doesn't support distinguishing guest and host userspace,
we'd still have to fix the timestamps and do a bit more work to
correlate that. And I've removed PERF_RECORD_MISC_HYPERVISOR as a
possible outcome of cs_etm__cpu_mode(). As far as I know this could
never have been returned anyway because machine__is_host(machine) was
always true due to session.machines.host being hard coded. And I'm not
sure of the relevance of the difference between PERF_RECORD_MISC_KERNEL
and PERF_RECORD_MISC_HYPERVISOR in this scenario.
The first commit is a tidy up, second fixes a bug that I found when
comparing the exception level and thread of branch records, the third
is the main fix, and the last commit is some extra error checking.
Applies to acme/perf-tools (48b1320a67)
James Clark (5):
perf cs-etm: Only track threads instead of PID and TIDs
perf cs-etm: Use previous thread for branch sample source IP
perf cs-etm: Make PID format accessible from struct cs_etm_auxtrace
perf cs-etm: Track exception level
perf cs-etm: Add exception level consistency check
.../perf/util/cs-etm-decoder/cs-etm-decoder.c | 33 +--
.../perf/util/cs-etm-decoder/cs-etm-decoder.h | 4 +-
tools/perf/util/cs-etm.c | 273 ++++++++++--------
tools/perf/util/cs-etm.h | 13 +-
4 files changed, 175 insertions(+), 148 deletions(-)
--
2.34.1
Some fixes to support an issue reported by Denis Nikitin where decoding
trace that contains different EL1 and EL2 kernels can crash or go into
an infinite loop because the wrong kernel maps are used for the decode.
This still doesn't support distinguishing guest and host userspace,
we'd still have to fix the timestamps and do a bit more work to
correlate that. And I've removed PERF_RECORD_MISC_HYPERVISOR as a
possible outcome of cs_etm__cpu_mode(). As far as I know this could
never have been returned anyway because machine__is_host(machine) was
always true due to session.machines.host being hard coded. And I'm not
sure of the relevance of the difference between PERF_RECORD_MISC_KERNEL
and PERF_RECORD_MISC_HYPERVISOR in this scenario.
The first commit is a tidy up, second fixes a bug that I found when
comparing the exception level and thread of branch records, the third
is the main fix, and the last commit is some extra error checking.
Applies to acme/perf-tools (4e111f0cf0)
James Clark (4):
perf cs-etm: Only track threads instead of PID and TIDs
perf cs-etm: Use previous thread for branch sample source IP
perf cs-etm: Track exception level
perf cs-etm: Add exception level consistency check
.../perf/util/cs-etm-decoder/cs-etm-decoder.c | 13 +-
.../perf/util/cs-etm-decoder/cs-etm-decoder.h | 4 +-
tools/perf/util/cs-etm.c | 220 +++++++++---------
tools/perf/util/cs-etm.h | 5 +-
4 files changed, 126 insertions(+), 116 deletions(-)
--
2.34.1
Instead of adding the PIDs forever to the list for the new CPUs, let us detect
a component to be ETMv4 based on the CoreSight CID, DEVTYPE=PE_TRACE and
DEVARCH=ETMv4. This is already done for some of the ETMs. We can extend the PID
matching to match the PIDR2:JEDEC, BIT[3], which must be 1 (RA0) always.
Link: https://lkml.kernel.org/r/20230317030501.1811905-1-anshuman.khandual@arm.com
Cc: Anshuman Khandual <anshuman.khandual(a)arm.com>
Cc: Rob Herring <robh+dt(a)kernel.org>
Cc: frowand.list(a)gmail.com
Cc: linux(a)armlinux.org.uk
Cc: Mike Leach <mike.leach(a)linaro.org>
Signed-off-by: Suzuki K Poulose <suzuki.poulose(a)arm.com>
---
.../coresight/coresight-etm4x-core.c | 5 +++++
drivers/hwtracing/coresight/coresight-priv.h | 19 +++++++++++++++++--
2 files changed, 22 insertions(+), 2 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c
index 4c15fae534f3..8a2e24d5686a 100644
--- a/drivers/hwtracing/coresight/coresight-etm4x-core.c
+++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c
@@ -2260,6 +2260,11 @@ static const struct amba_id etm4_ids[] = {
CS_AMBA_UCI_ID(0x000cc0af, uci_id_etm4),/* Marvell ThunderX2 */
CS_AMBA_UCI_ID(0x000b6d01, uci_id_etm4),/* HiSilicon-Hip08 */
CS_AMBA_UCI_ID(0x000b6d02, uci_id_etm4),/* HiSilicon-Hip09 */
+ /*
+ * Match all PIDs with ETM4 DEVARCH. No need for adding any of the new
+ * CPUs to the list here.
+ */
+ CS_AMBA_MATCH_ALL_UCI(uci_id_etm4),
{},
};
diff --git a/drivers/hwtracing/coresight/coresight-priv.h b/drivers/hwtracing/coresight/coresight-priv.h
index 595ce5862056..72ec36c9232c 100644
--- a/drivers/hwtracing/coresight/coresight-priv.h
+++ b/drivers/hwtracing/coresight/coresight-priv.h
@@ -193,12 +193,27 @@ extern void coresight_remove_cti_ops(void);
}
/* coresight AMBA ID, full UCI structure: id table entry. */
-#define CS_AMBA_UCI_ID(pid, uci_ptr) \
+#define __CS_AMBA_UCI_ID(pid, m, uci_ptr) \
{ \
.id = pid, \
- .mask = 0x000fffff, \
+ .mask = m, \
.data = (void *)uci_ptr \
}
+#define CS_AMBA_UCI_ID(pid, uci) __CS_AMBA_UCI_ID(pid, 0x000fffff, uci)
+/*
+ * PIDR2[JEDEC], BIT(3) must be 1 (Read As One) to indicate that rest of the
+ * PIDR1, PIDR2 DES_* fields follow JEDEC encoding for the designer. Use that
+ * as a match value for blanket matching all devices in the given CoreSight
+ * device type and architecture.
+ */
+#define PIDR2_JEDEC BIT(3)
+#define PID_PIDR2_JEDEC (PIDR2_JEDEC << 16)
+/*
+ * Match all PIDs in a given CoreSight device type and architecture, defined
+ * by the uci.
+ */
+#define CS_AMBA_MATCH_ALL_UCI(uci) \
+ __CS_AMBA_UCI_ID(PID_PIDR2_JEDEC, PID_PIDR2_JEDEC, uci)
/* extract the data value from a UCI structure given amba_id pointer. */
static inline void *coresight_get_uci_data(const struct amba_id *id)
--
2.34.1
On 06/06/2023 16:49, Uwe Kleine-König wrote:
> Hello,
>
> On Thu, May 18, 2023 at 10:16:29PM +0200, Uwe Kleine-König wrote:
>> etm4_remove_dev() returned zero unconditionally. Make it return void
>> instead, which makes it clear in the callers that there is no error to
>> handle. Simplify etm4_remove_platform_dev() accordingly.
>>
>> Signed-off-by: Uwe Kleine-König <u.kleine-koenig(a)pengutronix.de>
>> ---
>> drivers/hwtracing/coresight/coresight-etm4x-core.c | 9 +++------
>
> The changes to this file in the last year were all applied by you, maybe
> I can lure you in accepting this patch, too?
>
Apologies, I have now queued this here :
[1] https://git.kernel.org/coresight/c/c5f231f1a7e1
Suzuki