CoreSight

coresight@lists.linaro.org

5 participants
2642 discussions

by Al Grant

Hi, While running perf on some function-heavy code I noticed the ETM return stack isn't enabled (TRCCONFIGR bit 9). I know that it can easily be enabled with retstack=1, but have we considered making this the default as we move to simplification of perf options? It could lead to more efficient profiles and shouldn't be any more difficult to decode than ETM normally is. Al

6 years, 2 months

[PATCH v1 00/21] coresight: allow to build coresight as modules

by Tingwei Zhang

Allow to build coresight as modules. This gives developers the feasibility to test their code without reboot. This series is based on below two series. - "coresight: allow to build components as modules" https://lkml.org/lkml/2018/6/5/989 - "coresight: make drivers modular" https://lkml.org/lkml/2020/1/17/468 This series adds the support to dynamically remove module when the device in that module is enabled and used by some trace path. It disables all trace paths with that device and release the trace path. Kim Phillips (7): coresight: use IS_ENABLED for CONFIGs that may be modules coresight: allow etm3x to be built as a module coresight: allow etm4x to be built as a module coresight: allow etb to be built as a module coresight: allow tpiu to be built as a module coresight: allow tmc to be built as a module coresight: allow funnel and replicator drivers to be built as modules Mian Yousaf Kaukab (4): coresight: export global symbols coresight: remove multiple init calls from funnel driver coresight: remove multiple init calls from replicator driver coresight: tmc-etr: add function to register catu ops Tingwei Zhang (10): coresight: cpu_debug: add module name in Kconfig coresight: cpu_debug: define MODULE_DEVICE_TABLE coresight: add coresight prefix to barrier_pkt Allow to build coresight-stm as a module, for ease of development. coresight: cti: add function to register cti associate ops coresight: allow cti to be built as a module coresight: allow catu drivers to be built as modules coresight: disable trace path with device being removed coresight: allow the coresight core driver to be built as a module coresight: perf: clean up perf event on device unregister path drivers/hwtracing/coresight/Kconfig | 54 ++++- drivers/hwtracing/coresight/Makefile | 20 +- drivers/hwtracing/coresight/coresight-catu.c | 37 ++- drivers/hwtracing/coresight/coresight-catu.h | 2 - .../{coresight.c => coresight-core.c} | 218 ++++++++++++++++-- .../hwtracing/coresight/coresight-cpu-debug.c | 2 + .../{coresight-cti.c => coresight-cti-core.c} | 46 +++- drivers/hwtracing/coresight/coresight-etb10.c | 22 +- .../hwtracing/coresight/coresight-etm-perf.c | 166 ++++++++++++- .../hwtracing/coresight/coresight-etm-perf.h | 7 +- ...resight-etm3x.c => coresight-etm3x-core.c} | 27 ++- ...resight-etm4x.c => coresight-etm4x-core.c} | 31 ++- .../hwtracing/coresight/coresight-funnel.c | 62 ++++- .../hwtracing/coresight/coresight-platform.c | 1 + drivers/hwtracing/coresight/coresight-priv.h | 28 +-- .../coresight/coresight-replicator.c | 63 ++++- drivers/hwtracing/coresight/coresight-stm.c | 20 +- .../{coresight-tmc.c => coresight-tmc-core.c} | 19 +- .../hwtracing/coresight/coresight-tmc-etf.c | 2 +- .../hwtracing/coresight/coresight-tmc-etr.c | 21 +- drivers/hwtracing/coresight/coresight-tmc.h | 3 + drivers/hwtracing/coresight/coresight-tpiu.c | 19 +- include/linux/coresight.h | 2 +- kernel/events/core.c | 1 + 24 files changed, 796 insertions(+), 77 deletions(-) rename drivers/hwtracing/coresight/{coresight.c => coresight-core.c} (87%) rename drivers/hwtracing/coresight/{coresight-cti.c => coresight-cti-core.c} (95%) rename drivers/hwtracing/coresight/{coresight-etm3x.c => coresight-etm3x-core.c} (97%) rename drivers/hwtracing/coresight/{coresight-etm4x.c => coresight-etm4x-core.c} (98%) rename drivers/hwtracing/coresight/{coresight-tmc.c => coresight-tmc-core.c} (96%) -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project

6 years, 2 months

fedora package

by Jeremy Linton

Hi, As part of the effort to enable perf+coresight on fedora+RHEL, I am packaging up opencsd on fedora. This will make me the package maintainer there. As part of that work there were a couple minor tweaks to the install stanza in the makefile, as well as a couple gcc10 related warning cleanups I will forward here RSN too. If anyone is running fedora the early test packages are here: https://copr.fedorainfracloud.org/coprs/jlinton/opencsd/build/1519164/ or https://koji.fedoraproject.org/koji/taskinfo?taskID=46715425 and the in progress install tweak https://github.com/Linaro/OpenCSD/pull/26 Thanks,

6 years, 2 months

Timestamp generator

by Mathieu Poirier

Good day to all, >From an architecture point of view is it fair to assume there can be only one timestamp generator per system or there can be more, something like one per CPU cluster? Either way, is the current practice expected to continue or there are plans to move to different design standards? Thanks, Mathieu

6 years, 2 months

[RFC PATCH 0/3] CoreSight complex config support; ETM strobing.

by Mike Leach

This patchset introduces initial concepts in CoreSight complex configuration support - the device "feature", which is a method of programming the device to perform a specific function. A built-in feature is provided - the ETM strobing function, which programs the ETM to switch trace on and off in a specific mark / space ratio to effectively sample the program being traced. This feature is essential for the Auto-FDO flow using CoreSight trace. Features are declared as a data table, a set of register, resource and parameter requirements. A feature can then be loaded into a device, when the requirements are validated. Once loaded a feature can be enabled for a specific trace run. A feature appears in the sysfs file for the device, as a directory of form 'name.feat', with parameters 'enable', 'description' and any input parameters that may be used to control the operation. For example the ETM strobing feature provided has parameters of 'window' and 'period' to control the sampling mark / space ratio. The representation in sysfs for the ETMv4 is therefore:- etmX/strobing.feat/ /enable /window /period Future developments will introduce resource management, and allow for the runtime loading of additional features, and the setting of features across an entire CoreSight system. Mike Leach (3): coresight: etmv4: Fix resource selector constant. coresight: etmv4: Counter values not saved on disable. coresight: etmv4: Adds initial complex config with ETM4 strobe feature. drivers/hwtracing/coresight/Makefile | 7 +- .../hwtracing/coresight/coresight-config.c | 380 ++++++++++++++++++ .../hwtracing/coresight/coresight-config.h | 156 +++++++ .../hwtracing/coresight/coresight-etm4x-cfg.c | 325 +++++++++++++++ .../hwtracing/coresight/coresight-etm4x-cfg.h | 29 ++ .../coresight/coresight-etm4x-sysfs.c | 3 + drivers/hwtracing/coresight/coresight-etm4x.c | 24 +- drivers/hwtracing/coresight/coresight-etm4x.h | 4 +- drivers/hwtracing/coresight/coresight.c | 1 + include/linux/coresight.h | 2 + 10 files changed, 925 insertions(+), 6 deletions(-) create mode 100644 drivers/hwtracing/coresight/coresight-config.c create mode 100644 drivers/hwtracing/coresight/coresight-config.h create mode 100644 drivers/hwtracing/coresight/coresight-etm4x-cfg.c create mode 100644 drivers/hwtracing/coresight/coresight-etm4x-cfg.h -- 2.17.1

6 years, 2 months

[PATCH] coresight: etm4x: Fix save/restore during cpu idle

by Suzuki K Poulose

The ETM state save/restore incorrectly reads/writes some of the 64bit registers (e.g, address comparators, vmid/cid comparators etc.) using 32bit accesses. Ensure we use the appropriate width accessors for the registers. Fixes: f188b5e76aae ("coresight: etm4x: Save/restore state across CPU low power states") Cc: Mathieu Poirier <mathieu.poirier(a)linaro.org> Cc: Mike Leach <mike.leach(a)linaro.org> Signed-off-by: Suzuki K Poulose <suzuki.poulose(a)arm.com> --- drivers/hwtracing/coresight/coresight-etm4x.c | 16 ++++++++-------- drivers/hwtracing/coresight/coresight-etm4x.h | 2 +- 2 files changed, 9 insertions(+), 9 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c index 82fc2fab072a..be990457a8ea 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.c +++ b/drivers/hwtracing/coresight/coresight-etm4x.c @@ -1206,8 +1206,8 @@ static int etm4_cpu_save(struct etmv4_drvdata *drvdata) } for (i = 0; i < drvdata->nr_addr_cmp * 2; i++) { - state->trcacvr[i] = readl(drvdata->base + TRCACVRn(i)); - state->trcacatr[i] = readl(drvdata->base + TRCACATRn(i)); + state->trcacvr[i] = readq(drvdata->base + TRCACVRn(i)); + state->trcacatr[i] = readq(drvdata->base + TRCACATRn(i)); } /* @@ -1218,10 +1218,10 @@ static int etm4_cpu_save(struct etmv4_drvdata *drvdata) */ for (i = 0; i < drvdata->numcidc; i++) - state->trccidcvr[i] = readl(drvdata->base + TRCCIDCVRn(i)); + state->trccidcvr[i] = readq(drvdata->base + TRCCIDCVRn(i)); for (i = 0; i < drvdata->numvmidc; i++) - state->trcvmidcvr[i] = readl(drvdata->base + TRCVMIDCVRn(i)); + state->trcvmidcvr[i] = readq(drvdata->base + TRCVMIDCVRn(i)); state->trccidcctlr0 = readl(drvdata->base + TRCCIDCCTLR0); state->trccidcctlr1 = readl(drvdata->base + TRCCIDCCTLR1); @@ -1319,18 +1319,18 @@ static void etm4_cpu_restore(struct etmv4_drvdata *drvdata) } for (i = 0; i < drvdata->nr_addr_cmp * 2; i++) { - writel_relaxed(state->trcacvr[i], + writeq_relaxed(state->trcacvr[i], drvdata->base + TRCACVRn(i)); - writel_relaxed(state->trcacatr[i], + writeq_relaxed(state->trcacatr[i], drvdata->base + TRCACATRn(i)); } for (i = 0; i < drvdata->numcidc; i++) - writel_relaxed(state->trccidcvr[i], + writeq_relaxed(state->trccidcvr[i], drvdata->base + TRCCIDCVRn(i)); for (i = 0; i < drvdata->numvmidc; i++) - writel_relaxed(state->trcvmidcvr[i], + writeq_relaxed(state->trcvmidcvr[i], drvdata->base + TRCVMIDCVRn(i)); writel_relaxed(state->trccidcctlr0, drvdata->base + TRCCIDCCTLR0); diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h index 7da022e87218..b8283e1d6d88 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.h +++ b/drivers/hwtracing/coresight/coresight-etm4x.h @@ -334,7 +334,7 @@ struct etmv4_save_state { u64 trcacvr[ETM_MAX_SINGLE_ADDR_CMP]; u64 trcacatr[ETM_MAX_SINGLE_ADDR_CMP]; u64 trccidcvr[ETMv4_MAX_CTXID_CMP]; - u32 trcvmidcvr[ETM_MAX_VMID_CMP]; + u64 trcvmidcvr[ETM_MAX_VMID_CMP]; u32 trccidcctlr0; u32 trccidcctlr1; u32 trcvmidcctlr0; -- 2.24.1

6 years, 2 months

some problem about using opencsd-perf

by H MJ

Dears, I am beginner of using opencsd-perf to study the coresight. My testing platform is Qcom smart phone (SDM845). I've successful build the opencsed lib and perf-opencsd (both are master branch) https://github.com/Linaro/OpenCSD https://github.com/Linaro/perf-opencsd I can find some devices name like these, ( when executing `ls /sys/bus/coresight/devices/`) ..., coresight-stm, coresight-tmc-etf, coresight-tmc-etr, coresight-ssc-etm0, ... However, when I using the commands, I got the error. 1. perfcsd record -e cs_etm/coresight-tmc-etf/ --per-thread ls ==> event syntax error: 'cs_etm/coresight-tmc-etf/' \___ unknown term 2. perfcsd record -e cs_etm/@coresight-tmc-etf/ --per-thread ls ==> event syntax error: 'cs_etm/coresight-tmc-etf/' \___ parser error I've tried any solutions as many as possible, but I still cannot solve this problem. Does perf-opencsd support the android? Can you help me? Thank you very much. Eric

6 years, 2 months

Fwd: Coresight - help

by Mathieu Poirier

Hi David, I am CC'ing the coresight mailing list as it is the best way to get coresight related support on various issues. I have also included Sai who has worked on coresight on the dragon board 845. Regarding autoFDO, Mike Leach recently posted a patchset [1] that automatically configures autoFDO on a platform. You can either work with that patchset or use a scripted solution that Al Grant and Robert Walker have been using. Thanks, Mathieu [1]. https://lists.linaro.org/pipermail/coresight/2020-June/004078.html ---------- Forwarded message --------- From: David Cunado <David.Cunado(a)arm.com> Date: Mon, 29 Jun 2020 at 05:14 Subject: Coresight - help To: Mathieu Poirier <mathieu.poirier(a)linaro.org>, Dave Rodgman <dave.rodgman(a)arm.com> Cc: bill.fletcher(a)linaro.org <bill.fletcher(a)linaro.org> Hi Mathieu, James King passed me your details as you have had expensive experience with Coresight support in many platforms. One of our OSS teams here at Arm is working with Google to try to get Auto FDO working on DragonBoard 845 – do you know whether Coresight is ‘usable’ on this board and if so, if there are any tips on getting it to work? I’ve CC’ed Dave Rodgman, the Tech Lead for the team, who can provide additional technical details. Thanks! David david cunado | open source software group | Arm tel: +44 1223 404112 | mob: +44 7827 230 654 IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.

6 years, 2 months

[PATCH v5 0/5] Update CoreSight infrastructure to select a default sink.

by Mike Leach

This patchset provides an infrastructure to allow for the automatic selection of a sink during CoreSight tracing operations. Currently starting tracing using perf requires a sink selection on the command line:- sudo ./perf record -e cs_etm/@tmc_etr0/ --per-thread uname -a After this set (and the follow-up perf change set) the infrastructure will be able to select a default sink:- sudo ./perf record -e cs_etm// --per-thread uname -a This matches with the default operation provided with perf and intelpt. Where no sink is specified at the start of a trace session, the CoreSight system will walk the connection graph from the source ETM, to find a suitable sink using the first encountered highest priority device. The CoreSight infrastructure is updated to define sink sub_types to differentiate between sinks with built in buffers (ETB / ETF) - BUFFER type, and those that use system memory (ETR) - SYSMEM - types. SYSMEM types are considered higher priority. When two sinks are found of equal priority, then the closest sink to the source in terms of connection nodes is chosen. The automatic sink selection will also operate if an ETM is enabled using sysfs commands, and no sink is currently enabled. A last_sink attribute is added to trace sources that is set to the value of the sink used when a source is enabled via sysfs. This is set in both default and user enabled sink scenarios. Applies to Linux 5.8-rc1 Tested on Dragonboard DB410c. Changes since v4: 1) Added reviewed-by etc that were missing from previous sets. 2) Added last_sink attribute to source devices. 3) Added documentation patch to update docs for default sinks. 4) Moved comment fix patch into separate misc fixes set. Mike Leach (5): coresight: Add default sink selection to CoreSight base. coresight: tmc: Update sink types for default selection. coresight: etm: perf: Add default sink selection to etm perf. coresight: sysfs: Allow select default sink on source enable. documentation: coresight: Update CoreSight document for default sink. Documentation/trace/coresight/coresight.rst | 48 ++-- .../hwtracing/coresight/coresight-etm-perf.c | 17 +- drivers/hwtracing/coresight/coresight-priv.h | 2 + drivers/hwtracing/coresight/coresight-tmc.c | 3 +- drivers/hwtracing/coresight/coresight.c | 205 +++++++++++++++++- include/linux/coresight.h | 6 + 6 files changed, 261 insertions(+), 20 deletions(-) -- 2.17.1

6 years, 2 months

[PATCH v2] coresight: etmv4: Fix CPU power management setup in probe() function.

by Mike Leach

The current probe() function calls a pair of cpuhp_xxx API functions to setup CPU hotplug handling. The hotplug lock is held for the duration of the two calls and other CPU related code using cpus_read_lock() / cpus_read_unlock() calls. The problem is that on error states, goto: statements bypass the cpus_read_unlock() call. This code has increased in complexity as the driver has developed. This patch introduces a pair of helper functions etm4_pm_setup_cpuslocked() and etm4_pm_clear() which correct the issues above and group the PM code a little better. The two functions etm4_cpu_pm_register() and etm4_cpu_pm_unregister() are dropped as these call cpu_pm_register_notifier() / ..unregister_notifier() dependent on CONFIG_CPU_PM - but this define is used to nop these functions out in the pm headers - so the wrapper functions are superfluous. Fixes: f188b5e76aae ("coresight: etm4x: Save/restore state across CPU low power states") Fixes: e9f5d63f84fe ("hwtracing/coresight-etm4x: Use cpuhp_setup_state_nocalls_cpuslocked()") Fixes: 58eb457be028 ("etm4x: Convert to hotplug state machine") Signed-off-by: Mike Leach <mike.leach(a)linaro.org> --- drivers/hwtracing/coresight/coresight-etm4x.c | 82 ++++++++++++------- 1 file changed, 53 insertions(+), 29 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c index 82fc2fab072a..2d732af8b3e7 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.c +++ b/drivers/hwtracing/coresight/coresight-etm4x.c @@ -1398,18 +1398,57 @@ static struct notifier_block etm4_cpu_pm_nb = { .notifier_call = etm4_cpu_pm_notify, }; -static int etm4_cpu_pm_register(void) +/* Setup PM. Called with cpus locked. Deals with error conditions and counts */ +static int etm4_pm_setup_cpuslocked(void) { - if (IS_ENABLED(CONFIG_CPU_PM)) - return cpu_pm_register_notifier(&etm4_cpu_pm_nb); + int ret; - return 0; + if (etm4_count++) + return 0; + + ret = cpu_pm_register_notifier(&etm4_cpu_pm_nb); + if (ret) + goto reduce_count; + + ret = cpuhp_setup_state_nocalls_cpuslocked(CPUHP_AP_ARM_CORESIGHT_STARTING, + "arm/coresight4:starting", + etm4_starting_cpu, etm4_dying_cpu); + + if (ret) + goto unregister_notifier; + + ret = cpuhp_setup_state_nocalls_cpuslocked(CPUHP_AP_ONLINE_DYN, + "arm/coresight4:online", + etm4_online_cpu, NULL); + + /* HP dyn state ID returned in ret on success */ + if (ret > 0) { + hp_online = ret; + return 0; + } + + /* failed dyn state - remove others */ + cpuhp_remove_state_nocalls_cpuslocked(CPUHP_AP_ARM_CORESIGHT_STARTING); + +unregister_notifier: + cpu_pm_unregister_notifier(&etm4_cpu_pm_nb); + +reduce_count: + --etm4_count; + return ret; } -static void etm4_cpu_pm_unregister(void) +static void etm4_pm_clear(void) { - if (IS_ENABLED(CONFIG_CPU_PM)) - cpu_pm_unregister_notifier(&etm4_cpu_pm_nb); + if (--etm4_count != 0) + return; + + cpu_pm_unregister_notifier(&etm4_cpu_pm_nb); + cpuhp_remove_state_nocalls(CPUHP_AP_ARM_CORESIGHT_STARTING); + if (hp_online) { + cpuhp_remove_state_nocalls(hp_online); + hp_online = 0; + } } static int etm4_probe(struct amba_device *adev, const struct amba_id *id) @@ -1466,24 +1505,15 @@ static int etm4_probe(struct amba_device *adev, const struct amba_id *id) etm4_init_arch_data, drvdata, 1)) dev_err(dev, "ETM arch init failed\n"); - if (!etm4_count++) { - cpuhp_setup_state_nocalls_cpuslocked(CPUHP_AP_ARM_CORESIGHT_STARTING, - "arm/coresight4:starting", - etm4_starting_cpu, etm4_dying_cpu); - ret = cpuhp_setup_state_nocalls_cpuslocked(CPUHP_AP_ONLINE_DYN, - "arm/coresight4:online", - etm4_online_cpu, NULL); - if (ret < 0) - goto err_arch_supported; - hp_online = ret; + ret = etm4_pm_setup_cpuslocked(); + cpus_read_unlock(); - ret = etm4_cpu_pm_register(); - if (ret) - goto err_arch_supported; + /* etm4_pm_setup_cpuslocked() does its own cleanup - exit on error */ + if (ret) { + etmdrvdata[drvdata->cpu] = NULL; + return ret; } - cpus_read_unlock(); - if (etm4_arch_supported(drvdata->arch) == false) { ret = -EINVAL; goto err_arch_supported; @@ -1530,13 +1560,7 @@ static int etm4_probe(struct amba_device *adev, const struct amba_id *id) err_arch_supported: etmdrvdata[drvdata->cpu] = NULL; - if (--etm4_count == 0) { - etm4_cpu_pm_unregister(); - - cpuhp_remove_state_nocalls(CPUHP_AP_ARM_CORESIGHT_STARTING); - if (hp_online) - cpuhp_remove_state_nocalls(hp_online); - } + etm4_pm_clear(); return ret; } -- 2.17.1

6 years, 2 months

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