CoreSight

coresight@lists.linaro.org

7 participants
2474 discussions

Arm TechCon 2019

by Loretta Green

Hi If you are interested to get the list of attendees list of Arm TechCon 2019 with 4,458 contacts The expo will showcase the contacts of Information Technology, Software, Graphics, Software Development, Embedded Technology and Embedded Systems. Email me back so that I can share the best pricing & samples for the list of preview. Best Regards, Loretta Green

6 years, 1 month

[PATCH v4 0/6] coresight: etm4x: save/restore ETMv4 context across CPU low power states

by Andrew Murray

Some hardware will ignore bit TRCPDCR.PU which is used to signal to hardware that power should not be removed from the trace unit. Let's mitigate against this by conditionally saving and restoring the trace unit state when the CPU enters low power states. This patchset introduces a firmware property named 'arm,coresight-needs-save-restore' - when this is present the hardware state will be conditionally saved and restored. A module parameter 'pm_save_enable' is also introduced which can be configured to override the firmware property. The hardware state is only ever saved and restored when a self-hosted coresight is in use. Changes since v3: - Only save/restore when self-hosted is being used and detect this without relying on the coresight registers (which may not be available) - Only allocate memory for etmv4_save_state at probe time when configuration indicates it may be used - Set pm_save_enable param to 0444 such that it is static after boot - Save/restore TRCPDCR - Add missing comments to struct etm4_drvdata documentation - Rebased onto coresight/next (8f1f9857) Changes since v2: - Move the PM notifier block from drvdata to file static - Add section names to document references - Add additional information to commit messages - Remove trcdvcvr and trcdvcmr from saved state and add a comment to describe why - Ensure TRCPDCR_PU is set after restore and add a comment to explain why we bother toggling TRCPDCR_PU on save/restore - Reword the pm_save_enable options and add comments - Miscellaneous style changes - Move device tree binding documentation to its own patch Changes since v1: - Rebased onto coresight/next - Correcly pass bit number rather than BIT macro to coresight_timeout - Abort saving state if a timeout occurs - Fix completely broken pm_notify handling and unregister handler on error - Use state_needs_restore to ensure state is restored only once - Add module parameter description to existing boot_enable parameter and use module_param instead of module_param_named - Add firmware bindings for coresight-needs-save-restore - Rename 'disable_pm_save' to 'pm_save_enable' which allows for disabled, enabled or firmware - Update comment on etm4_os_lock, it incorrectly indicated that the code unlocks the trace registers - Add comments to explain use of OS lock during save/restore - Fix incorrect error description whilst waiting for PM stable - Add WARN_ON_ONCE when cpu isn't as expected during save/restore - Various updates to commit messages Andrew Murray (6): coresight: etm4x: remove superfluous setting of os_unlock coresight: etm4x: use explicit barriers on enable/disable coresight: etm4x: use module_param instead of module_param_named coresight: etm4x: improve clarity of etm4_os_unlock comment coresight: etm4x: save/restore state across CPU low power states dt-bindings: arm: coresight: Add support for coresight-needs-save-restore .../devicetree/bindings/arm/coresight.txt | 3 + drivers/hwtracing/coresight/coresight-etm4x.c | 346 +++++++++++++++++- drivers/hwtracing/coresight/coresight-etm4x.h | 64 ++++ 3 files changed, 406 insertions(+), 7 deletions(-) -- 2.21.0

6 years, 1 month

Configuring TRCCONFIGR

by Jeremy Ng

Hi Mathieu, I will like to ask how I might be able to configure the options in trcconfig driver file, found in /sys/bus/coresight/devices/*.etm/mgmt/ . For example, the trcidr0 denotes that tssize = 64bits (which indicates that timestamps are supported), retstack, cc, bb are also supported. However, my trcconfig file shows that none of the options are activated. In the *.etm driver files, it has the following files in it that I thought might have been linked to trcconfig, or at least be related to activating some of the options that are currently activated: 1. bb_ctrl (obviously bb) 2. cntr_ctrl 3. cyc_threshold (cc?) 4. event_ts (ts) I am hoping that help in activating these options can be provided. On another note, I will also like to ask if there might be example files that I may refer to to using sequencer/resource/events. In the *.etm file, there are seq_event,seq_idx,seq_reset_event,seq_state/res_ctrl, res_idx/event,event_instren,event_ts,event_vinst in the respective order (seq/res/events). I will like to understand how I might use these features to improve my tracing results. As well as understanding the various values I could apply to the mode file. As quoted in sysfs-bus-coresight-devices-etm4x, What: /sys/bus/coresight/devices/<memory_map>.etm/mode Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier(a)linaro.org> Description: (RW) Controls various modes supported by this ETM, for example P0 instruction tracing, branch broadcast, cycle counting and context ID tracing. However it does not explain how that file can control various modes. I have tried toying with this files and it went from useful tracing results to just kernel instruction tracing results. After applying 0x0 to the mode again (which was the default value when i start up my device), I am unable to re-obtain useful trace results and had to resort to re-power my device. Lastly, I understand that nr_ss_cmp meant that my etm can only have 1 single-shot comparator during a trace (correct me if I am wrong). This explains why when I applied 0x3 to addr_idx and set addr_start value, I am unable to set a value for addr_stop. On the other hand,i have 0x4 nr_addr_cmp. However, I do not understand how I might be able to use the other 2 addr comparator (i.e. when addr_idx = 0, I am able to set addr_start and addr_stop, which took up 2 addr_cmp. How then, might I be able to use the other 2 addr_cmp?) My apologies for many amateurish questions. I have been looking at the etm documentation (IHI0064F), particularly on comparators, bb, ts, events, resources but unfortunately unable to connect the dots on how I might be able to use them with the coresight drivers. Yours Sincerely, Jeremy Ng

6 years, 1 month

[PATCH v4 2/2] perf machine: arm/arm64: Improve completeness for kernel address space

by Leo Yan

Arm and arm64 architecture reserve some memory regions prior to the symbol '_stext' and these memory regions later will be used by device module and BPF jit. The current code misses to consider these memory regions thus any address in the regions will be taken as user space mode, but perf cannot find the corresponding dso with the wrong CPU mode so we misses to generate samples for device module and BPF related trace data. This patch parse the link scripts to get the memory size prior to start address and reduce this size from 'machine>->kernel_start', then can get a fixed up kernel start address which contain memory regions for device module and BPF. Finally, machine__get_kernel_start() can reflect more complete kernel memory regions and perf can successfully generate samples. The reason for parsing the link scripts is Arm architecture changes text offset dependent on different platforms, which define multiple text offsets in $kernel/arch/arm/Makefile. This offset is decided when build kernel and the final value is extended in the link script, so we can extract the used value from the link script. We use the same way to parse arm64 link script as well. If fail to find the link script, the pre start memory size is assumed as zero, in this case it has no any change caused with this patch. Below is detailed info for testing this patch: - Install or build LLVM/Clang; - Configure perf with ~/.perfconfig: root@debian:~# cat ~/.perfconfig # this file is auto-generated. [llvm] clang-path = /mnt/build/llvm-build/build/install/bin/clang kbuild-dir = /mnt/linux-kernel/linux-cs-dev/ clang-opt = "-g" dump-obj = true [trace] show_zeros = yes show_duration = no no_inherit = yes show_timestamp = no show_arg_names = no args_alignment = 40 show_prefix = yes - Run 'perf trace' command with eBPF event: root@debian:~# perf trace -e string \ -e $kernel/tools/perf/examples/bpf/augmented_raw_syscalls.c - Read eBPF program memory mapping in kernel: root@debian:~# echo 1 > /proc/sys/net/core/bpf_jit_kallsyms root@debian:~# cat /proc/kallsyms | grep -E "bpf_prog_.+_sys_[enter|exit]" ffff00000008a0d0 t bpf_prog_e470211b846088d5_sys_enter [bpf] ffff00000008c6a4 t bpf_prog_29c7ae234d79bd5c_sys_exit [bpf] - Launch any program which accesses file system frequently so can hit the system calls trace flow with eBPF event; - Capture CoreSight trace data with filtering eBPF program: root@debian:~# perf record -e cs_etm/@tmc_etr0/ \ --filter 'filter 0xffff00000008a0d0/0x800' -a sleep 5s - Decode the eBPF program symbol 'bpf_prog_f173133dc38ccf87_sys_enter': root@debian:~# perf script -F,ip,sym Frame deformatter: Found 4 FSYNCS 0 [unknown] ffff00000008a1ac bpf_prog_e470211b846088d5_sys_enter ffff00000008a250 bpf_prog_e470211b846088d5_sys_enter 0 [unknown] ffff00000008a124 bpf_prog_e470211b846088d5_sys_enter 0 [unknown] ffff00000008a14c bpf_prog_e470211b846088d5_sys_enter ffff00000008a13c bpf_prog_e470211b846088d5_sys_enter ffff00000008a14c bpf_prog_e470211b846088d5_sys_enter 0 [unknown] ffff00000008a180 bpf_prog_e470211b846088d5_sys_enter 0 [unknown] ffff00000008a1ac bpf_prog_e470211b846088d5_sys_enter ffff00000008a190 bpf_prog_e470211b846088d5_sys_enter ffff00000008a1ac bpf_prog_e470211b846088d5_sys_enter ffff00000008a250 bpf_prog_e470211b846088d5_sys_enter 0 [unknown] ffff00000008a124 bpf_prog_e470211b846088d5_sys_enter 0 [unknown] ffff00000008a14c bpf_prog_e470211b846088d5_sys_enter 0 [unknown] ffff00000008a180 bpf_prog_e470211b846088d5_sys_enter [...] Cc: Mathieu Poirier <mathieu.poirier(a)linaro.org> Cc: Alexander Shishkin <alexander.shishkin(a)linux.intel.com> Cc: Jiri Olsa <jolsa(a)redhat.com> Cc: Namhyung Kim <namhyung(a)kernel.org> Cc: Peter Zijlstra <peterz(a)infradead.org> Cc: Suzuki Poulouse <suzuki.poulose(a)arm.com> Cc: coresight(a)lists.linaro.org Cc: linux-arm-kernel(a)lists.infradead.org Signed-off-by: Leo Yan <leo.yan(a)linaro.org> --- tools/perf/Makefile.config | 22 ++++++++++++++++++++++ tools/perf/arch/arm/util/Build | 2 ++ tools/perf/arch/arm/util/machine.c | 17 +++++++++++++++++ tools/perf/arch/arm64/util/Build | 1 + tools/perf/arch/arm64/util/machine.c | 17 +++++++++++++++++ 5 files changed, 59 insertions(+) create mode 100644 tools/perf/arch/arm/util/machine.c create mode 100644 tools/perf/arch/arm64/util/machine.c diff --git a/tools/perf/Makefile.config b/tools/perf/Makefile.config index e4988f49ea79..76e0ad0b4fd2 100644 --- a/tools/perf/Makefile.config +++ b/tools/perf/Makefile.config @@ -51,6 +51,17 @@ endif ifeq ($(SRCARCH),arm) NO_PERF_REGS := 0 LIBUNWIND_LIBS = -lunwind -lunwind-arm + PRE_START_SIZE := 0 + ifneq ($(wildcard $(srctree)/arch/$(SRCARCH)/kernel/vmlinux.lds),) + # Extract info from lds: + # . = ((0xC0000000)) + 0x00208000; + # PRE_START_SIZE := 0x00208000 + PRE_START_SIZE := $(shell egrep ' \. \= ${2}0x[0-9a-fA-F]+${2}' \ + $(srctree)/arch/$(SRCARCH)/kernel/vmlinux.lds | \ + sed -e 's/[(|)|.|=|+|<|;|-]//g' -e 's/ \+/ /g' -e 's/^[ \t]*//' | \ + awk -F' ' '{printf "0x%x", $$2}' 2>/dev/null) + endif + CFLAGS += -DARM_PRE_START_SIZE=$(PRE_START_SIZE) endif ifeq ($(SRCARCH),arm64) @@ -58,6 +69,17 @@ ifeq ($(SRCARCH),arm64) NO_SYSCALL_TABLE := 0 CFLAGS += -I$(OUTPUT)arch/arm64/include/generated LIBUNWIND_LIBS = -lunwind -lunwind-aarch64 + PRE_START_SIZE := 0 + ifneq ($(wildcard $(srctree)/arch/$(SRCARCH)/kernel/vmlinux.lds),) + # Extract info from lds: + # . = ((((((((0xffffffffffffffff)) - (((1)) << (48)) + 1) + (0)) + (0x08000000))) + (0x08000000))) + 0x00080000; + # PRE_START_SIZE := (0x08000000 + 0x08000000 + 0x00080000) = 0x10080000 + PRE_START_SIZE := $(shell egrep ' \. \= ${8}0x[0-9a-fA-F]+${2}' \ + $(srctree)/arch/$(SRCARCH)/kernel/vmlinux.lds | \ + sed -e 's/[(|)|.|=|+|<|;|-]//g' -e 's/ \+/ /g' -e 's/^[ \t]*//' | \ + awk -F' ' '{printf "0x%x", $$6+$$7+$$8}' 2>/dev/null) + endif + CFLAGS += -DARM_PRE_START_SIZE=$(PRE_START_SIZE) endif ifeq ($(SRCARCH),csky) diff --git a/tools/perf/arch/arm/util/Build b/tools/perf/arch/arm/util/Build index 296f0eac5e18..efa6b768218a 100644 --- a/tools/perf/arch/arm/util/Build +++ b/tools/perf/arch/arm/util/Build @@ -1,3 +1,5 @@ +perf-y += machine.o + perf-$(CONFIG_DWARF) += dwarf-regs.o perf-$(CONFIG_LOCAL_LIBUNWIND) += unwind-libunwind.o diff --git a/tools/perf/arch/arm/util/machine.c b/tools/perf/arch/arm/util/machine.c new file mode 100644 index 000000000000..db172894e4ea --- /dev/null +++ b/tools/perf/arch/arm/util/machine.c @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0 +#include <linux/types.h> +#include <linux/string.h> +#include <stdlib.h> + +#include "../../util/machine.h" + +void arch__fix_kernel_text_start(u64 *start) +{ + /* + * On arm, the 16MB virtual memory space prior to 'kernel_start' is + * allocated to device modules, a PMD table if CONFIG_HIGHMEM is + * enabled and a PGD table. To reflect the complete kernel address + * space, compensate the pre-defined regions for kernel start address. + */ + *start = *start - ARM_PRE_START_SIZE; +} diff --git a/tools/perf/arch/arm64/util/Build b/tools/perf/arch/arm64/util/Build index 3cde540d2fcf..8081fb8a7b3d 100644 --- a/tools/perf/arch/arm64/util/Build +++ b/tools/perf/arch/arm64/util/Build @@ -1,4 +1,5 @@ perf-y += header.o +perf-y += machine.o perf-y += sym-handling.o perf-$(CONFIG_DWARF) += dwarf-regs.o perf-$(CONFIG_LOCAL_LIBUNWIND) += unwind-libunwind.o diff --git a/tools/perf/arch/arm64/util/machine.c b/tools/perf/arch/arm64/util/machine.c new file mode 100644 index 000000000000..61058dca8c5a --- /dev/null +++ b/tools/perf/arch/arm64/util/machine.c @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0 +#include <linux/types.h> +#include <linux/string.h> +#include <stdlib.h> + +#include "../../util/machine.h" + +void arch__fix_kernel_text_start(u64 *start) +{ + /* + * On arm64, the root PGD table, device module memory region and + * BPF jit region are prior to 'kernel_start'. To reflect the + * complete kernel address space, compensate these pre-defined + * regions for kernel start address. + */ + *start = *start - ARM_PRE_START_SIZE; +} -- 2.17.1

6 years, 1 month

Re: coresight@lists.linaro.org

by Jeremy Ng

Hi Mike, Thank you for your reply! On Thu, Aug 1, 2019 at 1:09 AM Mike Leach <mike.leach(a)linaro.org> wrote: > > Hi Jeremy, > > The trc_pkt_lister app uses a mapping from core name to determine architecture version and core profile. A73 was not included inthe version of the library you are using, but it has been updated in v0.12.0 released today. > > Thank you for updating me on this information. I have tried it with Cortex-A73 and it works! > > On Thu, 25 Jul 2019 at 10:44, Jeremy Ng <ngyzj95(a)gmail.com> wrote: >> >> Dear Mike, >> >> I will like to ask you for guidance on using openCSD. >> >> I was trying to use and understand trc_pkt_lister from demos >> and notice that snapshot of the device is required >> (hikey960 device is used here). >> >> I have also tried looking at the programmer's guide for >> openCSD but I am confused with what I am required to do. >> >> Nevertheless, I tried running trc_pkt_lister in the hikey960 >> snapshot folder and it gave me this error: >> >> Trace Packet Lister : reading snapshot from path ./ >> Using ETR_0 as trace source >> ss2_dcdtree : 0x0025 (OCSD_ERR_TEST_SS_TO_DECODER) [test snapshot to decode tree conversion error]; Unrecognized Core name Cortex-A73. Cannot evaluate profile or architecture.ss2_dcdtree : 0x0025 (OCSD_ERR_TEST_SS_TO_DECODER) [test snapshot to decode tree conversion error]; Failed to create decoder for source ETM_4. >> ss2_dcdtree : 0x0025 (OCSD_ERR_TEST_SS_TO_DECODER) [test snapshot to decode tree conversion error]; Unrecognized Core name Cortex-A73. Cannot evaluate profile or architecture.ss2_dcdtree : 0x0025 (OCSD_ERR_TEST_SS_TO_DECODER) [test snapshot to decode tree conversion error]; Failed to create decoder for source ETM_5. >> ss2_dcdtree : 0x0025 (OCSD_ERR_TEST_SS_TO_DECODER) [test snapshot to decode tree conversion error]; Unrecognized Core name Cortex-A73. Cannot evaluate profile or architecture.ss2_dcdtree : 0x0025 (OCSD_ERR_TEST_SS_TO_DECODER) [test snapshot to decode tree conversion error]; Failed to create decoder for source ETM_6. >> ss2_dcdtree : 0x0025 (OCSD_ERR_TEST_SS_TO_DECODER) [test snapshot to decode tree conversion error]; Unrecognized Core name Cortex-A73. Cannot evaluate profile or architecture.ss2_dcdtree : 0x0025 (OCSD_ERR_TEST_SS_TO_DECODER) [test snapshot to decode tree conversion error]; Failed to create decoder for source ETM_7. >> Trace Packet Lister : Protocol printer ETMV4I on Trace ID 0x10 >> Trace Packet Lister : Protocol printer ETMV4I on Trace ID 0x12 >> Trace Packet Lister : Protocol printer ETMV4I on Trace ID 0x14 >> Trace Packet Lister : Protocol printer ETMV4I on Trace ID 0x16 >> Trace Packet Lister : Error : Unable to open trace buffer >> >> >> I am not exactly sure if there is a proper software to >> perform snapshots/kernel dump/reading registers values. >> I also thought it worthy to note that the snapshot files >> are made in reference to the juno-uname-002 demo project. >> >> >> On another note, I will like to ask if it is possible >> to use openCSD to decode just the trace binary dumps >> without the need for snapshots. > > > If you write your own application to use the library then you can specify whatever input format you wish to provide the correct data for the library. > > What level of decode are you looking for? If you want to simply convert the trace binaries into simple packet listings like ptmtohuman, then far less information is needed. For a full trace decode however both configuration information and program images are required for decode. > > The snapshots provide a format that manages this information and is easy to use for the library test programs such as trc_pkt_lister. May I inquire how I might go about doing that? I am have gotten a snapshot of my device, thanks to Leo Yan, however, I will like to understand how the information in the snapshot was acquired. Especially the following values: In cpu_0.ini: 1) ``` [regs] PC(size:64)=0xFFFFFFC000081000 SP(size:64)=0 SCTLR_EL1=0x1007 CPSR=0x1C5 ``` How was the value for PC, SP, SPCTLR_EL1 and CPSR acquired? 2) ``` [dump1] file=kernel_dump.bin address=0xFFFFFFC000081000 length=0x00050000 ``` How do I acquire kernel_dump.bin and how was the address and length decided? My apologies for the amateurish questions. Regards, Jeremy > > Regrds > > Mike > > >> >> Any assistance will be appreciated >> >> Cheers, >> Jeremy > > -- > Mike Leach > Principal Engineer, ARM Ltd. > Manchester Design Centre. UK

6 years, 1 month

Release of OpenCSD 0.12.0 and development branch 0.13.0-dev

by Mike Leach

Hi, The OpenCSD library is released today @ version 0.12.0 Key updates include:- i) Correction and enhancement of ETMv4 Exception packets. The ETMv4 exception packet contains a preferred return address. This address can also be a target address for the preceding branch if the exception was taken after a branch but before any instructions at the branch target was taken. This is implied by the ordering of the output generic elements in previous versions of the library - but this version has an explicit flag to indicate when this occurs. The intention here is to make it easier for clients that such as perf that are creating lists of branch source/target pairs to correctly spot this event. The preferred return address can also contain a context element in the circumstances that it is also a target address. This was not being emitted correctly by the library. This has been corrected. ii) Support for trace source captures that come from TPIU - these will include FSYNC bytes that need to be handled by the library. Update to test program and snapshot to demo this. iii) Various minor bugfixes and documentation updates to support the changes above. The OpenCSD dev-0v13v0 branch is created. This contains support not previously available in the library, to allow the processing of ETMv4 Q packets. This feature is still undergoing testing but is being made available should any users have a target that can enable these packets. Support for speculative trace will be made available on this branch in due course. Regards Mike -- Mike Leach Principal Engineer, ARM Ltd. Manchester Design Centre. UK

6 years, 1 month

[PATCH] coresight: acpi: Static funnel support

by Suzuki K Poulose

The ACPI bindings for CoreSight has been updated to add the device id for non-programmable CoreSight funnels (aka static funnels) as of v1.1 [0]. Add the ACPI id for static funnels in the driver. [0] https://static.docs.arm.com/den0067/a/DEN0067_CoreSight_ACPI_1.1.pdf Signed-off-by: Suzuki K Poulose <suzuki.poulose(a)arm.com> --- drivers/hwtracing/coresight/coresight-funnel.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/hwtracing/coresight/coresight-funnel.c b/drivers/hwtracing/coresight/coresight-funnel.c index fa97cb9ab4f9..0c99848a5d69 100644 --- a/drivers/hwtracing/coresight/coresight-funnel.c +++ b/drivers/hwtracing/coresight/coresight-funnel.c @@ -5,6 +5,7 @@ * Description: CoreSight Funnel driver */ +#include <linux/acpi.h> #include <linux/kernel.h> #include <linux/init.h> #include <linux/types.h> @@ -302,11 +303,19 @@ static const struct of_device_id static_funnel_match[] = { {} }; +#ifdef CONFIG_ACPI +static const struct acpi_device_id static_funnel_ids[] = { + {"ARMHC9FE", 0}, + {}, +}; +#endif + static struct platform_driver static_funnel_driver = { .probe = static_funnel_probe, .driver = { .name = "coresight-static-funnel", .of_match_table = static_funnel_match, + .acpi_match_table = ACPI_PTR(static_funnel_ids), .pm = &funnel_dev_pm_ops, .suppress_bind_attrs = true, }, -- 2.21.0

6 years, 1 month

[PATCH v3 0/6] coresight: etm4x: save/restore ETMv4 context across CPU low power states

by Andrew Murray

Some hardware will ignore bit TRCPDCR.PU which is used to signal to hardware that power should not be removed from the trace unit. Let's mitigate against this by conditionally saving and restoring the trace unit state when the CPU enters low power states. This patchset introduces a firmware property named 'arm,coresight-needs-save-restore' - when this is present the hardware state will be conditionally saved and restored. A module parameter 'pm_save_enable' is also introduced which can be configured to override the firmware property. The hardware state is only ever saved and restored when the claim tags indicate that coresight is in use. Changes since v2: - Move the PM notifier block from drvdata to file static - Add section names to document references - Add additional information to commit messages - Remove trcdvcvr and trcdvcmr from saved state and add a comment to describe why - Ensure TRCPDCR_PU is set after restore and add a comment to explain why we bother toggling TRCPDCR_PU on save/restore - Reword the pm_save_enable options and add comments - Miscellaneous style changes - Move device tree binding documentation to its own patch Changes since v1: - Rebased onto coresight/next - Correcly pass bit number rather than BIT macro to coresight_timeout - Abort saving state if a timeout occurs - Fix completely broken pm_notify handling and unregister handler on error - Use state_needs_restore to ensure state is restored only once - Add module parameter description to existing boot_enable parameter and use module_param instead of module_param_named - Add firmware bindings for coresight-needs-save-restore - Rename 'disable_pm_save' to 'pm_save_enable' which allows for disabled, enabled or firmware - Update comment on etm4_os_lock, it incorrectly indicated that the code unlocks the trace registers - Add comments to explain use of OS lock during save/restore - Fix incorrect error description whilst waiting for PM stable - Add WARN_ON_ONCE when cpu isn't as expected during save/restore - Various updates to commit messages Andrew Murray (6): coresight: etm4x: remove superfluous setting of os_unlock coresight: etm4x: use explicit barriers on enable/disable coresight: etm4x: use module_param instead of module_param_named coresight: etm4x: improve clarity of etm4_os_unlock comment coresight: etm4x: save/restore state across CPU low power states dt-bindings: arm: coresight: Add support for coresight-needs-save-restore .../devicetree/bindings/arm/coresight.txt | 3 + drivers/hwtracing/coresight/coresight-etm4x.c | 348 +++++++++++++++++- drivers/hwtracing/coresight/coresight-etm4x.h | 62 ++++ drivers/hwtracing/coresight/coresight.c | 2 +- include/linux/coresight.h | 8 + 5 files changed, 415 insertions(+), 8 deletions(-) -- 2.21.0

6 years, 1 month

Coresight Memory Mapped Addresses in Hikey960

by Jeremy Ng

Dear Leo Yan, I will like to ask if there are any better documentations that detail the memory mapped addresses for Coresight registers in Hikey960. I am currently referring to Chapter 2-9-1 in http://mirror.lemaker.org/HiKey960_SoC_Reference_Manual.pdf. This is all the information about coresight addresses that I could retrieve: 0xEC000000 0xED7FFFFF 24M CSSYS_APB I will like to check if there are any datasheet for hikey960 that is as detailed as that for Juno device (link here: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0515b/CHDIFA… ). This is important to me as I am trying to acquire the device snapshot by using CSAL API. I am not sure if there are other ways to do this since the documentation hasn't been exactly straightforward. The reason for wanting the snapshot is to possibly run openCSD and decode my trace binary files. I have followed the CSAL build documentations and ran `csls` on my hikey960. The following output is seen but it crashed my device soon after: ```bash hikey960:/ # csls ** CSLS: listing CoreSight config... ** CSLS: Using default ROM address 0xEC000000 00EC031000: 2.1 908 00000037 00/0F type= 4 - LINK [FUNNEL: 7 in ports] 00EC032000: 1.1 912 000000A0 00/0F type= 8 - SINK PORT [TPIU] 00EC033000: 1.2 961 00001B40 00/0F type= 7 - SINK BUFFER(ETR r/w size: 4K) [TMC: ETR configuration] 00EC034000: 4.1 906 00040800 00/0F type=10 - CTI 00EC035000: 3.6 963 00010000 00/0F type= 3 - SOURCE SWSTIM(65536) [STM ext ports only, 64-bit, 128 masters] 00EC036000: 2.3 961 00000480 00/0F type= 6 - LINK SINK BUFFER(4K) [TMC: ETF configuration] 00EC037000: type=13 O TIMESTAMP 00EC038000: type=13 O TIMESTAMP ``` I will also like to understand why it might have crashed my device during the execution of csls. Please assist. Yours Sincerely, Jeremy

6 years, 1 month

[PATCH 0/5] coresight: tmc error handling and misc fixes

by Suzuki K Poulose

This series is a collection of fixes and cleanups I gathered from trying to get coresight up on a new platform. The TMC-ETR reports MemErr in the status register if there was an error in in the AXI transaction. So far we have ignored it and assumed that we are running on perfect platforms. Let us add the support for handling the MemErr reports and discard the buffer in such case. Also verify that the ETR can do non-secure transactions on the platform at probe time, in order to avoid presenting the user with a non-useable ETR. Suzuki K Poulose (5): coresight: Fix DEBUG_LOCKS_WARN_ON for uninitialized attribute coresight: funnel: Convert pr_warn to dev_warn for obsolete bindings coresight: etr_buf: Consolidate refcount initialization coresight: tmc-etr: Handle memory errors coresight: tmc-etr: Check if non-secure access is enabled .../hwtracing/coresight/coresight-etm-perf.c | 1 + .../hwtracing/coresight/coresight-funnel.c | 2 +- .../hwtracing/coresight/coresight-tmc-etr.c | 26 +++++++++++-------- drivers/hwtracing/coresight/coresight-tmc.c | 12 +++++++++ drivers/hwtracing/coresight/coresight-tmc.h | 4 +++ 5 files changed, 33 insertions(+), 12 deletions(-) -- 2.21.0

6 years, 1 month

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