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[PATCH 11/53] docs: trace: coresight: coresight-etm4x-reference.rst: avoid using UTF-8 chars

by Mauro Carvalho Chehab

While UTF-8 characters can be used at the Linux documentation, the best is to use them only when ASCII doesn't offer a good replacement. So, replace the occurences of the following UTF-8 characters: - U+00a0 (' '): NO-BREAK SPACE - U+2018 ('‘'): LEFT SINGLE QUOTATION MARK - U+2019 ('’'): RIGHT SINGLE QUOTATION MARK Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei(a)kernel.org> --- .../coresight/coresight-etm4x-reference.rst | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/Documentation/trace/coresight/coresight-etm4x-reference.rst b/Documentation/trace/coresight/coresight-etm4x-reference.rst index b64d9a9c79df..e8ddfc144d9a 100644 --- a/Documentation/trace/coresight/coresight-etm4x-reference.rst +++ b/Documentation/trace/coresight/coresight-etm4x-reference.rst @@ -15,14 +15,14 @@ Root: ``/sys/bus/coresight/devices/etm<N>`` The following paragraphs explain the association between sysfs files and the ETMv4 registers that they effect. Note the register names are given without -the ‘TRC’ prefix. +the 'TRC' prefix. ---- :File: ``mode`` (rw) :Trace Registers: {CONFIGR + others} :Notes: - Bit select trace features. See ‘mode’ section below. Bits + Bit select trace features. See 'mode' section below. Bits in this will cause equivalent programming of trace config and other registers to enable the features requested. @@ -89,7 +89,7 @@ the ‘TRC’ prefix. :Notes: Pair of addresses for a range selected by addr_idx. Include / exclude according to the optional parameter, or if omitted - uses the current ‘mode’ setting. Select comparator range in + uses the current 'mode' setting. Select comparator range in control register. Error if index is odd value. :Depends: ``mode, addr_idx`` @@ -277,7 +277,7 @@ the ‘TRC’ prefix. :Trace Registers: VICTLR{23:20} :Notes: Program non-secure exception level filters. Set / clear NS - exception filter bits. Setting ‘1’ excludes trace from the + exception filter bits. Setting '1' excludes trace from the exception level. :Syntax: @@ -427,7 +427,7 @@ the ‘TRC’ prefix. :Syntax: ``echo idx > vmid_idx`` - Where idx < numvmidc + Where idx < numvmidc ---- @@ -628,7 +628,7 @@ the reset parameter:: -The ‘mode’ sysfs parameter. +The 'mode' sysfs parameter. --------------------------- This is a bitfield selection parameter that sets the overall trace mode for the @@ -696,7 +696,7 @@ Bit assignments shown below:- ETM_MODE_QELEM(val) **description:** - ‘val’ determines level of Q element support enabled if + 'val' determines level of Q element support enabled if implemented by the ETM [IDR0] @@ -780,7 +780,7 @@ Bit assignments shown below:- ---- *Note a)* On startup the ETM is programmed to trace the complete address space -using address range comparator 0. ‘mode’ bits 30 / 31 modify this setting to +using address range comparator 0. 'mode' bits 30 / 31 modify this setting to set EL exclude bits for NS state in either user space (EL0) or kernel space (EL1) in the address range comparator. (the default setting excludes all secure EL, and NS EL2) -- 2.30.2

4 years, 1 month

Re: [PATCH v1 2/2] dt-bindings: arm: add property for coresight component name

by taozha＠codeaurora.org

On 2021-04-16 22:47, Mike Leach wrote: > Hi > > On Fri, 16 Apr 2021 at 15:16, <taozha(a)codeaurora.org> wrote: >> >> On 2021-04-16 19:23, Alexander Shishkin wrote: >> > Tao Zhang <taozha(a)codeaurora.org> writes: >> > >> >> Add property "coresight-name" for coresight component name. This >> >> allows coresight driver to read device name from device entries. >> >> >> >> Signed-off-by: Tao Zhang <taozha(a)codeaurora.org> >> >> --- >> >> Documentation/devicetree/bindings/arm/coresight.txt | 2 ++ >> >> 1 file changed, 2 insertions(+) >> >> >> >> diff --git a/Documentation/devicetree/bindings/arm/coresight.txt >> >> b/Documentation/devicetree/bindings/arm/coresight.txt >> >> index d711676..0e980ce 100644 >> >> --- a/Documentation/devicetree/bindings/arm/coresight.txt >> >> +++ b/Documentation/devicetree/bindings/arm/coresight.txt >> >> @@ -103,6 +103,8 @@ its hardware characteristcs. >> >> powers down the coresight component also powers down and loses its >> >> context. This property is currently only used for the ETM 4.x >> >> driver. >> >> >> >> + * coresight-name: the name of the coresight devices. >> > >> > Which devices? Also, is it a common practice to extend device tree >> > definitions based on arbitrary driver needs, or should there be some >> > sort of a discussion first? >> > >> > Regards, >> > -- >> > Alex >> Through the device tree entries, we can define their own name for any >> coresight device. This design is mainly used to facilitate the unified >> naming of coresight devgies across targets. e.g, without this patch, >> we >> can only see from sysFS there are multiple funnels, but we cannot know >> which funnel it is based on their names from sysFS. After applying >> this >> patch, we can directly know what device it is by observing the device >> name in sysFS. And the common scripts can be developed, since applying >> this patch, the same coresight device can have the same name across >> targets. Each developer or vendor can define the name of each >> coresight >> device according to their preferences and products. >> >> Tao > > 1) I am concerned that this will break the existing protocol which > associates a fixed device type name + number with each device - i.e. > etm0, funnel1 etc. > This naming convention allows for generic common scripts to be > developed - see: > ./tools/perf/tests/shel/test_arm_coresight.sh > This relies on the device type prefixes to iterate across all devices > in a system - and uses the connections links that are present in each > of the devices to determine the topology. > Replacing these with arbitrary names will break existing scripts. > Yes, agree with you. The patch should not break the existing protocol. > 2) Using the current system it is entirely possible to determine which > specific device a given name relates to. > e.g. ls -al /sys/bus/coresight/devices/ > > lrwxrwxrwx 1 root root 0 Apr 14 19:02 cti_cpu0 -> > ../../../devices/platform/soc/858000.cti/cti_cpu0 > lrwxrwxrwx 1 root root 0 Apr 14 19:02 cti_cpu1 -> > ../../../devices/platform/soc/859000.cti/cti_cpu1 > lrwxrwxrwx 1 root root 0 Apr 14 19:02 cti_cpu2 -> > ../../../devices/platform/soc/85a000.cti/cti_cpu2 > lrwxrwxrwx 1 root root 0 Apr 14 19:02 cti_cpu3 -> > ../../../devices/platform/soc/85b000.cti/cti_cpu3 > lrwxrwxrwx 1 root root 0 Apr 14 19:02 cti_sys0 -> > ../../../devices/platform/soc/810000.cti/cti_sys0 > lrwxrwxrwx 1 root root 0 Apr 14 19:02 cti_sys1 -> > ../../../devices/platform/soc/811000.cti/cti_sys1 > lrwxrwxrwx 1 root root 0 Apr 14 19:02 etm0 -> > ../../../devices/platform/soc/85c000.etm/etm0 > lrwxrwxrwx 1 root root 0 Apr 14 19:02 etm1 -> > ../../../devices/platform/soc/85d000.etm/etm1 > lrwxrwxrwx 1 root root 0 Apr 14 19:02 etm2 -> > ../../../devices/platform/soc/85e000.etm/etm2 > lrwxrwxrwx 1 root root 0 Apr 14 19:02 etm3 -> > ../../../devices/platform/soc/85f000.etm/etm3 > lrwxrwxrwx 1 root root 0 Apr 16 14:17 funnel0 -> > ../../../devices/platform/soc/821000.funnel/funnel0 > lrwxrwxrwx 1 root root 0 Apr 16 14:17 funnel1 -> > ../../../devices/platform/soc/841000.funnel/funnel1 > lrwxrwxrwx 1 root root 0 Apr 16 14:17 replicator0 -> > ../../../devices/platform/soc/824000.replicator/replicator0 > lrwxrwxrwx 1 root root 0 Apr 16 14:17 tmc_etf0 -> > ../../../devices/platform/soc/825000.etf/tmc_etf0 > lrwxrwxrwx 1 root root 0 Apr 16 14:17 tmc_etr0 -> > ../../../devices/platform/soc/826000.etr/tmc_etr0 > lrwxrwxrwx 1 root root 0 Apr 16 14:17 tpiu0 -> > ../../../devices/platform/soc/820000.tpiu/tpiu > > Further topology can be determined using the connections sub-directory > in each device:- > > ls -al /sys/bus/coresight/devices/etm0/connections/out\:0 > lrwxrwxrwx 1 root root 0 Apr 16 14:18 > /sys/bus/coresight/devices/etm0/connections/out:0 -> > ../../../841000.funnel/funnel1 > > Using this information it is possible to iterate across the entire > topology of any coresight system. > Yes, these information can iterate across the entire topology of any coresight system. But it cannot quickly identify specific coresight devices across targets. e.g. If there are a lot of cti on one target, we need to identify the cti by its register address. The same function cti may has different register address across targets. This patch allow the same function coresight device has the same name, and it could be operated by scripts easily. > 3) If there is some scripting requirement that cannot be solved with > the information available above - then it would be better to add this > name as an alias rather than a direct replacement. > Therefore any coresight device could have an alias_name entry, that > could be interrogated by a script and used as required. This avoids > breaking any existing scripts using the established naming convention. > Agree with you. Can I use sysfs_create_link to create a kernel link between alias name and coresight device kobject? At the same time, the original coresight device naming method remains unchanged. Thus, the existing protocol will not be broken. Or is there any better suggeston on how to add alias name for coresight device? > 4) Any devicetree attribute should follow the <owner>,<attribute> > naming convention. e.g. arm,some_attribute. > I agree with Alex that it may not be normal practice to add in > attributes in these circumstances - this does not appear to relate to > a specific hardware feature or limitation. You may wish to discuss > this with the device tree maintainers. > > Thanks and Regards > > Mike Sure. I will update this according to your suggestion on patch v2. Best. Tao

4 years, 1 month

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by Elena Miller

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4 years, 1 month

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by Hussein

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4 years, 2 months

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by Ms. Kim

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4 years, 2 months

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4 years, 2 months

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by Darren

4 years, 2 months

[PATCH 0/7] Split Coresight decode by aux records

by James Clark

Hi All, Since my previous RFC, I've fixed --per-thread mode and solved most of the open questions. I've also changed --dump-raw-trace to use the same code path so it's also working now. I think the only open questions are: * General approach * If aux records need to be saved, or if they can be pulled from elsewhere. I've also tested perf inject which is now working with troublesome files. Thanks James James Clark (7): perf cs-etm: Split up etm queue setup function perf cs-etm: Only search timestamp in current sample's queue. perf cs-etm: Save aux records in each etm queue perf cs-etm: don't process queues until cs_etm__flush_events perf cs-etm: split decode by aux records. perf cs-etm: Use existing decode code path for --dump-raw-trace perf cs-etm: Suppress printing when resetting decoder .../perf/util/cs-etm-decoder/cs-etm-decoder.c | 10 +- tools/perf/util/cs-etm.c | 300 ++++++++++-------- 2 files changed, 168 insertions(+), 142 deletions(-) -- 2.28.0

4 years, 2 months

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4 years, 2 months

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4 years, 2 months

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