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This series enables future IP trace features Embedded Trace Extension
(ETE) and Trace Buffer Extension (TRBE). This series applies on
v5.12-rc4 + some patches queued. A standalone tree is also available here [0].
The queued patches (almost there) are included in this posting for
the sake of constructing a tree from the posting.
ETE is the PE (CPU) trace unit for CPUs, implementing future
architecture extensions. ETE overlaps with the ETMv4 architecture, with
additions to support the newer architecture features and some restrictions
on the supported features w.r.t ETMv4. The ETE support is added by extending
the ETMv4 driver to recognise the ETE and handle the features as exposed by
the TRCIDRx registers. ETE only supports system instructions access from the
host CPU. The ETE could be integrated with a TRBE (see below), or with
the legacy CoreSight trace bus (e.g, ETRs). Thus the ETE follows same
firmware description as the ETMs and requires a node per instance.
Trace Buffer Extensions (TRBE) implements a per CPU trace buffer, which
is accessible via the system registers and can be combined with the ETE to
provide a 1x1 configuration of source & sink. TRBE is being represented
here as a CoreSight sink. Primary reason is that the ETE source could
work with other traditional CoreSight sink devices. As TRBE captures the
trace data which is produced by ETE, it cannot work alone.
TRBE representation here have some distinct deviations from a
traditional CoreSight sink device. Coresight path between ETE and TRBE are
not built during boot looking at respective DT or ACPI entries.
Unlike traditional sinks, TRBE can generate interrupts to signal
including many other things, buffer got filled. The interrupt is a PPI and
should be communicated from the platform. DT or ACPI entry representing TRBE
should have the PPI number for a given platform. During perf session, the
TRBE IRQ handler should capture trace for perf auxiliary buffer before restarting
it back. System registers being used here to configure ETE and TRBE could
be referred in the link below.
https://developer.arm.com/docs/ddi0601/g/aarch64-system-registers.
[0] https://gitlab.arm.com/linux-arm/linux-skp/-/tree/coresight/ete/v5/
Changes since V4:
https://lkml.kernel.org/r/20210225193543.2920532-1-suzuki.poulose@arm.com
- Split the documentation patches from the TRBE driver
- Drop the patches already queued for v5.12.
- Mark the buffer TRUNCATED in case of a WRAP event
- Fix error code for vmap failure
- Fix build break on arm32 for per-cpu sink patch
- Address comments on ETE dts bindings.
- Make ete_sysreg_read/write static (kernel test robot)
- Merged ete sysreg definition patch with ete support, to avoid
a "defined but unused warning" on build in part of the series.
- Add new bindings to MAINTAINERS
Changes since V3:
https://lore.kernel.org/linux-arm-kernel/1611737738-1493-1-git-send-email-a…
- ETE and TRBE changes have been captured in the respective patches
- Better support for nVHE
- Re-ordered and splitted the patches to keep the changes separate
for the generic/arm64 tree from CoreSight driver specific changes.
- Fixes for KVM handling of Trace/SPE
Changes since V2:
https://lore.kernel.org/linux-arm-kernel/1610511498-4058-1-git-send-email-a…
- Rebased on coresight/next
- Changed DT bindings for ETE
- Included additional patches for arm64 nvhe, perf aux buffer flags etc
- TRBE changes have been captured in the respective patches
Changes since V1:
https://lore.kernel.org/linux-arm-kernel/1608717823-18387-1-git-send-email-…
- Converted both ETE and TRBE DT bindings into Yaml
- TRBE changes have been captured in the respective patches
Changes since RFC:
- There are not much ETE changes from Suzuki apart from splitting of the
ETE DTS patch
- TRBE changes have been captured in the respective patches
RFC:
https://lore.kernel.org/linux-arm-kernel/1605012309-24812-1-git-send-email-…
Cc: Will Deacon <will(a)kernel.org>
Cc: Marc Zyngier <maz(a)kernel.org>
Cc: Peter Zilstra <peterz(a)infradead.org>
Cc: Mathieu Poirier <mathieu.poirier(a)linaro.org>
Cc: Suzuki K Poulose <suzuki.poulose(a)arm.com>
Cc: Mike Leach <mike.leach(a)linaro.org>
Cc: Linu Cherian <lcherian(a)marvell.com>
Cc: coresight(a)lists.linaro.org
Cc: linux-arm-kernel(a)lists.infradead.org
Cc: linux-kernel(a)vger.kernel.org
Anshuman Khandual (5):
arm64: Add TRBE definitions
coresight: core: Add support for dedicated percpu sinks
coresight: sink: Add TRBE driver
Documentation: coresight: trbe: Sysfs ABI description
Documentation: trace: Add documentation for TRBE
Suzuki K Poulose (14):
[Queued] kvm: arm64: Hide system instruction access to Trace registers
[Queued] kvm: arm64: Disable guest access to trace filter controls
perf: aux: Add flags for the buffer format
perf: aux: Add CoreSight PMU buffer formats
arm64: Add support for trace synchronization barrier
arm64: kvm: Enable access to TRBE support for host
coresight: etm4x: Move ETM to prohibited region for disable
coresight: etm-perf: Allow an event to use different sinks
coresight: Do not scan for graph if none is present
coresight: etm4x: Add support for PE OS lock
coresight: ete: Add support for ETE tracing
dts: bindings: Document device tree bindings for ETE
coresight: etm-perf: Handle stale output handles
dts: bindings: Document device tree bindings for Arm TRBE
.../testing/sysfs-bus-coresight-devices-trbe | 14 +
.../devicetree/bindings/arm/ete.yaml | 75 ++
.../devicetree/bindings/arm/trbe.yaml | 49 +
.../trace/coresight/coresight-trbe.rst | 38 +
MAINTAINERS | 2 +
arch/arm64/include/asm/barrier.h | 1 +
arch/arm64/include/asm/el2_setup.h | 13 +
arch/arm64/include/asm/kvm_arm.h | 3 +
arch/arm64/include/asm/kvm_host.h | 2 +
arch/arm64/include/asm/sysreg.h | 50 +
arch/arm64/kernel/cpufeature.c | 1 -
arch/arm64/kernel/hyp-stub.S | 3 +-
arch/arm64/kvm/debug.c | 6 +-
arch/arm64/kvm/hyp/nvhe/debug-sr.c | 42 +
arch/arm64/kvm/hyp/nvhe/switch.c | 1 +
drivers/hwtracing/coresight/Kconfig | 24 +-
drivers/hwtracing/coresight/Makefile | 1 +
drivers/hwtracing/coresight/coresight-core.c | 29 +-
.../hwtracing/coresight/coresight-etm-perf.c | 119 +-
.../coresight/coresight-etm4x-core.c | 161 ++-
.../coresight/coresight-etm4x-sysfs.c | 19 +-
drivers/hwtracing/coresight/coresight-etm4x.h | 83 +-
.../hwtracing/coresight/coresight-platform.c | 6 +
drivers/hwtracing/coresight/coresight-priv.h | 3 +
drivers/hwtracing/coresight/coresight-trbe.c | 1157 +++++++++++++++++
drivers/hwtracing/coresight/coresight-trbe.h | 152 +++
include/linux/coresight.h | 13 +
include/uapi/linux/perf_event.h | 13 +-
28 files changed, 2016 insertions(+), 64 deletions(-)
create mode 100644 Documentation/ABI/testing/sysfs-bus-coresight-devices-trbe
create mode 100644 Documentation/devicetree/bindings/arm/ete.yaml
create mode 100644 Documentation/devicetree/bindings/arm/trbe.yaml
create mode 100644 Documentation/trace/coresight/coresight-trbe.rst
create mode 100644 drivers/hwtracing/coresight/coresight-trbe.c
create mode 100644 drivers/hwtracing/coresight/coresight-trbe.h
--
2.24.1
On 2021-04-16 19:23, Alexander Shishkin wrote:
> Tao Zhang <taozha(a)codeaurora.org> writes:
>
>> Add property "coresight-name" for coresight component name. This
>> allows coresight driver to read device name from device entries.
>>
>> Signed-off-by: Tao Zhang <taozha(a)codeaurora.org>
>> ---
>> Documentation/devicetree/bindings/arm/coresight.txt | 2 ++
>> 1 file changed, 2 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/arm/coresight.txt
>> b/Documentation/devicetree/bindings/arm/coresight.txt
>> index d711676..0e980ce 100644
>> --- a/Documentation/devicetree/bindings/arm/coresight.txt
>> +++ b/Documentation/devicetree/bindings/arm/coresight.txt
>> @@ -103,6 +103,8 @@ its hardware characteristcs.
>> powers down the coresight component also powers down and loses its
>> context. This property is currently only used for the ETM 4.x
>> driver.
>>
>> + * coresight-name: the name of the coresight devices.
>
> Which devices? Also, is it a common practice to extend device tree
> definitions based on arbitrary driver needs, or should there be some
> sort of a discussion first?
>
> Regards,
> --
> Alex
Through the device tree entries, we can define their own name for any
coresight device. This design is mainly used to facilitate the unified
naming of coresight devgies across targets. e.g, without this patch, we
can only see from sysFS there are multiple funnels, but we cannot know
which funnel it is based on their names from sysFS. After applying this
patch, we can directly know what device it is by observing the device
name in sysFS. And the common scripts can be developed, since applying
this patch, the same coresight device can have the same name across
targets. Each developer or vendor can define the name of each coresight
device according to their preferences and products.
Tao
*** BLURB HERE ***
Tao Zhang (2):
coresight: Add support for device names
dt-bindings: arm: add property for coresight component name
Documentation/devicetree/bindings/arm/coresight.txt | 2 ++
drivers/hwtracing/coresight/coresight-core.c | 6 ++++++
2 files changed, 8 insertions(+)
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
Current coresight implementation only supports enabling source
ETMs or STM. This patch adds support to enable more kinds of
coresight source to sink paths. We build a path from source to
sink when any source is enabled and store it in a list. When the
source is disabled, we fetch the corresponding path from the list
and decrement the refcount on each device in the path. The device
is disabled if the refcount reaches zero. Don't store path to
coresight data structure of source to avoid unnecessary change to
ABI.
Since some targets may have coresight sources other than STM and
ETMs, we need to add this change to support these coresight
devices.
Signed-off-by: Satyajit Desai <sadesai(a)codeaurora.org>
Signed-off-by: Rama Aparna Mallavarapu <aparnam(a)codeaurora.org>
Signed-off-by: Mulu He <muluhe(a)codeaurora.org>
Signed-off-by: Tingwei Zhang <tingwei(a)codeaurora.org>
Signed-off-by: Tao Zhang <taozha(a)codeaurora.org>
---
drivers/hwtracing/coresight/coresight-core.c | 101 +++++++++++++++------------
1 file changed, 56 insertions(+), 45 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-core.c b/drivers/hwtracing/coresight/coresight-core.c
index 4ba801d..7dfadb6 100644
--- a/drivers/hwtracing/coresight/coresight-core.c
+++ b/drivers/hwtracing/coresight/coresight-core.c
@@ -35,18 +35,16 @@ struct coresight_node {
};
/*
- * When operating Coresight drivers from the sysFS interface, only a single
- * path can exist from a tracer (associated to a CPU) to a sink.
+ * struct coresight_path - path from source to sink
+ * @path: Address of path list.
+ * @link: hook to the list.
*/
-static DEFINE_PER_CPU(struct list_head *, tracer_path);
+struct coresight_path {
+ struct list_head *path;
+ struct list_head link;
+};
-/*
- * As of this writing only a single STM can be found in CS topologies. Since
- * there is no way to know if we'll ever see more and what kind of
- * configuration they will enact, for the time being only define a single path
- * for STM.
- */
-static struct list_head *stm_path;
+static LIST_HEAD(cs_active_paths);
/*
* When losing synchronisation a new barrier packet needs to be inserted at the
@@ -326,7 +324,7 @@ static void coresight_disable_sink(struct coresight_device *csdev)
if (ret)
return;
coresight_control_assoc_ectdev(csdev, false);
- csdev->enable = false;
+ csdev->activated = false;
}
static int coresight_enable_link(struct coresight_device *csdev,
@@ -562,6 +560,20 @@ int coresight_enable_path(struct list_head *path, u32 mode, void *sink_data)
goto out;
}
+static struct coresight_device *coresight_get_source(struct list_head *path)
+{
+ struct coresight_device *csdev;
+
+ if (!path)
+ return NULL;
+
+ csdev = list_first_entry(path, struct coresight_node, link)->csdev;
+ if (csdev->type != CORESIGHT_DEV_TYPE_SOURCE)
+ return NULL;
+
+ return csdev;
+}
+
struct coresight_device *coresight_get_sink(struct list_head *path)
{
struct coresight_device *csdev;
@@ -1047,9 +1059,23 @@ static int coresight_validate_source(struct coresight_device *csdev,
return 0;
}
+static int coresight_store_path(struct list_head *path)
+{
+ struct coresight_path *node;
+
+ node = kzalloc(sizeof(struct coresight_path), GFP_KERNEL);
+ if (!node)
+ return -ENOMEM;
+
+ node->path = path;
+ list_add(&node->link, &cs_active_paths);
+
+ return 0;
+}
+
int coresight_enable(struct coresight_device *csdev)
{
- int cpu, ret = 0;
+ int ret = 0;
struct coresight_device *sink;
struct list_head *path;
enum coresight_dev_subtype_source subtype;
@@ -1094,25 +1120,9 @@ int coresight_enable(struct coresight_device *csdev)
if (ret)
goto err_source;
- switch (subtype) {
- case CORESIGHT_DEV_SUBTYPE_SOURCE_PROC:
- /*
- * When working from sysFS it is important to keep track
- * of the paths that were created so that they can be
- * undone in 'coresight_disable()'. Since there can only
- * be a single session per tracer (when working from sysFS)
- * a per-cpu variable will do just fine.
- */
- cpu = source_ops(csdev)->cpu_id(csdev);
- per_cpu(tracer_path, cpu) = path;
- break;
- case CORESIGHT_DEV_SUBTYPE_SOURCE_SOFTWARE:
- stm_path = path;
- break;
- default:
- /* We can't be here */
- break;
- }
+ ret = coresight_store_path(path);
+ if (ret)
+ goto err_source;
out:
mutex_unlock(&coresight_mutex);
@@ -1129,8 +1139,11 @@ EXPORT_SYMBOL_GPL(coresight_enable);
void coresight_disable(struct coresight_device *csdev)
{
- int cpu, ret;
+ int ret;
struct list_head *path = NULL;
+ struct coresight_path *cspath = NULL;
+ struct coresight_path *cspath_next = NULL;
+ struct coresight_device *src_csdev = NULL;
mutex_lock(&coresight_mutex);
@@ -1141,20 +1154,18 @@ void coresight_disable(struct coresight_device *csdev)
if (!csdev->enable || !coresight_disable_source(csdev))
goto out;
- switch (csdev->subtype.source_subtype) {
- case CORESIGHT_DEV_SUBTYPE_SOURCE_PROC:
- cpu = source_ops(csdev)->cpu_id(csdev);
- path = per_cpu(tracer_path, cpu);
- per_cpu(tracer_path, cpu) = NULL;
- break;
- case CORESIGHT_DEV_SUBTYPE_SOURCE_SOFTWARE:
- path = stm_path;
- stm_path = NULL;
- break;
- default:
- /* We can't be here */
- break;
+ list_for_each_entry_safe(cspath, cspath_next, &cs_active_paths, link) {
+ src_csdev = coresight_get_source(cspath->path);
+ if (!src_csdev)
+ continue;
+ if (src_csdev == csdev) {
+ path = cspath->path;
+ list_del(&cspath->link);
+ kfree(cspath);
+ }
}
+ if (path == NULL)
+ goto out;
coresight_disable_path(path);
coresight_release_path(path);
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
This series add support for coresight device name. In this way,
nodes with specific names can be generated under sysfs, not just
names with prefixes and index numbers. The coresight device can
be quickly identified by the coresight names of sysfs nodes. This
also allows using same names for CoreSight devices across different
targets. This makes it easy to develop common scripts, which can
be run across targets. Meanwhile, the script can use the same
device name to control the same coresight device.
This series patches base on coresight-next repo
http://git.linaro.org/kernel/coresight.git/log/?h=next
Tao Zhang (2):
coresight: Add support for device names
dt-bindings: arm: add property for coresight component name
Documentation/devicetree/bindings/arm/coresight.txt | 2 ++
drivers/hwtracing/coresight/coresight-core.c | 6 ++++++
2 files changed, 8 insertions(+)
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
The following changes since commit 4fb13790417a7bf726f3867a5d2b9723efde488b:
dts: bindings: Document device tree bindings for Arm TRBE (2021-04-06 16:05:38 -0600)
are available in the Git repository at:
git@gitolite.kernel.org:pub/scm/linux/kernel/git/coresight/linux.git next-ETE-TRBE
for you to fetch changes up to 68d400c079978f649e7f63aba966d219743edd64:
coresight: trbe: Fix return value check in arm_trbe_register_coresight_cpu() (2021-04-13 09:46:27 -0600)
----------------------------------------------------------------
Hi Marc,
Please consider these two patches, they are ETE/TRBE fixes found by bots.
Let me know if you want me to rebase on your next branch and send the
pull request from that.
Thanks,
Mathieu
----------------------------------------------------------------
Wei Yongjun (2):
coresight: core: Make symbol 'csdev_sink' static
coresight: trbe: Fix return value check in arm_trbe_register_coresight_cpu()
drivers/hwtracing/coresight/coresight-core.c | 2 +-
drivers/hwtracing/coresight/coresight-trbe.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)