CoreSight

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2627 discussions

[PATCH v2 0/6] coresight: syscfg: Extend configfs for config load

by Mike Leach

This set extends the configfs support to allow loading and unloading of configurations as binary files via configfs. Additional attributes - load, unload and last_load_status are provided to implement the load functionality. Routines to generate binary configuration files are supplied in ./samples/coresight. Example generator and reader applications are provided. Additional Makefile.host supplied to build the generator and reader applications on the host system separate from a cross compiled kernel. Documentation is updated to describe feature usage. Applies and tested on latest coresight/next that includes the previous coresight configuration dynamic load patchset. Changes since v1: 1) Rebased to coresight/next - 5.16-rc1 with previous coresight config set applied. 2) Makefile.host fixed to default to all target. Mike Leach (6): coresight: configfs: Add in functionality for load via configfs coresight: configfs: Add in binary attributes to load files coresight: configfs: Modify config files to allow userspace use coresight: samples: Add an example config writer for configfs load coresight: samples: Add coresight file reader sample program Documentation: coresight: docs for config load via configfs .../trace/coresight/coresight-config.rst | 151 +++++- drivers/hwtracing/coresight/Makefile | 2 +- .../coresight/coresight-config-file.c | 472 ++++++++++++++++++ .../coresight/coresight-config-file.h | 158 ++++++ .../hwtracing/coresight/coresight-config.h | 38 ++ .../coresight/coresight-syscfg-configfs.c | 148 +++++- .../coresight/coresight-syscfg-configfs.h | 8 + .../hwtracing/coresight/coresight-syscfg.c | 36 ++ .../hwtracing/coresight/coresight-syscfg.h | 2 + samples/coresight/Makefile | 23 + samples/coresight/Makefile.host | 47 ++ samples/coresight/coresight-cfg-bufw.c | 302 +++++++++++ samples/coresight/coresight-cfg-bufw.h | 24 + samples/coresight/coresight-cfg-file-read.c | 191 +++++++ samples/coresight/coresight-cfg-filegen.c | 89 ++++ 15 files changed, 1677 insertions(+), 14 deletions(-) create mode 100644 drivers/hwtracing/coresight/coresight-config-file.c create mode 100644 drivers/hwtracing/coresight/coresight-config-file.h create mode 100644 samples/coresight/Makefile.host create mode 100644 samples/coresight/coresight-cfg-bufw.c create mode 100644 samples/coresight/coresight-cfg-bufw.h create mode 100644 samples/coresight/coresight-cfg-file-read.c create mode 100644 samples/coresight/coresight-cfg-filegen.c -- 2.17.1

4 years

Re: [PATCH v2] coresight: syscfg: Fix memleak on registration failure in cscfg_create_device

by Mathieu Poirier

On Mon, Jan 24, 2022 at 12:41:21PM +0000, Miaoqian Lin wrote: > device_register() calls device_initialize(), > according to doc of device_initialize: > > Use put_device() to give up your reference instead of freeing > * @dev directly once you have called this function. > > To prevent potential memleak, use put_device() for error handling. > > Signed-off-by: Miaoqian Lin <linmq006(a)gmail.com> > --- > Changes in v2: > - simply call put_device() instead of cscfg_dev_release() in the error > path of cscfg_create_device. > --- > drivers/hwtracing/coresight/coresight-syscfg.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/hwtracing/coresight/coresight-syscfg.c b/drivers/hwtracing/coresight/coresight-syscfg.c > index 43054568430f..c30989e0675f 100644 > --- a/drivers/hwtracing/coresight/coresight-syscfg.c > +++ b/drivers/hwtracing/coresight/coresight-syscfg.c > @@ -791,7 +791,7 @@ static int cscfg_create_device(void) > > err = device_register(dev); > if (err) > - cscfg_dev_release(dev); > + put_device(dev); Applied. Thanks, Mathieu > > create_dev_exit_unlock: > mutex_unlock(&cscfg_mutex); > -- > 2.17.1 >

4 years

[PATCH v2 0/1] coresight: Fix TRCCONFIGR.QE sysfs interface

by James Clark

Changes since v1: * Add Mike's reviewed by tag * Also make it impossible to write the reserved value of 0b10, regardless of what is supplied by the user. James Clark (1): coresight: Fix TRCCONFIGR.QE sysfs interface drivers/hwtracing/coresight/coresight-etm4x-sysfs.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) -- 2.28.0

4 years

Re: [RFC PATCH] ACPI / amba: Skip creating amba device when associated cpu is not online

by Suzuki K Poulose

On 28/01/2022 15:28, Robin Murphy wrote: > On 2022-01-28 11:00, Suzuki K Poulose wrote: >> Hi Xiang >> >> On 07/01/2022 08:41, chenxiang wrote: >>> From: Xiang Chen <chenxiang66(a)hisilicon.com> >>> >>> If not up all the cpus with command line "maxcpus=x", system will be >>> blocked. >>> We find that some amba devices such as ETM devices, are associated with >>> special cpus, and if the cpu is not up, the register of associated >>> device >>> is not allowed to access. BIOS reports all the ETM device nodes and a >>> amba device is created for every ETM device, so even if one cpu is >>> not up, >>> the amba device will still be created for the associated device, and >>> also >>> the register of device (pid and cid) will be accessed when adding amba >>> device which will cause the issue. >>> To fix it, skip creating amba device if it is associated with a cpu >>> which >>> is not online. >> >> I understand the issue. We do not have an issue at least on DT based >> platforms with a similar environment (Juno). The key is the power >> management for the components. >> >> There are two separate issues at play here : >> >> 1) Power management with ACPI. I believe there is a solution in progress >> to address this. >> >> 2) The ETM is in the same power domain as that of the CPU and normal >> device power management may not work without the CPU being online. >> >> 3) Additionally we have other issue of supporting system instructions >> with ACPI, which do not appear on the AMBA bus. >> >> Considering all of these, the ideal solution is to : >> >> 1) Implement power management for ACPI, which is anyway in progress >> (at least for SCMI based systems) >> 2) Move the ETM driver away from the AMBA framework. That would make >> the CPU online problem and the (3) above easier to solve. >> Anshuman is going to look into this. >> >> In the meantime, we could have this temporary fix in and solve it >> forever by moving away from the AMBA. > > Out of curiosity, what happens when you boot with "maxcpus=" and then > manually bring up the extra cpus from userspace later? Is there a chance > that tracing will explode if some online CPUs have ETM initialised but > others don't? No. At the moment, we don't bring the ETMs online for hotplugged CPUs. i.e., ETM is not registered for the CPU. So any attempt to trace on that CPU will fail. Probe deferral doesn't go beyond the userspace init. But we plan to add hotplug support, by defering the ETM probe. At present, the ETMs are bound to the AMBA frame work and I am not sure if there is a way to explicitly trigger a probe from the AMBA layer on CPU hotplug. The other option is to always create the AMBA device and defer the "etm" probe to a cpu hotplug notifier in the ETM driver. This is something we plan to add. Suzuki > > Robin. > >>> >>> Signed-off-by: Xiang Chen <chenxiang66(a)hisilicon.com> >>> --- >>> drivers/acpi/acpi_amba.c | 36 ++++++++++++++++++++++++++++++++++++ >>> 1 file changed, 36 insertions(+) >>> >>> diff --git a/drivers/acpi/acpi_amba.c b/drivers/acpi/acpi_amba.c >>> index ab8a4e0191b1..2369198f734b 100644 >>> --- a/drivers/acpi/acpi_amba.c >>> +++ b/drivers/acpi/acpi_amba.c >>> @@ -16,6 +16,7 @@ >>> #include <linux/ioport.h> >>> #include <linux/kernel.h> >>> #include <linux/module.h> >>> +#include <acpi/processor.h> >>> #include "internal.h" >>> @@ -45,6 +46,35 @@ static void amba_register_dummy_clk(void) >>> clk_register_clkdev(amba_dummy_clk, "apb_pclk", NULL); >>> } >>> +static int acpi_handle_to_cpuid(acpi_handle handle) >>> +{ >>> + int cpu = -1; >>> + struct acpi_processor *pr; >>> + >>> + for_each_possible_cpu(cpu) { >>> + pr = per_cpu(processors, cpu); >>> + if (pr && pr->handle == handle) >>> + break; >>> + } >>> + >>> + return cpu; >>> +} >>> + >> >> Please could we reuse the function in coresight-platform.c ? >> i.e, move it to a generic location and share it, rather than >> duplicating it ? >> >> >>> +static int acpi_dev_get_cpu(struct acpi_device *adev) >>> +{ >>> + acpi_handle cpu_handle; >>> + acpi_status status; >>> + int cpu; >>> + >>> + status = acpi_get_parent(adev->handle, &cpu_handle); >>> + if (ACPI_FAILURE(status)) >>> + return -1; >>> + cpu = acpi_handle_to_cpuid(cpu_handle); >>> + if (cpu >= nr_cpu_ids) >>> + return -1; >>> + return cpu; >>> +} >>> + >>> static int amba_handler_attach(struct acpi_device *adev, >>> const struct acpi_device_id *id) >>> { >>> @@ -54,11 +84,17 @@ static int amba_handler_attach(struct acpi_device >>> *adev, >>> bool address_found = false; >>> int irq_no = 0; >>> int ret; >>> + int cpu; >>> /* If the ACPI node already has a physical device attached, >>> skip it. */ >>> if (adev->physical_node_count) >>> return 0; >>> + /* If the cpu associated with the device is not online, skip it. */ >>> + cpu = acpi_dev_get_cpu(adev); >>> + if (cpu >= 0 && !cpu_online(cpu)) >>> + return 0; >>> + >> >> Except for the comment above, the patch looks good to me. >> >> Suzuki >> >> _______________________________________________ >> linux-arm-kernel mailing list >> linux-arm-kernel(a)lists.infradead.org >> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

4 years

Re: [PATCH V3 RESEND 0/7] coresight: trbe: Workaround Cortex-A510 erratas

by Mathieu Poirier

On Fri, 28 Jan 2022 at 03:51, Catalin Marinas <catalin.marinas(a)arm.com> wrote: > > Hi Mathieu, > > On Thu, Jan 27, 2022 at 01:22:20PM -0700, Mathieu Poirier wrote: > > On Tue, Jan 25, 2022 at 07:50:30PM +0530, Anshuman Khandual wrote: > > > Anshuman Khandual (7): > > > arm64: Add Cortex-A510 CPU part definition > > > arm64: errata: Add detection for TRBE ignored system register writes > > > arm64: errata: Add detection for TRBE invalid prohibited states > > > arm64: errata: Add detection for TRBE trace data corruption > > > coresight: trbe: Work around the ignored system register writes > > > coresight: trbe: Work around the invalid prohibited states > > > coresight: trbe: Work around the trace data corruption > > > > > > Documentation/arm64/silicon-errata.rst | 6 + > > > arch/arm64/Kconfig | 59 ++++++++++ > > > arch/arm64/include/asm/cputype.h | 2 + > > > arch/arm64/kernel/cpu_errata.c | 27 +++++ > > > arch/arm64/tools/cpucaps | 3 + > > > drivers/hwtracing/coresight/coresight-trbe.c | 114 ++++++++++++++----- > > > drivers/hwtracing/coresight/coresight-trbe.h | 8 -- > > > 7 files changed, 183 insertions(+), 36 deletions(-) > > > > I have applied this set and sent a pull request to Catalin for the arm64 > > portion. > > Well, I'm happy for the whole series to go in via Greg's tree or however > the coresight patches go in (that's why I acked them). The last three > patches depend on the first four, so you might as well send them all > together. I'd split the series only if there's a conflict with the arm64 > tree (I haven't checked). > Very well - thanks for the follow up. > -- > Catalin

4 years

Re: [RFC PATCH] ACPI / amba: Skip creating amba device when associated cpu is not online

by Suzuki K Poulose

Hi Xiang On 07/01/2022 08:41, chenxiang wrote: > From: Xiang Chen <chenxiang66(a)hisilicon.com> > > If not up all the cpus with command line "maxcpus=x", system will be > blocked. > We find that some amba devices such as ETM devices, are associated with > special cpus, and if the cpu is not up, the register of associated device > is not allowed to access. BIOS reports all the ETM device nodes and a > amba device is created for every ETM device, so even if one cpu is not up, > the amba device will still be created for the associated device, and also > the register of device (pid and cid) will be accessed when adding amba > device which will cause the issue. > To fix it, skip creating amba device if it is associated with a cpu which > is not online. I understand the issue. We do not have an issue at least on DT based platforms with a similar environment (Juno). The key is the power management for the components. There are two separate issues at play here : 1) Power management with ACPI. I believe there is a solution in progress to address this. 2) The ETM is in the same power domain as that of the CPU and normal device power management may not work without the CPU being online. 3) Additionally we have other issue of supporting system instructions with ACPI, which do not appear on the AMBA bus. Considering all of these, the ideal solution is to : 1) Implement power management for ACPI, which is anyway in progress (at least for SCMI based systems) 2) Move the ETM driver away from the AMBA framework. That would make the CPU online problem and the (3) above easier to solve. Anshuman is going to look into this. In the meantime, we could have this temporary fix in and solve it forever by moving away from the AMBA. > > Signed-off-by: Xiang Chen <chenxiang66(a)hisilicon.com> > --- > drivers/acpi/acpi_amba.c | 36 ++++++++++++++++++++++++++++++++++++ > 1 file changed, 36 insertions(+) > > diff --git a/drivers/acpi/acpi_amba.c b/drivers/acpi/acpi_amba.c > index ab8a4e0191b1..2369198f734b 100644 > --- a/drivers/acpi/acpi_amba.c > +++ b/drivers/acpi/acpi_amba.c > @@ -16,6 +16,7 @@ > #include <linux/ioport.h> > #include <linux/kernel.h> > #include <linux/module.h> > +#include <acpi/processor.h> > > #include "internal.h" > > @@ -45,6 +46,35 @@ static void amba_register_dummy_clk(void) > clk_register_clkdev(amba_dummy_clk, "apb_pclk", NULL); > } > > +static int acpi_handle_to_cpuid(acpi_handle handle) > +{ > + int cpu = -1; > + struct acpi_processor *pr; > + > + for_each_possible_cpu(cpu) { > + pr = per_cpu(processors, cpu); > + if (pr && pr->handle == handle) > + break; > + } > + > + return cpu; > +} > + Please could we reuse the function in coresight-platform.c ? i.e, move it to a generic location and share it, rather than duplicating it ? > +static int acpi_dev_get_cpu(struct acpi_device *adev) > +{ > + acpi_handle cpu_handle; > + acpi_status status; > + int cpu; > + > + status = acpi_get_parent(adev->handle, &cpu_handle); > + if (ACPI_FAILURE(status)) > + return -1; > + cpu = acpi_handle_to_cpuid(cpu_handle); > + if (cpu >= nr_cpu_ids) > + return -1; > + return cpu; > +} > + > static int amba_handler_attach(struct acpi_device *adev, > const struct acpi_device_id *id) > { > @@ -54,11 +84,17 @@ static int amba_handler_attach(struct acpi_device *adev, > bool address_found = false; > int irq_no = 0; > int ret; > + int cpu; > > /* If the ACPI node already has a physical device attached, skip it. */ > if (adev->physical_node_count) > return 0; > > + /* If the cpu associated with the device is not online, skip it. */ > + cpu = acpi_dev_get_cpu(adev); > + if (cpu >= 0 && !cpu_online(cpu)) > + return 0; > + Except for the comment above, the patch looks good to me. Suzuki

4 years

Re: [RFC PATCH] ACPI / amba: Skip creating amba device when associated cpu is not online

by Mathieu Poirier

Hi Cheng, I am severely behind in my patch review process and as such will not be able to start reviewing your work before the week of February 7th. Thanks, Mathieu On Fri, 7 Jan 2022 at 01:47, chenxiang <chenxiang66(a)hisilicon.com> wrote: > > From: Xiang Chen <chenxiang66(a)hisilicon.com> > > If not up all the cpus with command line "maxcpus=x", system will be > blocked. > We find that some amba devices such as ETM devices, are associated with > special cpus, and if the cpu is not up, the register of associated device > is not allowed to access. BIOS reports all the ETM device nodes and a > amba device is created for every ETM device, so even if one cpu is not up, > the amba device will still be created for the associated device, and also > the register of device (pid and cid) will be accessed when adding amba > device which will cause the issue. > To fix it, skip creating amba device if it is associated with a cpu which > is not online. > > Signed-off-by: Xiang Chen <chenxiang66(a)hisilicon.com> > --- > drivers/acpi/acpi_amba.c | 36 ++++++++++++++++++++++++++++++++++++ > 1 file changed, 36 insertions(+) > > diff --git a/drivers/acpi/acpi_amba.c b/drivers/acpi/acpi_amba.c > index ab8a4e0191b1..2369198f734b 100644 > --- a/drivers/acpi/acpi_amba.c > +++ b/drivers/acpi/acpi_amba.c > @@ -16,6 +16,7 @@ > #include <linux/ioport.h> > #include <linux/kernel.h> > #include <linux/module.h> > +#include <acpi/processor.h> > > #include "internal.h" > > @@ -45,6 +46,35 @@ static void amba_register_dummy_clk(void) > clk_register_clkdev(amba_dummy_clk, "apb_pclk", NULL); > } > > +static int acpi_handle_to_cpuid(acpi_handle handle) > +{ > + int cpu = -1; > + struct acpi_processor *pr; > + > + for_each_possible_cpu(cpu) { > + pr = per_cpu(processors, cpu); > + if (pr && pr->handle == handle) > + break; > + } > + > + return cpu; > +} > + > +static int acpi_dev_get_cpu(struct acpi_device *adev) > +{ > + acpi_handle cpu_handle; > + acpi_status status; > + int cpu; > + > + status = acpi_get_parent(adev->handle, &cpu_handle); > + if (ACPI_FAILURE(status)) > + return -1; > + cpu = acpi_handle_to_cpuid(cpu_handle); > + if (cpu >= nr_cpu_ids) > + return -1; > + return cpu; > +} > + > static int amba_handler_attach(struct acpi_device *adev, > const struct acpi_device_id *id) > { > @@ -54,11 +84,17 @@ static int amba_handler_attach(struct acpi_device *adev, > bool address_found = false; > int irq_no = 0; > int ret; > + int cpu; > > /* If the ACPI node already has a physical device attached, skip it. */ > if (adev->physical_node_count) > return 0; > > + /* If the cpu associated with the device is not online, skip it. */ > + cpu = acpi_dev_get_cpu(adev); > + if (cpu >= 0 && !cpu_online(cpu)) > + return 0; > + > dev = amba_device_alloc(dev_name(&adev->dev), 0, 0); > if (!dev) { > dev_err(&adev->dev, "%s(): amba_device_alloc() failed\n", > -- > 2.33.0 >

4 years

Re: [PATCH V3 RESEND 0/7] coresight: trbe: Workaround Cortex-A510 erratas

by Mathieu Poirier

On Tue, Jan 25, 2022 at 07:50:30PM +0530, Anshuman Khandual wrote: > This series adds three different workarounds in the TRBE driver for > Cortex-A510 specific erratas. But first, this adds Cortex-A510 specific cpu > part number definition in the platform. This series applies on 5.17-rc1. > > Relevant errata documents can be found here. > > https://developer.arm.com/documentation/SDEN2397239/900 > https://developer.arm.com/documentation/SDEN2397589/900 > > Changes in V3: > > https://lore.kernel.org/all/1641872346-3270-1-git-send-email-anshuman.khand… > > - Moved the comment inside trbe_needs_drain_after_disable() > - Moved the comment inside trbe_needs_ctxt_sync_after_enable() > > Changes in V2: > > https://lore.kernel.org/all/1641517808-5735-1-git-send-email-anshuman.khand… > > Accommodated most review comments from the previous version. > > - Split all patches into CPU errata definition, detection and TRBE workarounds > - s/TRBE_WORKAROUND_SYSREG_WRITE_FAILURE/TRBE_NEEDS_DRAIN_AFTER_DISABLE > - s/TRBE_WORKAROUND_CORRUPTION_WITH_ENABLE/TRBE_NEEDS_CTXT_SYNC_AFTER_ENABLE > - s/trbe_may_fail_sysreg_write()/trbe_needs_drain_after_disable() > - s/trbe_may_corrupt_with_enable()/trbe_needs_ctxt_sync_after_enable() > - Updated Kconfig help message for config ARM64_ERRATUM_1902691 > - Updated error message for trbe_is_broken() detection > - Added new trblimitr parameter to set_trbe_enabled(), improving performance > - Added COMPILE_TEST dependency in the errata, until TRBE part is available > > Changes in V1: > > https://lore.kernel.org/lkml/1641359159-22726-1-git-send-email-anshuman.kha… > > Cc: Catalin Marinas <catalin.marinas(a)arm.com> > Cc: Will Deacon <will(a)kernel.org> > Cc: Mathieu Poirier <mathieu.poirier(a)linaro.org> > Cc: Suzuki Poulose <suzuki.poulose(a)arm.com> > Cc: coresight(a)lists.linaro.org > Cc: linux-doc(a)vger.kernel.org > Cc: linux-arm-kernel(a)lists.infradead.org > Cc: linux-kernel(a)vger.kernel.org > > Anshuman Khandual (7): > arm64: Add Cortex-A510 CPU part definition > arm64: errata: Add detection for TRBE ignored system register writes > arm64: errata: Add detection for TRBE invalid prohibited states > arm64: errata: Add detection for TRBE trace data corruption > coresight: trbe: Work around the ignored system register writes > coresight: trbe: Work around the invalid prohibited states > coresight: trbe: Work around the trace data corruption > > Documentation/arm64/silicon-errata.rst | 6 + > arch/arm64/Kconfig | 59 ++++++++++ > arch/arm64/include/asm/cputype.h | 2 + > arch/arm64/kernel/cpu_errata.c | 27 +++++ > arch/arm64/tools/cpucaps | 3 + > drivers/hwtracing/coresight/coresight-trbe.c | 114 ++++++++++++++----- > drivers/hwtracing/coresight/coresight-trbe.h | 8 -- > 7 files changed, 183 insertions(+), 36 deletions(-) I have applied this set and sent a pull request to Catalin for the arm64 portion. Thanks, Mathieu > > -- > 2.25.1 >

4 years

Re: [PATCH v2 2/9] Coresight: Add coresight TPDM source driver

by Mathieu Poirier

Hi Jinlong, On Fri, Jan 21, 2022 at 10:01:47PM +0800, Jinlong Mao wrote: > Hi Mathieu, > > Good Day. > > On 12/17/2021 3:02 AM, Mathieu Poirier wrote: > > [...] > > > > > > > > + > > > > > > +static void tpdm_init_default_data(struct tpdm_drvdata *drvdata) > > > > > > +{ > > > > > > + static int traceid = TPDM_TRACE_ID_START; > > > > > > + > > > > > > + drvdata->traceid = traceid++; > > > > > > +} > > > > > I have been specific on how to properly do this in the last revision. Given the > > > > > above about the MAINTAINERS file, I am not sure that I will continue reviewing this set. > > > > > > > > > > There is also no need to rush another revision as I won't have the bandwidth to > > > > > process it before the holidays. > > > > > > > > > > Thanks, > > > > > Mathieu > > > > Hi Mathieu, > > > > > > > > Sorry, not addressed your previous comments here. > > > > > > > > For the trace id, each coresight component has 7 bits to store the trace > > > > id. So the trace id should be from 1 to 127 as 0 is invalid. > > > IDs 0x70 - 0x7F (`112 - 127 ) are reserved - see the ARM Coresight > > > Architecture specification v3.0 > > > > > Correct > > > > > > Apart from TPDMs/STM/ETMs, we also have other coresight components in > > > > our internal device. About 80 ids are already used. > > > > > > > > Some components have fixed trace id in HW. If we use functions below to > > > > count the trace id, there will be conflict to other components. > > > > > > > > Can we use 1-15 for etm trace ids and 16 - 127 for other coresight > > > > components ? And handle trace ids in its' own driver ? > > > > > > > This will limit systems to 15 cores - some have more! > > > > > Correct > > > > > > static inline int coresight_get_system_trace_id(int id) > > > > { > > > > /* Start system IDs above the highest per CPU trace ID. */ > > > > return coresigth_get_trace_id(cpumask_last(cpu_possible_mask) + 1); > > > > } > > Looking at my own suggestion again this won't work since it returns the same traceID > > when called multiple times. > > > > For this patchset and _without_ taking into account internal devices that have > > their traceID set in HW: > > > > 1. Define a bitmask that is 7 bit wide. > Should it be a 128 bit wide bitmask (0--127)? > > 2. By default, set bits under 0x10 and between 0x70 - 0x7F. > > 3. In coresight_get_system_trace_id(), drop the @id parameter and allocate the > > first available bit after cpumask_last(cpu_possible_mask) + 1. > > Should it allocate the first available bit after (cpumask_last(cpu_possible_mask) *2 ) + 0x10 ? > Return the first zero bit position as the trace id and set the bit. Please ignore my email from January 26th and proceed exactly as you stated above. I had conversations with Suzuki and Mike and providing an appropriate fix for this issue needs more investigation. Aplogies for the flip-flopping, as I said earlier this is a complex problem we've been restling with for quite some time now. Thanks, Mathieu > > > 4. Define a new function called coresight_put_system_trace_id(int id) that > > clears the bit in the mask corresponding to @id. > > > > For now that should work. > > > > > > static inline int coresight_get_trace_id(int cpu) > > > > { > > > > /* > > > > * A trace ID of value 0 is invalid, so let's start at some > > > > * random value that fits in 7 bits and go from there. Since > > > > * the common convention is to have data trace IDs be I(N) + 1, > > > > * set instruction trace IDs as a function of the CPU number. > > > > */ > > > > return (CORESIGHT_ETM_PMU_SEED + (cpu * 2)); > > > > } > > > > > > > This fixed relationship between cpu and trace ID is used in the perf > > > tooling to populate the elements in the perf.data file to correctly > > > allow association between CPU and trace data, and thus allow correct > > > trace decode. > > TraceIDs associated to CPUs are communicated to the perf tooling by way of the > > perf header - theoretically we should be able to change the allocation scheme > > without impacting the decoding process. > > > > > It should be possible to create another more dynamic mapping scheme - > > > but this must include a way to support the perf requirements too. > > > > > TraceIDs have been a lurking problem for as long as the subsystem has existed. > > For now what I have suggested above should be sufficient to provide an > > in-between solution that doesn't hold back this patchset. > > > > That being said, we need to start thinking about the best way to do this. I > > will put a patchset together in the new year that aims in that direction. > > > > > Regards > > > > > > Mike > > > > > > > Thanks > > > > > > > > Jinlong Mao > > > > > > > > > > + > > > > > > +static int tpdm_probe(struct amba_device *adev, const struct amba_id *id) > > > > > > +{ > > > > > > + struct device *dev = &adev->dev; > > > > > > + struct coresight_platform_data *pdata; > > > > > > + struct tpdm_drvdata *drvdata; > > > > > > + struct coresight_desc desc = { 0 }; > > > > > > + > > > > > > + desc.name = coresight_alloc_device_name(&tpdm_devs, dev); > > > > > > + if (!desc.name) > > > > > > + return -ENOMEM; > > > > > > + pdata = coresight_get_platform_data(dev); > > > > > > + if (IS_ERR(pdata)) > > > > > > + return PTR_ERR(pdata); > > > > > > + adev->dev.platform_data = pdata; > > > > > > + > > > > > > + drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL); > > > > > > + if (!drvdata) > > > > > > + return -ENOMEM; > > > > > > + drvdata->dev = &adev->dev; > > > > > > + dev_set_drvdata(dev, drvdata); > > > > > > + > > > > > > + drvdata->base = devm_ioremap_resource(dev, &adev->res); > > > > > > + if (!drvdata->base) > > > > > > + return -ENOMEM; > > > > > > + > > > > > > + mutex_init(&drvdata->lock); > > > > > > + > > > > > > + desc.type = CORESIGHT_DEV_TYPE_SOURCE; > > > > > > + desc.subtype.source_subtype = CORESIGHT_DEV_SUBTYPE_SOURCE_SYS; > > > > > > + desc.ops = &tpdm_cs_ops; > > > > > > + desc.pdata = adev->dev.platform_data; > > > > > > + desc.dev = &adev->dev; > > > > > > + drvdata->csdev = coresight_register(&desc); > > > > > > + if (IS_ERR(drvdata->csdev)) > > > > > > + return PTR_ERR(drvdata->csdev); > > > > > > + > > > > > > + tpdm_init_default_data(drvdata); > > > > > > + pm_runtime_put(&adev->dev); > > > > > > + > > > > > > + return 0; > > > > > > +} > > > > > > + > > > > > > +static void __exit tpdm_remove(struct amba_device *adev) > > > > > > +{ > > > > > > + struct tpdm_drvdata *drvdata = dev_get_drvdata(&adev->dev); > > > > > > + > > > > > > + coresight_unregister(drvdata->csdev); > > > > > > +} > > > > > > + > > > > > > +static struct amba_id tpdm_ids[] = { > > > > > > + { > > > > > > + .id = 0x000f0e00, > > > > > > + .mask = 0x000fff00, > > > > > > + }, > > > > > > + { 0, 0}, > > > > > > +}; > > > > > > + > > > > > > +static struct amba_driver tpdm_driver = { > > > > > > + .drv = { > > > > > > + .name = "coresight-tpdm", > > > > > > + .owner = THIS_MODULE, > > > > > > + .suppress_bind_attrs = true, > > > > > > + }, > > > > > > + .probe = tpdm_probe, > > > > > > + .id_table = tpdm_ids, > > > > > > +}; > > > > > > + > > > > > > +module_amba_driver(tpdm_driver); > > > > > > + > > > > > > +MODULE_LICENSE("GPL v2"); > > > > > > +MODULE_DESCRIPTION("Trace, Profiling & Diagnostic Monitor driver"); > > > > > > diff --git a/drivers/hwtracing/coresight/coresight-tpdm.h b/drivers/hwtracing/coresight/coresight-tpdm.h > > > > > > new file mode 100644 > > > > > > index 000000000000..980ae90ff1c8 > > > > > > --- /dev/null > > > > > > +++ b/drivers/hwtracing/coresight/coresight-tpdm.h > > > > > > @@ -0,0 +1,31 @@ > > > > > > +/* SPDX-License-Identifier: GPL-2.0 */ > > > > > > +/* > > > > > > + * Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved. > > > > > > + */ > > > > > > + > > > > > > +#ifndef _CORESIGHT_CORESIGHT_TPDM_H > > > > > > +#define _CORESIGHT_CORESIGHT_TPDM_H > > > > > > + > > > > > > +/* Default value of the traceid */ > > > > > > +#define TPDM_TRACE_ID_START 128 > > > > > > + > > > > > > +/** > > > > > > + * struct tpdm_drvdata - specifics associated to an TPDM component > > > > > > + * @base: memory mapped base address for this component. > > > > > > + * @dev: The device entity associated to this component. > > > > > > + * @csdev: component vitals needed by the framework. > > > > > > + * @lock: lock for the enable value. > > > > > > + * @enable: enable status of the component. > > > > > > + * @traceid: value of the current ID for this component. > > > > > > + */ > > > > > > + > > > > > > +struct tpdm_drvdata { > > > > > > + void __iomem *base; > > > > > > + struct device *dev; > > > > > > + struct coresight_device *csdev; > > > > > > + struct mutex lock; > > > > > > + bool enable; > > > > > > + int traceid; > > > > > > +}; > > > > > > + > > > > > > +#endif /* _CORESIGHT_CORESIGHT_TPDM_H */ > > > > > > diff --git a/include/linux/coresight.h b/include/linux/coresight.h > > > > > > index 93a2922b7653..e48d463be63b 100644 > > > > > > --- a/include/linux/coresight.h > > > > > > +++ b/include/linux/coresight.h > > > > > > @@ -65,6 +65,7 @@ enum coresight_dev_subtype_source { > > > > > > CORESIGHT_DEV_SUBTYPE_SOURCE_PROC, > > > > > > CORESIGHT_DEV_SUBTYPE_SOURCE_BUS, > > > > > > CORESIGHT_DEV_SUBTYPE_SOURCE_SOFTWARE, > > > > > > + CORESIGHT_DEV_SUBTYPE_SOURCE_SYS, > > > > > > }; > > > > > > > > > > > > enum coresight_dev_subtype_helper { > > > > > > -- > > > > > > 2.17.1 > > > > > > > > > > > > > > > -- > > > Mike Leach > > > Principal Engineer, ARM Ltd. > > > Manchester Design Centre. UK

4 years

Re: [PATCH v2 2/9] Coresight: Add coresight TPDM source driver

by Mathieu Poirier

On Wed, Jan 26, 2022 at 03:07:38PM +0800, Jinlong Mao wrote: > Hi Mathieu, > > Good afternoon. > > On 1/22/2022 1:15 AM, Mathieu Poirier wrote: > > Hey Jinlong, > > > > On Fri, Jan 21, 2022 at 10:01:47PM +0800, Jinlong Mao wrote: > > > Hi Mathieu, > > > > > > Good Day. > > > > > > On 12/17/2021 3:02 AM, Mathieu Poirier wrote: > > > > [...] > > > > > > > > > > > > + > > > > > > > > +static void tpdm_init_default_data(struct tpdm_drvdata *drvdata) > > > > > > > > +{ > > > > > > > > + static int traceid = TPDM_TRACE_ID_START; > > > > > > > > + > > > > > > > > + drvdata->traceid = traceid++; > > > > > > > > +} > > > > > > > I have been specific on how to properly do this in the last revision. Given the > > > > > > > above about the MAINTAINERS file, I am not sure that I will continue reviewing this set. > > > > > > > > > > > > > > There is also no need to rush another revision as I won't have the bandwidth to > > > > > > > process it before the holidays. > > > > > > > > > > > > > > Thanks, > > > > > > > Mathieu > > > > > > Hi Mathieu, > > > > > > > > > > > > Sorry, not addressed your previous comments here. > > > > > > > > > > > > For the trace id, each coresight component has 7 bits to store the trace > > > > > > id. So the trace id should be from 1 to 127 as 0 is invalid. > > > > > IDs 0x70 - 0x7F (`112 - 127 ) are reserved - see the ARM Coresight > > > > > Architecture specification v3.0 > > > > > > > > > Correct > > > > > > > > > > Apart from TPDMs/STM/ETMs, we also have other coresight components in > > > > > > our internal device. About 80 ids are already used. > > > > > > > > > > > > Some components have fixed trace id in HW. If we use functions below to > > > > > > count the trace id, there will be conflict to other components. > > > > > > > > > > > > Can we use 1-15 for etm trace ids and 16 - 127 for other coresight > > > > > > components ? And handle trace ids in its' own driver ? > > > > > > > > > > > This will limit systems to 15 cores - some have more! > > > > > > > > > Correct > > > > > > > > > > static inline int coresight_get_system_trace_id(int id) > > > > > > { > > > > > > /* Start system IDs above the highest per CPU trace ID. */ > > > > > > return coresigth_get_trace_id(cpumask_last(cpu_possible_mask) + 1); > > > > > > } > > > > Looking at my own suggestion again this won't work since it returns the same traceID > > > > when called multiple times. > > > > > > > > For this patchset and _without_ taking into account internal devices that have > > > > their traceID set in HW: > > > > > > > > 1. Define a bitmask that is 7 bit wide. > > > Should it be a 128 bit wide bitmask (0--127)? > > Yes, you are correct. > > > > > > 2. By default, set bits under 0x10 and between 0x70 - 0x7F. > > > > 3. In coresight_get_system_trace_id(), drop the @id parameter and allocate the > > > > first available bit after cpumask_last(cpu_possible_mask) + 1. > > > Should it allocate the first available bit after (cpumask_last(cpu_possible_mask) *2 ) + 0x10 ? > > > Return the first zero bit position as the trace id and set the bit. > > I need to clarify something with Mike on this - I will get back to you on > > Monday. > Do you have more comments on this ? I just received clarifications on this - there is no need to continue enacting the current scheme and as such reserving bits following the above formula will not be needed either. Simply assigning free traceIDs based on request will work just fine. That of course is taking into account that 0x0, 0x1 and 0x70 - 0x7f are reserved. 0x1 is currently used for STM and should eventually be fixed to simply request a traceID the same way any other component do. You can fix it as part of this set but it is not mandatory. Let me know if there are things I haven't been clear on. Thanks, Mathieu > > > > > > 4. Define a new function called coresight_put_system_trace_id(int id) that > > > > clears the bit in the mask corresponding to @id. > > > > > > > > For now that should work. > > > > > > > > > > static inline int coresight_get_trace_id(int cpu) > > > > > > { > > > > > > /* > > > > > > * A trace ID of value 0 is invalid, so let's start at some > > > > > > * random value that fits in 7 bits and go from there. Since > > > > > > * the common convention is to have data trace IDs be I(N) + 1, > > > > > > * set instruction trace IDs as a function of the CPU number. > > > > > > */ > > > > > > return (CORESIGHT_ETM_PMU_SEED + (cpu * 2)); > > > > > > } > > > > > > > > > > > This fixed relationship between cpu and trace ID is used in the perf > > > > > tooling to populate the elements in the perf.data file to correctly > > > > > allow association between CPU and trace data, and thus allow correct > > > > > trace decode. > > > > TraceIDs associated to CPUs are communicated to the perf tooling by way of the > > > > perf header - theoretically we should be able to change the allocation scheme > > > > without impacting the decoding process. > > > > > > > > > It should be possible to create another more dynamic mapping scheme - > > > > > but this must include a way to support the perf requirements too. > > > > > > > > > TraceIDs have been a lurking problem for as long as the subsystem has existed. > > > > For now what I have suggested above should be sufficient to provide an > > > > in-between solution that doesn't hold back this patchset. > > > > > > > > That being said, we need to start thinking about the best way to do this. I > > > > will put a patchset together in the new year that aims in that direction. > > > > > > > > > Regards > > > > > > > > > > Mike > > > > > > > > > > > Thanks > > > > > > > > > > > > Jinlong Mao > > > > > > > > > > > > > > + > > > > > > > > +static int tpdm_probe(struct amba_device *adev, const struct amba_id *id) > > > > > > > > +{ > > > > > > > > + struct device *dev = &adev->dev; > > > > > > > > + struct coresight_platform_data *pdata; > > > > > > > > + struct tpdm_drvdata *drvdata; > > > > > > > > + struct coresight_desc desc = { 0 }; > > > > > > > > + > > > > > > > > + desc.name = coresight_alloc_device_name(&tpdm_devs, dev); > > > > > > > > + if (!desc.name) > > > > > > > > + return -ENOMEM; > > > > > > > > + pdata = coresight_get_platform_data(dev); > > > > > > > > + if (IS_ERR(pdata)) > > > > > > > > + return PTR_ERR(pdata); > > > > > > > > + adev->dev.platform_data = pdata; > > > > > > > > + > > > > > > > > + drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL); > > > > > > > > + if (!drvdata) > > > > > > > > + return -ENOMEM; > > > > > > > > + drvdata->dev = &adev->dev; > > > > > > > > + dev_set_drvdata(dev, drvdata); > > > > > > > > + > > > > > > > > + drvdata->base = devm_ioremap_resource(dev, &adev->res); > > > > > > > > + if (!drvdata->base) > > > > > > > > + return -ENOMEM; > > > > > > > > + > > > > > > > > + mutex_init(&drvdata->lock); > > > > > > > > + > > > > > > > > + desc.type = CORESIGHT_DEV_TYPE_SOURCE; > > > > > > > > + desc.subtype.source_subtype = CORESIGHT_DEV_SUBTYPE_SOURCE_SYS; > > > > > > > > + desc.ops = &tpdm_cs_ops; > > > > > > > > + desc.pdata = adev->dev.platform_data; > > > > > > > > + desc.dev = &adev->dev; > > > > > > > > + drvdata->csdev = coresight_register(&desc); > > > > > > > > + if (IS_ERR(drvdata->csdev)) > > > > > > > > + return PTR_ERR(drvdata->csdev); > > > > > > > > + > > > > > > > > + tpdm_init_default_data(drvdata); > > > > > > > > + pm_runtime_put(&adev->dev); > > > > > > > > + > > > > > > > > + return 0; > > > > > > > > +} > > > > > > > > + > > > > > > > > +static void __exit tpdm_remove(struct amba_device *adev) > > > > > > > > +{ > > > > > > > > + struct tpdm_drvdata *drvdata = dev_get_drvdata(&adev->dev); > > > > > > > > + > > > > > > > > + coresight_unregister(drvdata->csdev); > > > > > > > > +} > > > > > > > > + > > > > > > > > +static struct amba_id tpdm_ids[] = { > > > > > > > > + { > > > > > > > > + .id = 0x000f0e00, > > > > > > > > + .mask = 0x000fff00, > > > > > > > > + }, > > > > > > > > + { 0, 0}, > > > > > > > > +}; > > > > > > > > + > > > > > > > > +static struct amba_driver tpdm_driver = { > > > > > > > > + .drv = { > > > > > > > > + .name = "coresight-tpdm", > > > > > > > > + .owner = THIS_MODULE, > > > > > > > > + .suppress_bind_attrs = true, > > > > > > > > + }, > > > > > > > > + .probe = tpdm_probe, > > > > > > > > + .id_table = tpdm_ids, > > > > > > > > +}; > > > > > > > > + > > > > > > > > +module_amba_driver(tpdm_driver); > > > > > > > > + > > > > > > > > +MODULE_LICENSE("GPL v2"); > > > > > > > > +MODULE_DESCRIPTION("Trace, Profiling & Diagnostic Monitor driver"); > > > > > > > > diff --git a/drivers/hwtracing/coresight/coresight-tpdm.h b/drivers/hwtracing/coresight/coresight-tpdm.h > > > > > > > > new file mode 100644 > > > > > > > > index 000000000000..980ae90ff1c8 > > > > > > > > --- /dev/null > > > > > > > > +++ b/drivers/hwtracing/coresight/coresight-tpdm.h > > > > > > > > @@ -0,0 +1,31 @@ > > > > > > > > +/* SPDX-License-Identifier: GPL-2.0 */ > > > > > > > > +/* > > > > > > > > + * Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved. > > > > > > > > + */ > > > > > > > > + > > > > > > > > +#ifndef _CORESIGHT_CORESIGHT_TPDM_H > > > > > > > > +#define _CORESIGHT_CORESIGHT_TPDM_H > > > > > > > > + > > > > > > > > +/* Default value of the traceid */ > > > > > > > > +#define TPDM_TRACE_ID_START 128 > > > > > > > > + > > > > > > > > +/** > > > > > > > > + * struct tpdm_drvdata - specifics associated to an TPDM component > > > > > > > > + * @base: memory mapped base address for this component. > > > > > > > > + * @dev: The device entity associated to this component. > > > > > > > > + * @csdev: component vitals needed by the framework. > > > > > > > > + * @lock: lock for the enable value. > > > > > > > > + * @enable: enable status of the component. > > > > > > > > + * @traceid: value of the current ID for this component. > > > > > > > > + */ > > > > > > > > + > > > > > > > > +struct tpdm_drvdata { > > > > > > > > + void __iomem *base; > > > > > > > > + struct device *dev; > > > > > > > > + struct coresight_device *csdev; > > > > > > > > + struct mutex lock; > > > > > > > > + bool enable; > > > > > > > > + int traceid; > > > > > > > > +}; > > > > > > > > + > > > > > > > > +#endif /* _CORESIGHT_CORESIGHT_TPDM_H */ > > > > > > > > diff --git a/include/linux/coresight.h b/include/linux/coresight.h > > > > > > > > index 93a2922b7653..e48d463be63b 100644 > > > > > > > > --- a/include/linux/coresight.h > > > > > > > > +++ b/include/linux/coresight.h > > > > > > > > @@ -65,6 +65,7 @@ enum coresight_dev_subtype_source { > > > > > > > > CORESIGHT_DEV_SUBTYPE_SOURCE_PROC, > > > > > > > > CORESIGHT_DEV_SUBTYPE_SOURCE_BUS, > > > > > > > > CORESIGHT_DEV_SUBTYPE_SOURCE_SOFTWARE, > > > > > > > > + CORESIGHT_DEV_SUBTYPE_SOURCE_SYS, > > > > > > > > }; > > > > > > > > > > > > > > > > enum coresight_dev_subtype_helper { > > > > > > > > -- > > > > > > > > 2.17.1 > > > > > > > > > > > > > > > > > > -- > > > > > Mike Leach > > > > > Principal Engineer, ARM Ltd. > > > > > Manchester Design Centre. UK

4 years

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