CoreSight

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Re: [PATCH 1/1] arm64: defconfig: Add Coresight as module

by James Clark

On 21/09/2022 17:46, Mathieu Poirier wrote: > On Wed, Sep 21, 2022 at 04:26:59PM +0100, Mark Brown wrote: >> On Wed, Sep 21, 2022 at 03:05:35PM +0100, James Clark wrote: >> >>> +CONFIG_CORESIGHT_CTI=m >>> +CONFIG_CORESIGHT_CTI_INTEGRATION_REGS=y >> > > I agree - integration registers should not be enabled by default. > >> Do we want this turned on by default? According to the >> description it's a bit dangerous and it's exposed via sysfs >> rather than debugfs. > > Should I disable just CONFIG_CORESIGHT_CTI_INTEGRATION_REGS or CONFIG_CORESIGHT_CTI as well? There are other writable registers exposed via sysfs outside of these two options, so I wanted to check if it's just the integration registers that are the issue.

3 years, 3 months

[PATCH 0/1] arm64: defconfig: Add Coresight as module

by James Clark

As suggested by Catalin here's the change to add Coresight to defconfig. Unfortunately I don't think we should add CONFIG_CORESIGHT_SOURCE_ETM4X which builds a few files until [1] is merged because of the overhead of CONFIG_PID_IN_CONTEXTIDR. [1]: https://lore.kernel.org/lkml/20211021134530.206216-1-leo.yan@linaro.org/T/ James Clark (1): arm64: defconfig: Add Coresight as module arch/arm64/configs/defconfig | 9 +++++++++ 1 file changed, 9 insertions(+) -- 2.28.0

3 years, 3 months

Re: coresight-etm4x-core.c:969:26: error: 'ID_AA64DFR0_TRACEVER_SHIFT' undeclared

by James Clark

On 20/09/2022 12:39, Naresh Kamboju wrote: > Following build warnings / errors noticed while building arm64 coresight > on linux next-20220919 and next-20220920. Fix is here: https://lists.linaro.org/archives/list/coresight@lists.linaro.org/thread/OS… > > Reported-by: Linux Kernel Functional Testing <lkft(a)linaro.org> > > make --silent --keep-going --jobs=8 > O=/home/tuxbuild/.cache/tuxmake/builds/1/build > CROSS_COMPILE_COMPAT=arm-linux-gnueabihf- ARCH=arm64 > CROSS_COMPILE=aarch64-linux-gnu- 'CC=sccache aarch64-linux-gnu-gcc' > 'HOSTCC=sccache gcc' > > drivers/hwtracing/coresight/coresight-etm4x-core.c: In function > 'cpu_supports_sysreg_trace': > drivers/hwtracing/coresight/coresight-etm4x-core.c:969:26: error: > 'ID_AA64DFR0_TRACEVER_SHIFT' undeclared (first use in this function); > did you mean 'ID_AA64DFR0_EL1_TraceVer_SHIFT'? > 969 | return ((dfr0 >> ID_AA64DFR0_TRACEVER_SHIFT) & 0xfUL) > 0; > | ^~~~~~~~~~~~~~~~~~~~~~~~~~ > | ID_AA64DFR0_EL1_TraceVer_SHIFT > drivers/hwtracing/coresight/coresight-etm4x-core.c:969:26: note: each > undeclared identifier is reported only once for each function it > appears in > drivers/hwtracing/coresight/coresight-etm4x-core.c: In function > 'cpu_detect_trace_filtering': > drivers/hwtracing/coresight/coresight-etm4x-core.c:1057:57: error: > 'ID_AA64DFR0_TRACE_FILT_SHIFT' undeclared (first use in this > function); did you mean 'ID_AA64PFR0_EL1_DIT_SHIFT'? > 1057 | if (!cpuid_feature_extract_unsigned_field(dfr0, > ID_AA64DFR0_TRACE_FILT_SHIFT)) > | > ^~~~~~~~~~~~~~~~~~~~~~~~~~~~ > | > ID_AA64PFR0_EL1_DIT_SHIFT > drivers/hwtracing/coresight/coresight-etm4x-core.c: In function > 'cpu_supports_sysreg_trace': > drivers/hwtracing/coresight/coresight-etm4x-core.c:970:1: error: > control reaches end of non-void function [-Werror=return-type] > 970 | } > | ^ > cc1: some warnings being treated as errors > > Regressions found on arm64: > - build-clang-13-lkftconfig > - build-gcc-11-lkftconfig-devicetree > - build-gcc-11-lkftconfig-kunit > - build-gcc-11-lkftconfig-perf > - build-gcc-11-lkftconfig-64k_page_size > - build-gcc-11-lkftconfig-debug > - build-gcc-11-lkftconfig-libgpiod > - build-gcc-11-lkftconfig-debug-kmemleak > - build-clang-14-lkftconfig > - build-clang-nightly-lkftconfig > - build-gcc-11-lkftconfig > - build-gcc-11-lkftconfig-kasan > - build-clang-12-lkftconfig > - build-gcc-11-lkftconfig-kselftest-kernel > - build-gcc-11-lkftconfig-rcutorture > - build-gcc-11-lkftconfig-armv8_features > - build-gcc-11-lkftconfig-kselftest > > Build: https://builds.tuxbuild.com/2F1cW8NpQ0Z6l9h9rfkZT5AXzqg/ > config: https://builds.tuxbuild.com/2F1cW8NpQ0Z6l9h9rfkZT5AXzqg/config > > > -- > Linaro LKFT > https://lkft.linaro.org > > _______________________________________________ > linux-arm-kernel mailing list > linux-arm-kernel(a)lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

3 years, 3 months

[PATCH] coresight: Use new autogenerated sysreg definitions

by James Clark

Fix the build by updating registers to use the new autogenerated format. Fixes: c0357a73fa4a ("arm64/sysreg: Align field names in ID_AA64DFR0_EL1 with architecture") Signed-off-by: James Clark <james.clark(a)arm.com> --- drivers/hwtracing/coresight/coresight-etm4x-core.c | 4 ++-- drivers/hwtracing/coresight/coresight-trbe.h | 3 ++- 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c index d39660a3e50c..80fefaba58ee 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c @@ -966,7 +966,7 @@ static inline bool cpu_supports_sysreg_trace(void) { u64 dfr0 = read_sysreg_s(SYS_ID_AA64DFR0_EL1); - return ((dfr0 >> ID_AA64DFR0_TRACEVER_SHIFT) & 0xfUL) > 0; + return ((dfr0 >> ID_AA64DFR0_EL1_TraceVer_SHIFT) & 0xfUL) > 0; } static bool etm4_init_sysreg_access(struct etmv4_drvdata *drvdata, @@ -1054,7 +1054,7 @@ static void cpu_detect_trace_filtering(struct etmv4_drvdata *drvdata) u64 trfcr; drvdata->trfcr = 0; - if (!cpuid_feature_extract_unsigned_field(dfr0, ID_AA64DFR0_TRACE_FILT_SHIFT)) + if (!cpuid_feature_extract_unsigned_field(dfr0, ID_AA64DFR0_EL1_TraceFilt_SHIFT)) return; /* diff --git a/drivers/hwtracing/coresight/coresight-trbe.h b/drivers/hwtracing/coresight/coresight-trbe.h index 30e4d7db4f8e..98ff1b17ad07 100644 --- a/drivers/hwtracing/coresight/coresight-trbe.h +++ b/drivers/hwtracing/coresight/coresight-trbe.h @@ -20,7 +20,8 @@ static inline bool is_trbe_available(void) { u64 aa64dfr0 = read_sysreg_s(SYS_ID_AA64DFR0_EL1); - unsigned int trbe = cpuid_feature_extract_unsigned_field(aa64dfr0, ID_AA64DFR0_TRBE_SHIFT); + unsigned int trbe = cpuid_feature_extract_unsigned_field(aa64dfr0, + ID_AA64DFR0_EL1_TraceBuffer_SHIFT); return trbe >= 0b0001; } -- 2.28.0

3 years, 3 months

[GIT PULL] Coresight changes for v6.1

by Suzuki K Poulose

Hi Greg, Please find the coresight self hosted trace subsystem updates for v6.1. Kindly consider pulling. Thanks Suzuki The following changes since commit 1c23f9e627a7b412978b4e852793c5e3c3efc555: Linux 6.0-rc2 (2022-08-21 17:32:54 -0700) are available in the Git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/coresight/linux.git tags/coresight-next-v6.1 for you to fetch changes up to 5fc1531dd771cd1481116a66f992a190e01efce6: hwtracing: hisi_ptt: Fix up for "iommu/dma: Make header private" (2022-09-12 10:12:25 -0600) ---------------------------------------------------------------- coresight: Changes for v6.1 Coresight trace subsystem updates for v6.1 includes: - Support for HiSilicon PTT trace - Coresight cleanup of sysfs accessor functions, reduced code size. - Expose coresight timestamp source for ETMv4+ - DT binding updates to include missing properties - Minor documentation, Kconfig text fixes. Signed-off-by: Suzuki K Poulose <suzuki.poulose(a)arm.com> ---------------------------------------------------------------- Christophe JAILLET (1): coresight: docs: Fix a broken reference German Gomez (2): coresight: etm4x: Expose default timestamp source in sysfs coresight: etm4x: docs: Add documentation for 'ts_source' sysfs interface James Clark (5): coresight: Remove unused function parameter coresight: Simplify sysfs accessors by using csdev_access abstraction coresight: Re-use same function for similar sysfs register accessors coresight: cti-sysfs: Re-use same functions for similar sysfs register accessors coresight: Make new csdev_access offsets unsigned Nathan Chancellor (1): coresight: cti-sysfs: Mark coresight_cti_reg_store() as __maybe_unused Randy Dunlap (1): coresight: trbe: fix Kconfig "its" grammar Rob Herring (2): dt-bindings: arm: coresight: Add 'power-domains' property dt-bindings: arm: coresight-tmc: Add 'iommu' property Stephen Rothwell (1): hwtracing: hisi_ptt: Fix up for "iommu/dma: Make header private" Yicong Yang (5): iommu/arm-smmu-v3: Make default domain type of HiSilicon PTT device to identity hwtracing: hisi_ptt: Add trace function support for HiSilicon PCIe Tune and Trace device hwtracing: hisi_ptt: Add tune function support for HiSilicon PCIe Tune and Trace device docs: trace: Add HiSilicon PTT device driver documentation MAINTAINERS: Add maintainer for HiSilicon PTT driver .../ABI/testing/sysfs-bus-coresight-devices-etm4x | 8 + Documentation/ABI/testing/sysfs-devices-hisi_ptt | 61 ++ .../bindings/arm/arm,coresight-catu.yaml | 3 + .../devicetree/bindings/arm/arm,coresight-cti.yaml | 3 + .../bindings/arm/arm,coresight-dynamic-funnel.yaml | 3 + .../arm/arm,coresight-dynamic-replicator.yaml | 3 + .../bindings/arm/arm,coresight-etb10.yaml | 3 + .../devicetree/bindings/arm/arm,coresight-etm.yaml | 3 + .../bindings/arm/arm,coresight-static-funnel.yaml | 3 + .../arm/arm,coresight-static-replicator.yaml | 3 + .../devicetree/bindings/arm/arm,coresight-stm.yaml | 3 + .../devicetree/bindings/arm/arm,coresight-tmc.yaml | 6 + .../bindings/arm/arm,coresight-tpiu.yaml | 3 + .../bindings/arm/arm,embedded-trace-extension.yaml | 3 + .../trace/coresight/coresight-cpu-debug.rst | 3 +- .../trace/coresight/coresight-etm4x-reference.rst | 14 + Documentation/trace/hisi-ptt.rst | 298 ++++++ Documentation/trace/index.rst | 1 + MAINTAINERS | 8 + arch/arm64/include/asm/sysreg.h | 1 + drivers/Makefile | 1 + drivers/hwtracing/Kconfig | 2 + drivers/hwtracing/coresight/Kconfig | 4 +- drivers/hwtracing/coresight/coresight-catu.c | 27 +- drivers/hwtracing/coresight/coresight-catu.h | 8 +- drivers/hwtracing/coresight/coresight-core.c | 28 + drivers/hwtracing/coresight/coresight-cti-sysfs.c | 213 ++-- drivers/hwtracing/coresight/coresight-etb10.c | 28 +- .../hwtracing/coresight/coresight-etm3x-sysfs.c | 34 +- .../hwtracing/coresight/coresight-etm4x-sysfs.c | 29 + drivers/hwtracing/coresight/coresight-priv.h | 72 +- drivers/hwtracing/coresight/coresight-replicator.c | 10 +- drivers/hwtracing/coresight/coresight-stm.c | 40 +- drivers/hwtracing/coresight/coresight-tmc-core.c | 48 +- drivers/hwtracing/coresight/coresight-tmc.h | 4 +- drivers/hwtracing/ptt/Kconfig | 12 + drivers/hwtracing/ptt/Makefile | 2 + drivers/hwtracing/ptt/hisi_ptt.c | 1046 ++++++++++++++++++++ drivers/hwtracing/ptt/hisi_ptt.h | 200 ++++ drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 21 + include/linux/coresight.h | 23 + 41 files changed, 1973 insertions(+), 312 deletions(-) create mode 100644 Documentation/ABI/testing/sysfs-devices-hisi_ptt create mode 100644 Documentation/trace/hisi-ptt.rst create mode 100644 drivers/hwtracing/ptt/Kconfig create mode 100644 drivers/hwtracing/ptt/Makefile create mode 100644 drivers/hwtracing/ptt/hisi_ptt.c create mode 100644 drivers/hwtracing/ptt/hisi_ptt.h

3 years, 3 months

Re: [PATCH] coresight: acpi: add support for amba dma-330 controller

by Suzuki K Poulose

Hi nit: on subject. This has no relation to CoreSight. This could be : acpi: amba: Add support for xyz. Suzuki

3 years, 3 months

Re: [PATCH 1/9] dt-bindings: arm: Add support for DSB element

by Tao Zhang

在 9/13/2022 8:48 AM, Rob Herring 写道: > On Thu, Sep 08, 2022 at 04:44:57PM +0800, Tao Zhang wrote: >> Add property "qcom,dsb-elem-size" to support DSB element for TPDA. >> Specifies the DSB element size supported by each monitor connected >> to the aggregator on each port. Should be specified in pairs (port, >> dsb element size). > What is DSB? The full name of DSB is "Discrete Single Bit". The DSB element size supported by different DSB subunit TPDMs is different, so TPDA needs to be informed through configuration in device tree. >> Signed-off-by: Tao Zhang <quic_taozha(a)quicinc.com> >> --- >> Documentation/devicetree/bindings/arm/qcom,coresight-tpda.yaml | 9 +++++++++ >> 1 file changed, 9 insertions(+) >> >> diff --git a/Documentation/devicetree/bindings/arm/qcom,coresight-tpda.yaml b/Documentation/devicetree/bindings/arm/qcom,coresight-tpda.yaml >> index eb9bfc5..1bb3fdf 100644 >> --- a/Documentation/devicetree/bindings/arm/qcom,coresight-tpda.yaml >> +++ b/Documentation/devicetree/bindings/arm/qcom,coresight-tpda.yaml >> @@ -40,6 +40,13 @@ properties: >> minItems: 1 >> maxItems: 2 >> >> + qcom,dsb-elem-size: >> + description: | >> + Specifies the DSB element size supported by each monitor >> + connected to the aggregator on each port. Should be specified >> + in pairs (port, dsb element size). >> + $ref: /schemas/types.yaml#/definitions/uint32-array > The binding (not yet upstream) says there is just 1 port (port 0). So > why do you need more than a single uint32? > > Rob TPDA(Trace, Profiling and Diagnostics Aggregator) is to provide packetization, funneling and timestamping of TPDM data. Multiple monitors are connected to different input ports of TPDA. - - - - - - - - - - - - | TPDM 0| | TPDM 1 | | TPDM 2| - - - - - - - - - - - - | | | |_ _ _ _ _ _ | _ _ _ _ | | | | | | | ------------------ | TPDA | ------------------ There may be multiple DSB subunit TPDMs connected to different input ports of the same TPDA, so we need to use port here to define the distinction in device tree. Best regards, Tao

3 years, 3 months

Re: [PATCH 1/9] dt-bindings: arm: Add support for DSB element

by Tao Zhang

在 9/8/2022 6:54 PM, Krzysztof Kozlowski 写道: > On 08/09/2022 10:44, Tao Zhang wrote: >> Add property "qcom,dsb-elem-size" to support DSB element for TPDA. >> Specifies the DSB element size supported by each monitor connected >> to the aggregator on each port. Should be specified in pairs (port, >> dsb element size). >> >> Signed-off-by: Tao Zhang <quic_taozha(a)quicinc.com> >> --- >> Documentation/devicetree/bindings/arm/qcom,coresight-tpda.yaml | 9 +++++++++ >> 1 file changed, 9 insertions(+) >> >> diff --git a/Documentation/devicetree/bindings/arm/qcom,coresight-tpda.yaml b/Documentation/devicetree/bindings/arm/qcom,coresight-tpda.yaml >> index eb9bfc5..1bb3fdf 100644 >> --- a/Documentation/devicetree/bindings/arm/qcom,coresight-tpda.yaml >> +++ b/Documentation/devicetree/bindings/arm/qcom,coresight-tpda.yaml >> @@ -40,6 +40,13 @@ properties: >> minItems: 1 >> maxItems: 2 >> >> + qcom,dsb-elem-size: >> + description: | >> + Specifies the DSB element size supported by each monitor >> + connected to the aggregator on each port. Should be specified >> + in pairs (port, dsb element size). >> + $ref: /schemas/types.yaml#/definitions/uint32-array > So it is rather uint32-matrix (need to describe the items subschema). > What about maxItems? > > Best regards, > Krzysztof Yes, indeed it should be uint32-matrix here. I will update in the next release. The "maxItems" cannot be known explicitly because it depends on how many DSB subunit TPDMs are connected to the TPDA input ports. Usually the number of the items is 1 to several, but there is no limit to its maximum value. Best regards, Tao

3 years, 3 months

Re: [PATCH] coresight: docs: Fix a broken reference

by Suzuki K Poulose

Cc: acme On 22/08/2022 17:02, Mathieu Poirier wrote: > On Sun, Jul 31, 2022 at 09:06:48AM +0200, Christophe JAILLET wrote: >> Since the commit in Fixes: tag, "coresight-cpu-debug.txt" has been turned >> into "arm,coresight-cpu-debug.yaml". >> >> Update the doc accordingly to avoid a 'make htmldocs' warning >> >> Fixes: 66d052047ca8 ("dt-bindings: arm: Convert CoreSight CPU debug to DT schema") >> Signed-off-by: Christophe JAILLET <christophe.jaillet(a)wanadoo.fr> >> --- >> Documentation/trace/coresight/coresight-cpu-debug.rst | 3 ++- >> 1 file changed, 2 insertions(+), 1 deletion(-) >> > > Applied. fyi, there is another patch fixing the same here. https://lkml.kernel.org/r/20815dbff3d27f5d3e6876363f052d2a08ad2e72.16608294… We may have to decide which one goes in. Cheers Suzuki > > Thanks, > Mathieu > >> diff --git a/Documentation/trace/coresight/coresight-cpu-debug.rst b/Documentation/trace/coresight/coresight-cpu-debug.rst >> index 993dd294b81b..836b35532667 100644 >> --- a/Documentation/trace/coresight/coresight-cpu-debug.rst >> +++ b/Documentation/trace/coresight/coresight-cpu-debug.rst >> @@ -117,7 +117,8 @@ divide into below cases: >> Device Tree Bindings >> -------------------- >> >> -See Documentation/devicetree/bindings/arm/coresight-cpu-debug.txt for details. >> +See Documentation/devicetree/bindings/arm/arm,coresight-cpu-debug.yaml for >> +details. >> >> >> How to use the module >> -- >> 2.34.1 >>

3 years, 3 months

Re: [PATCH 06/13] Documentation: coresight: fix a documentation build warning

by Suzuki K Poulose

On 18/08/2022 14:38, Mauro Carvalho Chehab wrote: > Using wildcards for cross-reference doesn't work, as the Sphinx > automarkup plugin is not smart enough. So, changeset > c06475910b52 ("Documentation: coresight: Escape coresight bindings file wildcard") > tried to fix it, but at the wrong way, as it the building system > will keep producing warnings about that: > > Warning: Documentation/trace/coresight/coresight.rst references a file that doesn't exist: Documentation/devicetree/bindings/arm/arm,coresight- > > As automarkup will still try (and fail) to create a cross reference. > So, instead, change the markup to ensure that the warning won't be > reported. > > Fixes: c06475910b52 ("Documentation: coresight: Escape coresight bindings file wildcard") > Cc: Bagas Sanjaya <bagasdotme(a)gmail.com> > Signed-off-by: Mauro Carvalho Chehab <mchehab(a)kernel.org> Acked-by: Suzuki K Poulose <suzuki.poulose(a)arm.com> > --- > > See [PATCH 00/13] at: https://lore.kernel.org/all/cover.1660829433.git.mchehab@kernel.org/ > > Documentation/trace/coresight/coresight.rst | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/Documentation/trace/coresight/coresight.rst b/Documentation/trace/coresight/coresight.rst > index 4a71ea6cb390..826e59a698da 100644 > --- a/Documentation/trace/coresight/coresight.rst > +++ b/Documentation/trace/coresight/coresight.rst > @@ -130,7 +130,7 @@ Misc: > Device Tree Bindings > -------------------- > > -See Documentation/devicetree/bindings/arm/arm,coresight-\*.yaml for details. > +See ``Documentation/devicetree/bindings/arm/arm,coresight-*.yaml`` for details. > > As of this writing drivers for ITM, STMs and CTIs are not provided but are > expected to be added as the solution matures.

3 years, 3 months

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