CoreSight

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6 participants
2351 discussions

[GIT PULL] Coresight subsystem for v5.16

by Mathieu Poirier

The following changes since commit 5816b3e6577eaa676ceb00a848f0fd65fe2adc29: Linux 5.15-rc3 (2021-09-26 14:08:19 -0700) are available in the Git repository at: git@gitolite.kernel.org:pub/scm/linux/kernel/git/coresight/linux.git tags/v5.16-next for you to fetch changes up to 7cf0754113f7ed6fad999483e40d95985c987353: arm64: errata: Enable TRBE workaround for write to out-of-range address (2021-10-25 12:06:02 -0600) ---------------------------------------------------------------- Hi Greg, Please consider these for the next merge window. Also let me know if there is any modifications I can do to this pull request to make things easier on your side. Thanks, Mathieu Included herein: - A new option to make coresight cpu-debug capabilities available as early as possible in the kernel boot process. - Make trace sessions more enduring by coping with scenarios where events are scheduled on CPUs that can't reach the selected sink. - A set of improvement to make the TMC-ETR driver more efficient. - Enhancements to the TRBE driver to correct several errata. - An enhancement to make the AXI burts size configurable for TMC devices that can't work with the default value. - A fix in the CTI module to use the correct device when calling pm_runtime_put() - The addition of the Kryo-5xx device to the list of support ETMs. ---------------------------------------------------------------- Brian Norris (1): coresight: cpu-debug: Control default behavior via Kconfig James Clark (1): coresight: Don't immediately close events that are run on invalid CPU/sink combos Leo Yan (5): coresight: tmc-etr: Add barrier after updating AUX ring buffer coresight: tmc-etf: Add comment for store ordering coresight: tmc-etr: Use perf_output_handle::head for AUX ring buffer coresight: Update comments for removing cs_etm_find_snapshot() coresight: tmc-etr: Speed up for bounce buffer in flat mode Suzuki K Poulose (28): arm64: Add Neoverse-N2, Cortex-A710 CPU part definition arm64: errata: Add detection for TRBE overwrite in FILL mode arm64: errata: Add workaround for TSB flush failures arm64: errata: Add detection for TRBE write to out-of-range coresight: etm4x: Save restore TRFCR_EL1 coresight: etm4x: Use Trace Filtering controls dynamically coresight: etm-pmu: Ensure the AUX handle is valid coresight: trbe: Ensure the format flag is always set coresight: trbe: Drop duplicate TRUNCATE flags coresight: trbe: Unify the enabling sequence coresight: trbe: irq handler: Do not disable TRBE if no action is needed coresight: trbe: Fix handling of spurious interrupts coresight: trbe: Do not truncate buffer on IRQ coresight: trbe: End the AUX handle on truncation coresight: trbe: Prohibit trace before disabling TRBE coresight: trbe: Fix incorrect access of the sink specific data coresight: trbe: Defer the probe on offline CPUs coresight: trbe: Add a helper to calculate the trace generated coresight: trbe: Add a helper to pad a given buffer area coresight: trbe: Decouple buffer base from the hardware base coresight: trbe: Allow driver to choose a different alignment coresight: trbe: Add infrastructure for Errata handling coresight: trbe: Workaround TRBE errata overwrite in FILL mode coresight: trbe: Add a helper to determine the minimum buffer size coresight: trbe: Make sure we have enough space coresight: trbe: Work around write to out of range arm64: errata: Enable workaround for TRBE overwrite in FILL mode arm64: errata: Enable TRBE workaround for write to out-of-range address Tanmay Jagdale (2): dt-bindings: coresight: Add burst size for TMC coresight: tmc: Configure AXI write burst size Tao Zhang (2): coresight: cti: Correct the parameter for pm_runtime_put coresight: etm4x: Add ETM PID for Kryo-5XX Documentation/arm64/silicon-errata.rst | 12 + .../devicetree/bindings/arm/coresight.txt | 5 + arch/arm64/Kconfig | 111 +++++ arch/arm64/include/asm/barrier.h | 16 +- arch/arm64/include/asm/cputype.h | 4 + arch/arm64/kernel/cpu_errata.c | 64 +++ arch/arm64/tools/cpucaps | 3 + drivers/hwtracing/coresight/Kconfig | 13 + drivers/hwtracing/coresight/coresight-cpu-debug.c | 2 +- drivers/hwtracing/coresight/coresight-cti-core.c | 2 +- drivers/hwtracing/coresight/coresight-etb10.c | 5 +- drivers/hwtracing/coresight/coresight-etm-perf.c | 56 ++- drivers/hwtracing/coresight/coresight-etm4x-core.c | 101 +++- drivers/hwtracing/coresight/coresight-etm4x.h | 9 +- .../coresight/coresight-self-hosted-trace.h | 33 ++ drivers/hwtracing/coresight/coresight-tmc-core.c | 21 +- drivers/hwtracing/coresight/coresight-tmc-etf.c | 10 +- drivers/hwtracing/coresight/coresight-tmc-etr.c | 52 +- drivers/hwtracing/coresight/coresight-tmc.h | 6 +- drivers/hwtracing/coresight/coresight-trbe.c | 534 +++++++++++++++++---- 20 files changed, 905 insertions(+), 154 deletions(-) create mode 100644 drivers/hwtracing/coresight/coresight-self-hosted-trace.h

3 years, 6 months

Re: [PATCH v6 00/15] arm64: Self-hosted trace related errata workarounds

by Mathieu Poirier

On Fri, Oct 22, 2021 at 09:14:38AM +0200, Greg KH wrote: > On Thu, Oct 21, 2021 at 05:47:31PM +0100, Will Deacon wrote: > > Hi Mathieu, > > > > [CC Greg] > > > > On Thu, Oct 21, 2021 at 10:35:31AM -0600, Mathieu Poirier wrote: > > > On Thu, Oct 21, 2021 at 09:53:14AM +0100, Will Deacon wrote: > > > > On Wed, Oct 20, 2021 at 09:42:07AM -0600, Mathieu Poirier wrote: > > > > > On Tue, Oct 19, 2021 at 05:31:38PM +0100, Suzuki K Poulose wrote: > > > > > > Suzuki K Poulose (15): > > > > > > arm64: Add Neoverse-N2, Cortex-A710 CPU part definition > > > > > > arm64: errata: Add detection for TRBE overwrite in FILL mode > > > > > > arm64: errata: Add workaround for TSB flush failures > > > > > > arm64: errata: Add detection for TRBE write to out-of-range > > > > > > coresight: trbe: Add a helper to calculate the trace generated > > > > > > coresight: trbe: Add a helper to pad a given buffer area > > > > > > coresight: trbe: Decouple buffer base from the hardware base > > > > > > coresight: trbe: Allow driver to choose a different alignment > > > > > > coresight: trbe: Add infrastructure for Errata handling > > > > > > coresight: trbe: Workaround TRBE errata overwrite in FILL mode > > > > > > coresight: trbe: Add a helper to determine the minimum buffer size > > > > > > coresight: trbe: Make sure we have enough space > > > > > > coresight: trbe: Work around write to out of range > > > > > > arm64: errata: Enable workaround for TRBE overwrite in FILL mode > > > > > > arm64: errata: Enable TRBE workaround for write to out-of-range > > > > > > address > > > > > > > > > > > > Documentation/arm64/silicon-errata.rst | 12 + > > > > > > arch/arm64/Kconfig | 111 ++++++ > > > > > > arch/arm64/include/asm/barrier.h | 16 +- > > > > > > arch/arm64/include/asm/cputype.h | 4 + > > > > > > arch/arm64/kernel/cpu_errata.c | 64 +++ > > > > > > arch/arm64/tools/cpucaps | 3 + > > > > > > drivers/hwtracing/coresight/coresight-trbe.c | 394 +++++++++++++++++-- > > > > > > 7 files changed, 567 insertions(+), 37 deletions(-) > > > > > > > > > > I have applied this set. > > > > > > > > Mathieu -- the plan here (which we have discussed on the list [1]) is > > > > for the first four patches to be shared with arm64. Since you've gone > > > > ahead and applied the whole series, please can you provide me a stable > > > > branch with the first four patches only so that I can include them in > > > > the arm64 tree? > > > > > > > > Failing that, I can create a branch for you to pull and apply the remaining > > > > patches on top. > > > > > > > > Please let me know. > > > > > > Coresight patches flow through Greg's tree and as such the coresight-next tree > > > gets rebased anyway. I will remove the first 4 patches and push again. By the > > > way do you also want to pick up patches 14 and 16 since they are concerned with > > > "arch/arm64/Kconfig" or should I keep them? > > > > I'll take the first 4 and put them on a stable branch, which you can choose > > to pull if you like (but please don't rebase it or we'll end up with > > duplicate commits). The rest of the patches, including the later Kconfig > > changes, are yours but I doubt they'll apply cleanly without the initial > > changes. > > > > Are you sure Greg rebases everything? That sounds a bit weird to me, as it > > means it's impossible to share branches with other trees. How do you usually > > handle this situation? > > No, I never rebase my trees. For coresight patches I take them as > emailed patches due to previous history requiring me to review them all > myself. If this is an issue here, I can always take a pull request as > long as you all don't want my review :) Can you expand on the "previous history requiring" you to review coresight patches? Rebasing the coresight-next tree when patches are pulled in the char-misc tree causes problems when features involve other subsystems. I definitely appreciate reviews of coresight patches from anyone. The subsystem has grown to be very complex and more reviewers mean higher probabilities of catching problems. There has to be a way for that to continue while making it easier to collaborate with other subsystems. For this particular patchset, Will has picked up the first 4 patches, I will pick up patches 5 to 13 and patches 14 and 15 will have to go in the next cycle. I doubt this is the best we can do. Regards, Mathieu > > thanks, > > greg k-h

3 years, 6 months

Re: [PATCH v6 00/15] arm64: Self-hosted trace related errata workarounds

by Mathieu Poirier

On Thu, 21 Oct 2021 at 10:47, Will Deacon <will(a)kernel.org> wrote: > > Hi Mathieu, > > [CC Greg] > > On Thu, Oct 21, 2021 at 10:35:31AM -0600, Mathieu Poirier wrote: > > On Thu, Oct 21, 2021 at 09:53:14AM +0100, Will Deacon wrote: > > > On Wed, Oct 20, 2021 at 09:42:07AM -0600, Mathieu Poirier wrote: > > > > On Tue, Oct 19, 2021 at 05:31:38PM +0100, Suzuki K Poulose wrote: > > > > > Suzuki K Poulose (15): > > > > > arm64: Add Neoverse-N2, Cortex-A710 CPU part definition > > > > > arm64: errata: Add detection for TRBE overwrite in FILL mode > > > > > arm64: errata: Add workaround for TSB flush failures > > > > > arm64: errata: Add detection for TRBE write to out-of-range > > > > > coresight: trbe: Add a helper to calculate the trace generated > > > > > coresight: trbe: Add a helper to pad a given buffer area > > > > > coresight: trbe: Decouple buffer base from the hardware base > > > > > coresight: trbe: Allow driver to choose a different alignment > > > > > coresight: trbe: Add infrastructure for Errata handling > > > > > coresight: trbe: Workaround TRBE errata overwrite in FILL mode > > > > > coresight: trbe: Add a helper to determine the minimum buffer size > > > > > coresight: trbe: Make sure we have enough space > > > > > coresight: trbe: Work around write to out of range > > > > > arm64: errata: Enable workaround for TRBE overwrite in FILL mode > > > > > arm64: errata: Enable TRBE workaround for write to out-of-range > > > > > address > > > > > > > > > > Documentation/arm64/silicon-errata.rst | 12 + > > > > > arch/arm64/Kconfig | 111 ++++++ > > > > > arch/arm64/include/asm/barrier.h | 16 +- > > > > > arch/arm64/include/asm/cputype.h | 4 + > > > > > arch/arm64/kernel/cpu_errata.c | 64 +++ > > > > > arch/arm64/tools/cpucaps | 3 + > > > > > drivers/hwtracing/coresight/coresight-trbe.c | 394 +++++++++++++++++-- > > > > > 7 files changed, 567 insertions(+), 37 deletions(-) > > > > > > > > I have applied this set. > > > > > > Mathieu -- the plan here (which we have discussed on the list [1]) is > > > for the first four patches to be shared with arm64. Since you've gone > > > ahead and applied the whole series, please can you provide me a stable > > > branch with the first four patches only so that I can include them in > > > the arm64 tree? > > > > > > Failing that, I can create a branch for you to pull and apply the remaining > > > patches on top. > > > > > > Please let me know. > > > > Coresight patches flow through Greg's tree and as such the coresight-next tree > > gets rebased anyway. I will remove the first 4 patches and push again. By the > > way do you also want to pick up patches 14 and 16 since they are concerned with > > "arch/arm64/Kconfig" or should I keep them? > > I'll take the first 4 and put them on a stable branch, which you can choose > to pull if you like (but please don't rebase it or we'll end up with > duplicate commits). The rest of the patches, including the later Kconfig > changes, are yours but I doubt they'll apply cleanly without the initial > changes. Right - I just had another look at them and what I suggested above won't work. > > Are you sure Greg rebases everything? That sounds a bit weird to me, as it > means it's impossible to share branches with other trees. How do you usually > handle this situation? Greg applies the patches I send to him near the end of every cycle - see this one [1] as an example. Unfortunately that way of working makes it hard to deal with patchsets such as this one. To move forward you can either pick up this whole series (just add my RB to all the CS patches) or I start sending pull requests to Greg. Greg - what's your take on this? [1]. https://www.spinics.net/lists/arm-kernel/msg915961.html > > Will

3 years, 6 months

Re: [PATCH v6 00/15] arm64: Self-hosted trace related errata workarounds

by Mathieu Poirier

On Thu, Oct 21, 2021 at 09:53:14AM +0100, Will Deacon wrote: > On Wed, Oct 20, 2021 at 09:42:07AM -0600, Mathieu Poirier wrote: > > On Tue, Oct 19, 2021 at 05:31:38PM +0100, Suzuki K Poulose wrote: > > > Suzuki K Poulose (15): > > > arm64: Add Neoverse-N2, Cortex-A710 CPU part definition > > > arm64: errata: Add detection for TRBE overwrite in FILL mode > > > arm64: errata: Add workaround for TSB flush failures > > > arm64: errata: Add detection for TRBE write to out-of-range > > > coresight: trbe: Add a helper to calculate the trace generated > > > coresight: trbe: Add a helper to pad a given buffer area > > > coresight: trbe: Decouple buffer base from the hardware base > > > coresight: trbe: Allow driver to choose a different alignment > > > coresight: trbe: Add infrastructure for Errata handling > > > coresight: trbe: Workaround TRBE errata overwrite in FILL mode > > > coresight: trbe: Add a helper to determine the minimum buffer size > > > coresight: trbe: Make sure we have enough space > > > coresight: trbe: Work around write to out of range > > > arm64: errata: Enable workaround for TRBE overwrite in FILL mode > > > arm64: errata: Enable TRBE workaround for write to out-of-range > > > address > > > > > > Documentation/arm64/silicon-errata.rst | 12 + > > > arch/arm64/Kconfig | 111 ++++++ > > > arch/arm64/include/asm/barrier.h | 16 +- > > > arch/arm64/include/asm/cputype.h | 4 + > > > arch/arm64/kernel/cpu_errata.c | 64 +++ > > > arch/arm64/tools/cpucaps | 3 + > > > drivers/hwtracing/coresight/coresight-trbe.c | 394 +++++++++++++++++-- > > > 7 files changed, 567 insertions(+), 37 deletions(-) > > > > I have applied this set. > > Mathieu -- the plan here (which we have discussed on the list [1]) is > for the first four patches to be shared with arm64. Since you've gone > ahead and applied the whole series, please can you provide me a stable > branch with the first four patches only so that I can include them in > the arm64 tree? > > Failing that, I can create a branch for you to pull and apply the remaining > patches on top. > > Please let me know. Coresight patches flow through Greg's tree and as such the coresight-next tree gets rebased anyway. I will remove the first 4 patches and push again. By the way do you also want to pick up patches 14 and 16 since they are concerned with "arch/arm64/Kconfig" or should I keep them? Thanks, Mathieu > > Thanks, > > Will > > [1] https://lore.kernel.org/all/20211008073229.GB32625@willie-the-truck/

3 years, 6 months

[PATCH v6 00/15] arm64: Self-hosted trace related errata workarounds

by Suzuki K Poulose

This series adds CPU erratum work arounds related to the self-hosted tracing. The list of affected errata handled in this series are : * TRBE may overwrite trace in FILL mode - Arm Neoverse-N2 #2139208 - Cortex-A710 #211985 * A TSB instruction may not flush the trace completely when executed in trace prohibited region. - Arm Neoverse-N2 #2067961 - Cortex-A710 #2054223 * TRBE may write to out-of-range address - Arm Neoverse-N2 #2253138 - Cortex-A710 #2224489 The series applies on coresight/next. The series has been reordered to make it easier to merge the patches via arm64 tree and the coresight tree. Patches 1-4 are could be picked up via arm64 tree. The rest can go via the coresight tree. The Kconfig items for the TRBE errata are initially dropped in with dependency on COMPILE_TEST. These are dropped only after the driver is equipped with the work around in later patches. A tree is available here : git@git.gitlab.arm.com:linux-arm/linux-skp.git coresight/errata/trbe-tsb-n2-a710/v6 Changes since v5: * https://lkml.kernel.org/r/20211014223125.2605031-1-suzuki.poulose@arm.com - Fix typo in the Kconfig symbol usage in errata listing (Will) - Fix typo in commit description for "arm64: errata: Add detection for TRBE overwrite in FILL mode" - Fix commit description checkpatch warnings on column length for: "arm64: errata: Add detection for TRBE write to out-of-range" - Collected Reviews/Acks from Mathieu/Anshuman/Will Changes since v4: * https://lkml.kernel.org/r/20211012131743.2040596-1-suzuki.poulose@arm.com - Fix WARN on trbe driver probe on a hotplugged CPU, by making sure that the arm_trbe_probe_cpu() is called from non-premptible context. this_cpu_has_cap() doesn't like to be called from a preemptible() context. - Fix Kconfig text issues pointed out by Randy Changes since v3: - Fix missing Kconfig selection for TSB flush failure erratum (Will) Merged the Kconfig changes to the core patch for TSB. - Use COMPILE_TEST dependency for the TRBE work arounds instead of delaying the Kconfig entries. Changes since v2: * https://lkml.kernel.org/r/20210921134121.2423546-1-suzuki.poulose@arm.com - Dropped patch adding a helper to reach cpudata from perf handle - Split the TSB erratum work around patch to split the Kconfig/erratum list update changes(pushed to the end of the series). - Added wrappers to check the erratum : trbe_has_erratum(cpudata, TRBE_ERRATUM_<TITLE>) -> trbe_may_<title> - More ASCII art explanation on workaround. Changes since v1: * https://lkml.kernel.org/r/20210728135217.591173-1-suzuki.poulose@arm.com - Added a fix to the TRBE driver handling of sink_specific data - Added more description and ASCII art for overwrite in FILL mode work around - Added another TRBE erratum to the list. "TRBE may write to out-of-range address" Patches from 12-17 - Added comment to list the expectations around TSB erratum workaround. Suzuki K Poulose (15): arm64: Add Neoverse-N2, Cortex-A710 CPU part definition arm64: errata: Add detection for TRBE overwrite in FILL mode arm64: errata: Add workaround for TSB flush failures arm64: errata: Add detection for TRBE write to out-of-range coresight: trbe: Add a helper to calculate the trace generated coresight: trbe: Add a helper to pad a given buffer area coresight: trbe: Decouple buffer base from the hardware base coresight: trbe: Allow driver to choose a different alignment coresight: trbe: Add infrastructure for Errata handling coresight: trbe: Workaround TRBE errata overwrite in FILL mode coresight: trbe: Add a helper to determine the minimum buffer size coresight: trbe: Make sure we have enough space coresight: trbe: Work around write to out of range arm64: errata: Enable workaround for TRBE overwrite in FILL mode arm64: errata: Enable TRBE workaround for write to out-of-range address Documentation/arm64/silicon-errata.rst | 12 + arch/arm64/Kconfig | 111 ++++++ arch/arm64/include/asm/barrier.h | 16 +- arch/arm64/include/asm/cputype.h | 4 + arch/arm64/kernel/cpu_errata.c | 64 +++ arch/arm64/tools/cpucaps | 3 + drivers/hwtracing/coresight/coresight-trbe.c | 394 +++++++++++++++++-- 7 files changed, 567 insertions(+), 37 deletions(-) -- 2.25.4

3 years, 6 months

[PATCH v5 00/15] arm64: Self-hosted trace related errata workarounds

by Suzuki K Poulose

This series adds CPU erratum work arounds related to the self-hosted tracing. The list of affected errata handled in this series are : * TRBE may overwrite trace in FILL mode - Arm Neoverse-N2 #2139208 - Cortex-A710 #211985 * A TSB instruction may not flush the trace completely when executed in trace prohibited region. - Arm Neoverse-N2 #2067961 - Cortex-A710 #2054223 * TRBE may write to out-of-range address - Arm Neoverse-N2 #2253138 - Cortex-A710 #2224489 The series applies on coresight/next. The series has been reordered to make it easier to merge the patches via arm64 tree and the coresight tree. Patches 1-4 are could be picked up via arm64 tree. The rest can go via the coresight tree. The Kconfig items for the TRBE errata are initially dropped in with dependency on COMPILE_TEST. These are dropped only after the driver is equipped with the work around in later patches. A tree is available here : git@git.gitlab.arm.com:linux-arm/linux-skp.git coresight/errata/trbe-tsb-n2-a710/v5 Changes since v4: - Fix WARN on trbe driver probe on a hotplugged CPU, by making sure that the arm_trbe_probe_cpu() is called from non-premptible context. this_cpu_has_cap() doesn't like to be called from a preemptible() context. - Fix Kconfig text issues pointed out by Randy Changes since v3: - Fix missing Kconfig selection for TSB flush failure erratum (Will) Merged the Kconfig changes to the core patch for TSB. - Use COMPILE_TEST dependency for the TRBE work arounds instead of delaying the Kconfig entries. Changes since v2: * https://lkml.kernel.org/r/20210921134121.2423546-1-suzuki.poulose@arm.com - Dropped patch adding a helper to reach cpudata from perf handle - Split the TSB erratum work around patch to split the Kconfig/erratum list update changes(pushed to the end of the series). - Added wrappers to check the erratum : trbe_has_erratum(cpudata, TRBE_ERRATUM_<TITLE>) -> trbe_may_<title> - More ASCII art explanation on workaround. Changes since v1: * https://lkml.kernel.org/r/20210728135217.591173-1-suzuki.poulose@arm.com - Added a fix to the TRBE driver handling of sink_specific data - Added more description and ASCII art for overwrite in FILL mode work around - Added another TRBE erratum to the list. "TRBE may write to out-of-range address" Patches from 12-17 - Added comment to list the expectations around TSB erratum workaround. Suzuki K Poulose (15): arm64: Add Neoverse-N2, Cortex-A710 CPU part definition arm64: errata: Add detection for TRBE overwrite in FILL mode arm64: errata: Add workaround for TSB flush failures arm64: errata: Add detection for TRBE write to out-of-range coresight: trbe: Add a helper to calculate the trace generated coresight: trbe: Add a helper to pad a given buffer area coresight: trbe: Decouple buffer base from the hardware base coresight: trbe: Allow driver to choose a different alignment coresight: trbe: Add infrastructure for Errata handling coresight: trbe: Workaround TRBE errata overwrite in FILL mode coresight: trbe: Add a helper to determine the minimum buffer size coresight: trbe: Make sure we have enough space coresight: trbe: Work around write to out of range arm64: errata: Enable workaround for TRBE overwrite in FILL mode arm64: errata: Enable TRBE workaround for write to out-of-range address Documentation/arm64/silicon-errata.rst | 12 + arch/arm64/Kconfig | 111 ++++++ arch/arm64/include/asm/barrier.h | 16 +- arch/arm64/include/asm/cputype.h | 4 + arch/arm64/kernel/cpu_errata.c | 64 +++ arch/arm64/tools/cpucaps | 3 + drivers/hwtracing/coresight/coresight-trbe.c | 395 +++++++++++++++++-- 7 files changed, 567 insertions(+), 38 deletions(-) -- 2.25.4

3 years, 6 months

Re: [PATCH v5 03/15] arm64: errata: Add workaround for TSB flush failures

by Suzuki K Poulose

On 19/10/2021 12:42, Will Deacon wrote: > On Tue, Oct 19, 2021 at 12:36:48PM +0100, Suzuki K Poulose wrote: >> On 19/10/2021 12:02, Will Deacon wrote: >>> On Thu, Oct 14, 2021 at 11:31:13PM +0100, Suzuki K Poulose wrote: >>>> @@ -558,6 +570,13 @@ const struct arm64_cpu_capabilities arm64_errata[] = { >>>> .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, >>>> CAP_MIDR_RANGE_LIST(trbe_overwrite_fill_mode_cpus), >>>> }, >>>> +#endif >>>> +#ifdef CONFIG_ARM64_WORKAROUND_TSB_FLUSH_FAILRE >>> >>> You still haven't fixed this typo... >>> >> >> Sorry about that. I thought it was about selecting the >> Kconfig entries, which was fixed. I will fix this. > > Sorry, I thought it was such a howler that it would've jumped out ;) > That's what made me think we should make sure the series compiles without > the coresight changes, so we can catch these problems early. > >>> Seriously, I get compile warnings from this -- are you not seeing them? >> >> No, I don't get any warnings. Is there something that I am missing ? > > Interesting. I see the warning below in my bisection testing, since the typo > means that the midr lookup table isn't used. Maybe you're only compiling the > end result? No, I was compiling this at the commit. Also, please note that the TSB flush failure config is enabled with the patch, unlike the TRBE errata ones. My GCC is : gcc version 9.3.1 20200408 (Red Hat 9.3.1-2) (GCC) $ grep TSB arch/arm64/Kconfig arch/arm64/kernel/cpu_errata.c .config arch/arm64/Kconfig:config ARM64_WORKAROUND_TSB_FLUSH_FAILURE arch/arm64/Kconfig: bool "Cortex-A710: 2054223: workaround TSB instruction failing to flush trace" arch/arm64/Kconfig: select ARM64_WORKAROUND_TSB_FLUSH_FAILURE arch/arm64/Kconfig: Affected cores may fail to flush the trace data on a TSB instruction, when arch/arm64/Kconfig: Workaround is to issue two TSB consecutively on affected cores. arch/arm64/Kconfig: bool "Neoverse-N2: 2067961: workaround TSB instruction failing to flush trace" arch/arm64/Kconfig: select ARM64_WORKAROUND_TSB_FLUSH_FAILURE arch/arm64/Kconfig: Affected cores may fail to flush the trace data on a TSB instruction, when arch/arm64/Kconfig: Workaround is to issue two TSB consecutively on affected cores. arch/arm64/kernel/cpu_errata.c:#ifdef CONFIG_ARM64_WORKAROUND_TSB_FLUSH_FAILURE arch/arm64/kernel/cpu_errata.c:#endif /* CONFIG_ARM64_WORKAROUND_TSB_FLUSH_FAILURE */ arch/arm64/kernel/cpu_errata.c:#ifdef CONFIG_ARM64_WORKAROUND_TSB_FLUSH_FAILRE arch/arm64/kernel/cpu_errata.c: .capability = ARM64_WORKAROUND_TSB_FLUSH_FAILURE, .config:CONFIG_ARM64_WORKAROUND_TSB_FLUSH_FAILURE=y suzuki@ewhatever:coresight$ git log --oneline -1 89e0c94bd734 (HEAD) arm64: errata: Add workaround for TSB flush failures > > Will > > --->8 > > +arch/arm64/kernel/cpu_errata.c:356:32: warning: ‘tsb_flush_fail_cpus’ defined but not used [-Wunused-const-variable=] > + 356 | static const struct midr_range tsb_flush_fail_cpus[] = { > + | ^~~~~~~~~~~~~~~~~~~ > That looks a valid warning. Hmm, strange. It does complain for an unused function though. $ make -j16 CALL scripts/atomic/check-atomics.sh CALL scripts/checksyscalls.sh CHK include/generated/compile.h CC arch/arm64/kernel/cpu_errata.o arch/arm64/kernel/cpu_errata.c:90:13: error: ‘here_is_an_unused_function’ defined but not used [-Werror=unused-function] static void here_is_an_unused_function(void) ^~~~~~~~~~~~~~~~~~~~~~~~~~ cc1: all warnings being treated as errors make[2]: *** [scripts/Makefile.build:277: arch/arm64/kernel/cpu_errata.o] Error 1 make[1]: *** [scripts/Makefile.build:540: arch/arm64/kernel] Error 2 make: *** [Makefile:1874: arch/arm64] Error 2 make: *** Waiting for unfinished jobs.... --8>-- diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c index aaa66c9eee24..57c83e84b274 100644 --- a/arch/arm64/kernel/cpu_errata.c +++ b/arch/arm64/kernel/cpu_errata.c @@ -87,12 +87,20 @@ has_mismatched_cache_type(const struct arm64_cpu_capabilities *entry, return (ctr_real != sys) && (ctr_raw != sys); } +static void here_is_an_unused_function(void) +{ + pr_crit("I am unused\n"); +} + static void cpu_enable_trap_ctr_access(const struct arm64_cpu_capabilities *cap) { u64 mask = arm64_ftr_reg_ctrel0.strict_mask; bool enable_uct_trap = false; +#ifdef CONFIG_UNUSED_FUNCTION + here_is_an_unused_function(); +#endif Cheers Suzuki

3 years, 6 months

Re: [PATCH v5 03/15] arm64: errata: Add workaround for TSB flush failures

by Suzuki K Poulose

On 19/10/2021 12:02, Will Deacon wrote: > On Thu, Oct 14, 2021 at 11:31:13PM +0100, Suzuki K Poulose wrote: >> diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c >> index ccd757373f36..bdbeac75ead6 100644 >> --- a/arch/arm64/kernel/cpu_errata.c >> +++ b/arch/arm64/kernel/cpu_errata.c >> @@ -352,6 +352,18 @@ static const struct midr_range trbe_overwrite_fill_mode_cpus[] = { >> }; >> #endif /* CONFIG_ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE */ >> >> +#ifdef CONFIG_ARM64_WORKAROUND_TSB_FLUSH_FAILURE >> +static const struct midr_range tsb_flush_fail_cpus[] = { >> +#ifdef CONFIG_ARM64_ERRATUM_2067961 >> + MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N2), >> +#endif >> +#ifdef CONFIG_ARM64_ERRATUM_2054223 >> + MIDR_ALL_VERSIONS(MIDR_CORTEX_A710), >> +#endif >> + {}, >> +}; >> +#endif /* CONFIG_ARM64_WORKAROUND_TSB_FLUSH_FAILURE */ >> + >> const struct arm64_cpu_capabilities arm64_errata[] = { >> #ifdef CONFIG_ARM64_WORKAROUND_CLEAN_CACHE >> { >> @@ -558,6 +570,13 @@ const struct arm64_cpu_capabilities arm64_errata[] = { >> .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, >> CAP_MIDR_RANGE_LIST(trbe_overwrite_fill_mode_cpus), >> }, >> +#endif >> +#ifdef CONFIG_ARM64_WORKAROUND_TSB_FLUSH_FAILRE > > You still haven't fixed this typo... > Sorry about that. I thought it was about selecting the Kconfig entries, which was fixed. I will fix this. > Seriously, I get compile warnings from this -- are you not seeing them? No, I don't get any warnings. Is there something that I am missing ? --8>-- suzuki@ewhatever:coresight$ grep "WERROR\|TSB" .config CONFIG_WERROR=y CONFIG_ARM64_WORKAROUND_TSB_FLUSH_FAILURE=y suzuki@ewhatever:coresight$ grep TSB arch/arm64/kernel/cpu_errata.c #ifdef CONFIG_ARM64_WORKAROUND_TSB_FLUSH_FAILURE #endif /* CONFIG_ARM64_WORKAROUND_TSB_FLUSH_FAILURE */ #ifdef CONFIG_ARM64_WORKAROUND_TSB_FLUSH_FAILRE .capability = ARM64_WORKAROUND_TSB_FLUSH_FAILURE, suzuki@ewhatever:coresight$ touch arch/arm64/kernel/cpu_errata.c suzuki@ewhatever:coresight$ make -j16 CALL scripts/atomic/check-atomics.sh CALL scripts/checksyscalls.sh CHK include/generated/compile.h CC arch/arm64/kernel/cpu_errata.o AR arch/arm64/kernel/built-in.a AR arch/arm64/built-in.a GEN .version CHK include/generated/compile.h UPD include/generated/compile.h CC init/version.o AR init/built-in.a LD vmlinux.o MODPOST vmlinux.symvers MODINFO modules.builtin.modinfo GEN modules.builtin LD .tmp_vmlinux.kallsyms1 KSYMS .tmp_vmlinux.kallsyms1.S AS .tmp_vmlinux.kallsyms1.S LD .tmp_vmlinux.kallsyms2 KSYMS .tmp_vmlinux.kallsyms2.S AS .tmp_vmlinux.kallsyms2.S LD vmlinux SORTTAB vmlinux SYSMAP System.map MODPOST modules-only.symvers OBJCOPY arch/arm64/boot/Image GEN Module.symvers GZIP arch/arm64/boot/Image.gz Suzuki > > Will >

3 years, 6 months

Re: [PATCH v5 02/15] arm64: errata: Add detection for TRBE overwrite in FILL mode

by Suzuki K Poulose

On 19/10/2021 12:04, Will Deacon wrote: > On Thu, Oct 14, 2021 at 11:31:12PM +0100, Suzuki K Poulose wrote: >> Arm Neoverse-N2 and the Cortex-A710 cores are affected >> by a CPU erratum where the TRBE will overwrite the trace buffer >> in FILL mode. The TRBE doesn't stop (as expected in FILL mode) >> when it reaches the limit and wraps to the base to continue >> writing upto 3 cache lines. This will overwrite any trace that >> was written previously. >> >> Add the Neoverse-N2 erratumi(#2139208) and Cortex-A710 erratum >> (#2119858) to the detection logic. > > Weird typo and double space in this sentence. I have fixed this now. Thanks Suzuki

3 years, 6 months

Re: [PATCH v5 10/15] coresight: trbe: Workaround TRBE errata overwrite in FILL mode

by Suzuki K Poulose

On 19/10/2021 05:36, Anshuman Khandual wrote: > > > On 10/19/21 2:45 AM, Suzuki K Poulose wrote: >> On 18/10/2021 16:51, Mathieu Poirier wrote: >>> On Thu, Oct 14, 2021 at 11:31:20PM +0100, Suzuki K Poulose wrote: >>>> ARM Neoverse-N2 (#2139208) and Cortex-A710(##2119858) suffers from >>>> an erratum, which when triggered, might cause the TRBE to overwrite >>>> the trace data already collected in FILL mode, in the event of a WRAP. >>>> i.e, the TRBE doesn't stop writing the data, instead wraps to the base >>>> and could write upto 3 cache line size worth trace. Thus, this could >>>> corrupt the trace at the "BASE" pointer. >>>> >>>> The workaround is to program the write pointer 256bytes from the >>>> base, such that if the erratum is triggered, it doesn't overwrite >>>> the trace data that was captured. This skipped region could be >>>> padded with ignore packets at the end of the session, so that >>>> the decoder sees a continuous buffer with some padding at the >>>> beginning. The trace data written at the base is considered >>>> lost as the limit could have been in the middle of the perf >>>> ring buffer, and jumping to the "base" is not acceptable. >>>> We set the flags already to indicate that some amount of trace >>>> was lost during the FILL event IRQ. So this is fine. >>>> >>>> One important change with the work around is, we program the >>>> TRBBASER_EL1 to current page where we are allowed to write. >>>> Otherwise, it could overwrite a region that may be consumed >>>> by the perf. Towards this, we always make sure that the >>>> "handle->head" and thus the trbe_write is PAGE_SIZE aligned, >>>> so that we can set the BASE to the PAGE base and move the >>>> TRBPTR to the 256bytes offset. >>>> >>>> Cc: Mike Leach <mike.leach(a)linaro.org> >>>> Cc: Mathieu Poirier <mathieu.poirier(a)linaro.org> >>>> Cc: Anshuman Khandual <anshuman.khandual(a)arm.com> >>>> Cc: Leo Yan <leo.yan(a)linaro.org> >>>> Reviewed-by: Mathieu Poirier <mathieu.poirier(a)linaro.org> >>>> Signed-off-by: Suzuki K Poulose <suzuki.poulose(a)arm.com> >>>> --- >>>> Changes since v2: >>>> - Updated the ASCII art to include better description of >>>> all the steps in the work around >>>> Change since v1: >>>> - Updated comment with ASCII art >>>> - Add _BYTES suffix for the space to skip for the work around. >>>> --- >>>> drivers/hwtracing/coresight/coresight-trbe.c | 169 +++++++++++++++++-- >>>> 1 file changed, 158 insertions(+), 11 deletions(-) >>>> >>>> diff --git a/drivers/hwtracing/coresight/coresight-trbe.c b/drivers/hwtracing/coresight/coresight-trbe.c >>>> index 314e5e7374c7..b56b166b2dec 100644 >>>> --- a/drivers/hwtracing/coresight/coresight-trbe.c >>>> +++ b/drivers/hwtracing/coresight/coresight-trbe.c >>>> @@ -16,6 +16,7 @@ >>>> #define pr_fmt(fmt) DRVNAME ": " fmt >>>> #include <asm/barrier.h> >>>> +#include <asm/cpufeature.h> >>> >>> Here too I get a checkpatch warning... >>> >> >> That is a false alarm. I guess that warns for including >> linux/cpufeature.h? It is a bit odd, we include this >> for the arm64 cpucaps, not the generic linux feature > > It is a bit odd, I saw that too. > >> checks. (They are used for "loading modules" based >> on "features" which are more like ELF HWCAPs). > > Should <asm/cpufeature.h> be renamed as <asm/arm64_cpufeature.h> > or something similar instead to differentiate it from the generic > <linux/cpufeature.h> as they are not related. Also, probably this > warning could be avoided. It is not that simple. asm/cpufeature.h on arm64 provides : * arch backend for linux/cpufeature.h * CPU feature sanity check infrastructure * CPU capability infrastructure ( features & errata ) So ideally it should be split into 3 for better cleanup and is something that could be pursued outside this series. Suzuki

3 years, 6 months

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