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[PATCH v5 00/10] Coresight: Add support for TPDM and TPDA

by Mao Jinlong

This series adds support for the trace performance monitoring and diagnostics hardware (TPDM and TPDA). It is composed of two major elements. a) Changes for original coresight framework to support for TPDM and TPDA. b) Add driver code for TPDM and TPDA. Introduction of changes for original coresight framework Support TPDM as new coresight source. Since only STM and ETM are supported as coresight source originally. TPDM is a newly added coresight source. We need to change the original way of saving coresight path to support more types source for coresight driver. The following patch is to add support more coresight sources. coresight: core: Use IDR for non-cpu bound sources' paths. Introduction of TPDM and TPDA TPDM - The trace performance monitoring and diagnostics monitor or TPDM in short serves as data collection component for various dataset types specified in the QPMDA(Qualcomm performance monitoring and diagnostics architecture) spec. The primary use case of the TPDM is to collect data from different data sources and send it to a TPDA for packetization, timestamping and funneling. Coresight: Add coresight TPDM source driver dt-bindings: arm: Adds CoreSight TPDM hardware definitions coresight-tpdm: Add DSB dataset support coresight-tpdm: Add integration test support docs: sysfs: coresight: Add sysfs ABI documentation for TPDM TPDA - The trace performance monitoring and diagnostics aggregator or TPDA in short serves as an arbitration and packetization engine for the performance monitoring and diagnostics network as specified in the QPMDA (Qualcomm performance monitoring and diagnostics architecture) specification. The primary use case of the TPDA is to provide packetization, funneling and timestamping of Monitor data as specified in the QPMDA specification. The following patch is to add driver for TPDA. Coresight: Add TPDA link driver dt-bindings: arm: Adds CoreSight TPDA hardware definitions The last patch of this series is a device tree modification, which add the TPDM and TPDA configuration to device tree for validating. ARM: dts: msm: Add coresight components for SM8250 ARM: dts: msm: Add tpdm mm/prng for sm8250 Once this series patches are applied properly, the tpdm and tpda nodes should be observed at the coresight path /sys/bus/coresight/devices e.g. /sys/bus/coresight/devices # ls -l | grep tpd tpda0 -> ../../../devices/platform/soc(a)0/6004000.tpda/tpda0 tpdm0 -> ../../../devices/platform/soc(a)0/6c08000.mm.tpdm/tpdm0 We can use the commands are similar to the below to validate TPDMs. Enable coresight sink first. echo 1 > /sys/bus/coresight/devices/tmc_etf0/enable_sink echo 1 > /sys/bus/coresight/devices/tpdm0/enable_source echo 1 > /sys/bus/coresight/devices/tpdm0/integration_test echo 2 > /sys/bus/coresight/devices/tpdm0/integration_test The test data will be collected in the coresight sink which is enabled. If rwp register of the sink is keeping updating when do integration_test (by cat tmc_etf0/mgmt/rwp), it means there is data generated from TPDM to sink. There must be a tpda between tpdm and the sink. When there are some other trace event hw components in the same HW block with tpdm, tpdm and these hw components will connect to the coresight funnel. When there is only tpdm trace hw in the HW block, tpdm will connect to tpda directly. +---------------+ +-------------+ | tpdm@6c08000 | |tpdm@684C000 | +-------|-------+ +------|------+ | | +-------|-------+ | | funnel@6c0b000| | +-------|-------+ | | | +-------|-------+ | |funnel@6c2d000 | | +-------|-------+ | | | | +---------------+ | +----- tpda@6004000 -----------+ +-------|-------+ | +-------|-------+ |funnel@6005000 | +---------------+ This patch series depends on patch series "coresight: Add new API to allocate trace source ID values". https://patchwork.kernel.org/project/linux-arm-kernel/cover/20220308205000.… Changes from V4: 1. Keep the ETM source paths per-CPU and use IDR for other sources' paths. (Suzuki K Poulose <suzuki.poulose(a)arm.com>) Mao Jinlong (10): coresight: core: Use IDR for non-cpu bound sources' paths. Coresight: Add coresight TPDM source driver dt-bindings: arm: Adds CoreSight TPDM hardware definitions coresight-tpdm: Add DSB dataset support coresight-tpdm: Add integration test support docs: sysfs: coresight: Add sysfs ABI documentation for TPDM Coresight: Add TPDA link driver dt-bindings: arm: Adds CoreSight TPDA hardware definitions ARM: dts: msm: Add coresight components for SM8250 ARM: dts: msm: Add tpdm mm/prng for sm8250 .../testing/sysfs-bus-coresight-devices-tpdm | 13 + .../bindings/arm/coresight-tpda.yaml | 119 +++ .../bindings/arm/coresight-tpdm.yaml | 99 +++ .../devicetree/bindings/arm/coresight.txt | 7 + MAINTAINERS | 1 + .../arm64/boot/dts/qcom/sm8250-coresight.dtsi | 708 ++++++++++++++++++ arch/arm64/boot/dts/qcom/sm8250.dtsi | 2 + drivers/hwtracing/coresight/Kconfig | 33 + drivers/hwtracing/coresight/Makefile | 2 + drivers/hwtracing/coresight/coresight-core.c | 42 +- drivers/hwtracing/coresight/coresight-tpda.c | 192 +++++ drivers/hwtracing/coresight/coresight-tpda.h | 32 + drivers/hwtracing/coresight/coresight-tpdm.c | 270 +++++++ drivers/hwtracing/coresight/coresight-tpdm.h | 61 ++ include/linux/coresight.h | 1 + 15 files changed, 1570 insertions(+), 12 deletions(-) create mode 100644 Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm create mode 100644 Documentation/devicetree/bindings/arm/coresight-tpda.yaml create mode 100644 Documentation/devicetree/bindings/arm/coresight-tpdm.yaml create mode 100644 arch/arm64/boot/dts/qcom/sm8250-coresight.dtsi create mode 100644 drivers/hwtracing/coresight/coresight-tpda.c create mode 100644 drivers/hwtracing/coresight/coresight-tpda.h create mode 100644 drivers/hwtracing/coresight/coresight-tpdm.c create mode 100644 drivers/hwtracing/coresight/coresight-tpdm.h -- 2.17.1

3 years, 7 months

Re: [PATCH v5 09/10] ARM: dts: msm: Add coresight components for SM8250

by Mike Leach

Hi On Wed, 13 Apr 2022 at 17:45, Jinlong Mao <quic_jinlmao(a)quicinc.com> wrote: > > Hi Konrad, > > Thank you for the review. > > On 4/13/2022 5:58 PM, Konrad Dybcio wrote: > > Hi, > > > > > > I added Bjorn, the linux-arm-msm maintainer to CC as he was missing > > for some reason. > > > > > > On 12/04/2022 14:50, Mao Jinlong wrote: > >> Add coresight device tree for sm8250. STM/ETM are added. > >> > >> Signed-off-by: Tao Zhang <quic_taozha(a)quicinc.com> > >> Signed-off-by: Mao Jinlong <quic_jinlmao(a)quicinc.com> > >> --- > >> .../arm64/boot/dts/qcom/sm8250-coresight.dtsi | 526 ++++++++++++++++++ > >> arch/arm64/boot/dts/qcom/sm8250.dtsi | 2 + > >> 2 files changed, 528 insertions(+) > >> create mode 100644 arch/arm64/boot/dts/qcom/sm8250-coresight.dtsi > >> > >> diff --git a/arch/arm64/boot/dts/qcom/sm8250-coresight.dtsi > >> b/arch/arm64/boot/dts/qcom/sm8250-coresight.dtsi > >> new file mode 100644 > >> index 000000000000..1de42fd39248 > >> --- /dev/null > >> +++ b/arch/arm64/boot/dts/qcom/sm8250-coresight.dtsi > >> @@ -0,0 +1,526 @@ > >> +// SPDX-License-Identifier: GPL-2.0 > > > > sm8250.dtsi is BSD-3-Clause. Please consider relicensing. > > > > > >> +/* > >> + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights > >> reserved. > >> + */ > >> + > >> +&soc { > >> + > >> + stm@6002000 { > >> + compatible = "arm,coresight-stm", "arm,primecell"; > >> + reg = <0 0x06002000 0 0x1000>, > > > > You don't need to break the line at so few characters. > > > > > >> + <0 0x16280000 0 0x180000>; > >> + reg-names = "stm-base", "stm-stimulus-base"; > >> + > >> + clocks = <&aoss_qmp>; > >> + clock-names = "apb_pclk"; > >> + > >> + out-ports { > >> + port { > >> + stm_out: endpoint { > >> + remote-endpoint = > >> + <&funnel0_in7>; > > > > Same here. > > > > > >> + }; > >> + }; > >> + }; > >> + }; > >> + > >> + funnel@6041000 { > >> + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; > >> + reg = <0 0x06041000 0 0x1000>; > >> + > >> + clocks = <&aoss_qmp>; > >> + clock-names = "apb_pclk"; > >> + > >> + out-ports { > >> + port { > >> + funnel0_out: endpoint { > >> + remote-endpoint = > >> + <&merge_funnel_in0>; > > > > And here. > > > > > >> + }; > >> + }; > >> + }; > >> + > >> + in-ports { > >> + #address-cells = <1>; > >> + #size-cells = <0>; > >> + > >> + port@7 { > >> + reg = <7>; > >> + funnel0_in7: endpoint { > >> + remote-endpoint = <&stm_out>; > >> + }; > >> + }; > >> + }; > >> + }; > >> + > >> + funnel@6042000 { > >> + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; > >> + reg = <0 0x06042000 0 0x1000>; > >> + > >> + clocks = <&aoss_qmp>; > >> + clock-names = "apb_pclk"; > >> + > >> + out-ports { > >> + port { > >> + funnel2_out: endpoint { > >> + remote-endpoint = > >> + <&merge_funnel_in2>; > > > > And here. > > > > > >> + }; > >> + }; > >> + }; > >> + > >> + in-ports { > >> + #address-cells = <1>; > >> + #size-cells = <0>; > >> + > >> + port@2 { > >> + reg = <4>; > >> + funnel2_in5: endpoint { > >> + remote-endpoint = > >> + <&apss_merge_funnel_out>; > >> + }; > >> + }; > >> + }; > >> + }; > >> + > >> + funnel@6b04000 { > >> + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; > >> + arm,primecell-periphid = <0x000bb908>; > >> + > >> + reg = <0 0x6b04000 0 0x1000>; > >> + reg-names = "funnel-base"; > >> + > >> + clocks = <&aoss_qmp>; > >> + clock-names = "apb_pclk"; > >> + > >> + out-ports { > >> + port { > >> + merge_funnel_out: endpoint { > >> + remote-endpoint = > >> + <&etf_in>; > > And here. > > > > > >> + }; > >> + }; > >> + }; > >> + > >> + in-ports { > >> + #address-cells = <1>; > >> + #size-cells = <0>; > >> + > >> + port@7 { > >> + reg = <7>; > >> + funnel_swao_in_funnel_merg: endpoint { > >> + remote-endpoint= > > > > And here. > > > > > >> + <&funnel_merg_out_funnel_swao>; > >> + }; > >> + }; > >> + }; > >> + > >> + }; > >> + > >> + funnel@6045000 { > > > > The nodes are not sorted properly (by address). Please fix that. > > > > > >> + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; > >> + reg = <0 0x06045000 0 0x1000>; > >> + > >> + clocks = <&aoss_qmp>; > >> + clock-names = "apb_pclk"; > >> + > >> + out-ports { > >> + port { > >> + funnel_merg_out_funnel_swao: endpoint { > >> + remote-endpoint = <&funnel_swao_in_funnel_merg>; > >> + }; > >> + }; > >> + }; > >> + > >> + in-ports { > >> + #address-cells = <1>; > >> + #size-cells = <0>; > >> + > >> + port@1 { > >> + reg = <0>; > >> + merge_funnel_in0: endpoint { > >> + remote-endpoint = > >> + <&funnel0_out>; > >> + }; > >> + }; > >> + > >> + port@2 { > >> + reg = <1>; > >> + merge_funnel_in2: endpoint { > >> + remote-endpoint = > >> + <&funnel2_out>; > >> + }; > >> + }; > >> + }; > >> + }; > >> + > >> + replicator@6046000 { > >> + compatible = "arm,coresight-dynamic-replicator", > >> "arm,primecell"; > >> + reg = <0 0x06046000 0 0x1000>; > >> + > >> + > >> + clocks = <&aoss_qmp>; > >> + clock-names = "apb_pclk"; > >> + > >> + out-ports { > >> + port { > >> + replicator_out: endpoint { > >> + remote-endpoint = <&etr_in>; > >> + }; > >> + }; > >> + }; > >> + > >> + in-ports { > >> + port { > >> + replicator_cx_in_swao_out: endpoint { > >> + remote-endpoint = <&replicator_swao_out_cx_in>; > >> + }; > >> + }; > >> + }; > >> + }; > >> + > >> + replicator@6b06000 { > >> + compatible = "arm,coresight-dynamic-replicator", > >> "arm,primecell"; > >> + reg = <0 0x06b06000 0 0x1000>; > >> + > >> + clocks = <&aoss_qmp>; > >> + clock-names = "apb_pclk"; > >> + > >> + out-ports { > >> + port { > >> + replicator_swao_out_cx_in: endpoint { > >> + remote-endpoint = <&replicator_cx_in_swao_out>; > >> + }; > >> + }; > >> + }; > >> + > >> + in-ports { > >> + port { > >> + replicator_in: endpoint { > >> + remote-endpoint = <&etf_out>; > >> + }; > >> + }; > >> + }; > >> + }; > >> + > >> + etf@6b05000 { > >> + compatible = "arm,coresight-tmc", "arm,primecell"; > >> + reg = <0 0x6b05000 0 0x1000>; > > > > Please pad the address to 8 chars. > > > > > >> + > >> + clocks = <&aoss_qmp>; > >> + clock-names = "apb_pclk"; > >> + > >> + out-ports { > >> + port { > >> + etf_out: endpoint { > >> + remote-endpoint = > >> + <&replicator_in>; > > > > And here. > > > > > >> + }; > >> + }; > >> + }; > >> + > >> + in-ports { > >> + #address-cells = <1>; > >> + #size-cells = <0>; > >> + > >> + port@1 { > >> + reg = <0>; > >> + etf_in: endpoint { > >> + remote-endpoint = > >> + <&merge_funnel_out>; > >> + }; > >> + }; > >> + }; > >> + }; > >> + > >> + etr@6048000 { > >> + compatible = "arm,coresight-tmc", "arm,primecell"; > >> + reg = <0 0x06048000 0 0x1000>; > >> + > >> + clocks = <&aoss_qmp>; > >> + clock-names = "apb_pclk"; > >> + arm,scatter-gather; > >> + > >> + in-ports { > >> + port { > >> + etr_in: endpoint { > >> + remote-endpoint = > >> + <&replicator_out>; > > > > And here. > > > > > >> + }; > >> + }; > >> + }; > >> + }; > >> + > >> + etm@7040000 { > >> + compatible = "arm,coresight-etm4x", "arm,primecell"; > >> + reg = <0 0x07040000 0 0x1000>; > >> + > >> + cpu = <&CPU0>; > >> + > >> + clocks = <&aoss_qmp>; > >> + clock-names = "apb_pclk"; > >> + arm,coresight-loses-context-with-cpu; > >> + > >> + out-ports { > >> + port { > >> + etm0_out: endpoint { > >> + remote-endpoint = > >> + <&apss_funnel_in0>; > > > > And here. > > > > > >> + }; > >> + }; > >> + }; > >> + }; > >> + > >> + etm@7140000 { > >> + compatible = "arm,coresight-etm4x", "arm,primecell"; > >> + reg = <0 0x07140000 0 0x1000>; > >> + > >> + cpu = <&CPU1>; > >> + > >> + clocks = <&aoss_qmp>; > >> + clock-names = "apb_pclk"; > >> + arm,coresight-loses-context-with-cpu; > >> + > >> + out-ports { > >> + port { > >> + etm1_out: endpoint { > >> + remote-endpoint = > >> + <&apss_funnel_in1>; > > > > And here. > > > > > >> + }; > >> + }; > >> + }; > >> + }; > >> + > >> + etm@7240000 { > >> + compatible = "arm,coresight-etm4x", "arm,primecell"; > >> + reg = <0 0x07240000 0 0x1000>; > >> + > >> + cpu = <&CPU2>; > >> + > >> + clocks = <&aoss_qmp>; > >> + clock-names = "apb_pclk"; > >> + arm,coresight-loses-context-with-cpu; > >> + > >> + out-ports { > >> + port { > >> + etm2_out: endpoint { > >> + remote-endpoint = > >> + <&apss_funnel_in2>; > > > > And here. > > > > > >> + }; > >> + }; > >> + }; > >> + }; > >> + > >> + etm@7340000 { > >> + compatible = "arm,coresight-etm4x", "arm,primecell"; > >> + reg = <0 0x07340000 0 0x1000>; > >> + > >> + cpu = <&CPU3>; > >> + > >> + clocks = <&aoss_qmp>; > >> + clock-names = "apb_pclk"; > >> + arm,coresight-loses-context-with-cpu; > >> + > >> + out-ports { > >> + port { > >> + etm3_out: endpoint { > >> + remote-endpoint = > >> + <&apss_funnel_in3>; > > > > And here. > > > > > >> + }; > >> + }; > >> + }; > >> + }; > >> + > >> + etm@7440000 { > >> + compatible = "arm,coresight-etm4x", "arm,primecell"; > >> + reg = <0 0x07440000 0 0x1000>; > >> + > >> + cpu = <&CPU4>; > >> + > >> + clocks = <&aoss_qmp>; > >> + clock-names = "apb_pclk"; > >> + arm,coresight-loses-context-with-cpu; > >> + > >> + out-ports { > >> + port { > >> + etm4_out: endpoint { > >> + remote-endpoint = > >> + <&apss_funnel_in4>; > > > > And here. > > > > > >> + }; > >> + }; > >> + }; > >> + }; > >> + > >> + etm@7540000 { > >> + compatible = "arm,coresight-etm4x", "arm,primecell"; > >> + reg = <0 0x07540000 0 0x1000>; > >> + > >> + cpu = <&CPU5>; > >> + > >> + clocks = <&aoss_qmp>; > >> + clock-names = "apb_pclk"; > >> + arm,coresight-loses-context-with-cpu; > >> + > >> + out-ports { > >> + port { > >> + etm5_out: endpoint { > >> + remote-endpoint = > >> + <&apss_funnel_in5>; > > > > And here. > > > > > >> + }; > >> + }; > >> + }; > >> + }; > >> + > >> + etm@7640000 { > >> + compatible = "arm,coresight-etm4x", "arm,primecell"; > >> + reg = <0 0x07640000 0 0x1000>; > >> + > >> + cpu = <&CPU6>; > >> + > >> + clocks = <&aoss_qmp>; > >> + clock-names = "apb_pclk"; > >> + arm,coresight-loses-context-with-cpu; > >> + > >> + out-ports { > >> + port { > >> + etm6_out: endpoint { > >> + remote-endpoint = > >> + <&apss_funnel_in6>; > >> + }; > >> + }; > >> + }; > >> + }; > >> + > >> + etm@7740000 { > >> + compatible = "arm,coresight-etm4x", "arm,primecell"; > >> + reg = <0 0x07740000 0 0x1000>; > >> + > >> + cpu = <&CPU7>; > >> + > >> + clocks = <&aoss_qmp>; > >> + clock-names = "apb_pclk"; > >> + arm,coresight-loses-context-with-cpu; > >> + > >> + out-ports { > >> + port { > >> + etm7_out: endpoint { > >> + remote-endpoint = > >> + <&apss_funnel_in7>; > > > > And here. > > > > > >> + }; > >> + }; > >> + }; > >> + }; > >> + > >> + funnel@7800000 { > >> + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; > >> + reg = <0 0x07800000 0 0x1000>; > >> + > >> + clocks = <&aoss_qmp>; > >> + clock-names = "apb_pclk"; > >> + > >> + out-ports { > >> + port { > >> + apss_funnel_out: endpoint { > >> + remote-endpoint = > >> + <&apss_merge_funnel_in>; > > > > And here. > > > > > >> + }; > >> + }; > >> + }; > >> + > >> + in-ports { > >> + #address-cells = <1>; > >> + #size-cells = <0>; > >> + > >> + port@0 { > >> + reg = <0>; > >> + apss_funnel_in0: endpoint { > >> + remote-endpoint = > >> + <&etm0_out>; > > > > And here. > > > > > >> + }; > >> + }; > >> + > >> + port@1 { > >> + reg = <1>; > >> + apss_funnel_in1: endpoint { > >> + remote-endpoint = > >> + <&etm1_out>; > > > > And here. > > > > > >> + }; > >> + }; > >> + > >> + port@2 { > >> + reg = <2>; > >> + apss_funnel_in2: endpoint { > >> + remote-endpoint = > >> + <&etm2_out>; > > > > And here. > > > > > >> + }; > >> + }; > >> + > >> + port@3 { > >> + reg = <3>; > >> + apss_funnel_in3: endpoint { > >> + remote-endpoint = > >> + <&etm3_out>; > > > > And here. > > > > > >> + }; > >> + }; > >> + > >> + port@4 { > >> + reg = <4>; > >> + apss_funnel_in4: endpoint { > >> + remote-endpoint = > >> + <&etm4_out>; > > > > And here. > > > > > >> + }; > >> + }; > >> + > >> + port@5 { > >> + reg = <5>; > >> + apss_funnel_in5: endpoint { > >> + remote-endpoint = > >> + <&etm5_out>; > > > > And here. > > > > > >> + }; > >> + }; > >> + > >> + port@6 { > >> + reg = <6>; > >> + apss_funnel_in6: endpoint { > >> + remote-endpoint = > >> + <&etm6_out>; > > > > And here. > > > > > >> + }; > >> + }; > >> + > >> + port@7 { > >> + reg = <7>; > >> + apss_funnel_in7: endpoint { > >> + remote-endpoint = > >> + <&etm7_out>; > > > > And here. > > > > > >> + }; > >> + }; > >> + }; > >> + }; > >> + > >> + funnel@7810000 { > >> + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; > >> + reg = <0 0x07810000 0 0x1000>; > >> + > >> + clocks = <&aoss_qmp>; > >> + clock-names = "apb_pclk"; > >> + > >> + out-ports { > >> + port { > >> + apss_merge_funnel_out: endpoint { > >> + remote-endpoint = > >> + <&funnel2_in5>; > > > > And here. > > > > > >> + }; > >> + }; > >> + }; > >> + > >> + in-ports { > >> + port@1 { > >> + reg = <0>; > >> + apss_merge_funnel_in: endpoint { > >> + remote-endpoint = > >> + <&apss_funnel_out>; > >> + }; > >> + }; > >> + }; > >> + }; > >> +}; > >> diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi > >> b/arch/arm64/boot/dts/qcom/sm8250.dtsi > >> index af8f22636436..115623392183 100644 > >> --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi > >> +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi > >> @@ -5434,3 +5434,5 @@ > >> }; > >> }; > >> }; > >> + > >> +#include "sm8250-coresight.dtsi" > > > > Why should everybody want coresight? It's not enabled on (most) > > production devices and may cause a platform crash when you try to use > > it on such ones. > > > > > > These nodes should probably be added to sm8250.dtsi, all with status = > > "disabled" by default, so that they don't break the devices that do > > not support it due to fuse configuration. > > > I will address your comments above. > I create coresight dtsi because of that there are dozens of coresight > nodes for qualcomm HW. > Add all the nodes in a separate file is easy to maintain. > For disabling all the nodes by default, i will check internally and get > back to you. > If the nodes are "disabled", then the base .dts files for platforms that do include coresight would have to be updated to enable all those nodes - which leaves potential for errors if nodes are accidentally omitted. Because sm8250-coresight.dtsi contains only Coresight devices, would it not be better to include this directly in the base .dts file for platforms that do have Coresight, and omit it from those that do not. Regards Mike > > Thanks > Jinlong Mao > > > > > > Konrad > > -- Mike Leach Principal Engineer, ARM Ltd. Manchester Design Centre. UK

3 years, 7 months

[PATCH v3 00/15] Make ETM register accesses consistent with sysreg.h

by James Clark

Changes since v2: * Implement Mike's suggestion of not having _SHIFT and using the existing FIELD_GET and FIELD_PREP methods. * Dropped the change to add the new REG_VAL macro because of the above. * FIELD_PREP could be used in some trivial cases, but in some cases the shift is still required but can be calculated with __bf_shf * Improved the commit messages. * The change is still binary equivalent, but requires an extra step mentioned at the end of this cover letter. Applies to coresight/next 3619ee28488 Also available at https://gitlab.arm.com/linux-arm/linux-jc/-/tree/james-cs-register-refactor… To check for binary equivalence follow the same steps in the cover letter of v2, but apply the following change to coresight-priv.h. This is because the existing version of the macros wrap the expression in a new scope {} that flips something in the compiler: #undef FIELD_GET #define FIELD_GET(_mask, _reg) (((_reg) & (_mask)) >> __bf_shf(_mask)) #undef FIELD_PREP #define FIELD_PREP(_mask, _val) (((_val) << __bf_shf(_mask)) & (_mask)) Thanks James James Clark (15): coresight: etm4x: Cleanup TRCIDR0 register accesses coresight: etm4x: Cleanup TRCIDR2 register accesses coresight: etm4x: Cleanup TRCIDR3 register accesses coresight: etm4x: Cleanup TRCIDR4 register accesses coresight: etm4x: Cleanup TRCIDR5 register accesses coresight: etm4x: Cleanup TRCCONFIGR register accesses coresight: etm4x: Cleanup TRCEVENTCTL1R register accesses coresight: etm4x: Cleanup TRCSTALLCTLR register accesses coresight: etm4x: Cleanup TRCVICTLR register accesses coresight: etm3x: Cleanup ETMTECR1 register accesses coresight: etm4x: Cleanup TRCACATRn register accesses coresight: etm4x: Cleanup TRCSSCCRn and TRCSSCSRn register accesses coresight: etm4x: Cleanup TRCSSPCICRn register accesses coresight: etm4x: Cleanup TRCBBCTLR register accesses coresight: etm4x: Cleanup TRCRSCTLRn register accesses .../coresight/coresight-etm3x-core.c | 2 +- .../coresight/coresight-etm3x-sysfs.c | 2 +- .../coresight/coresight-etm4x-core.c | 136 +++++-------- .../coresight/coresight-etm4x-sysfs.c | 180 +++++++++--------- drivers/hwtracing/coresight/coresight-etm4x.h | 122 ++++++++++-- 5 files changed, 244 insertions(+), 198 deletions(-) -- 2.28.0

3 years, 7 months

[PATCH] arm64: dts: juno: add CTI entries to device tree

by Mike Leach

Add in CTI entries for Juno r0, r1 and r2 to device tree entries. Tested on Linux 5.18-rc2 Signed-off-by: Mike Leach <mike.leach(a)linaro.org> Reviewed-by: Mathieu Poirier <mathieu.poirier(a)linaro.org> --- arch/arm64/boot/dts/arm/juno-base.dtsi | 162 +++++++++++++++++++++- arch/arm64/boot/dts/arm/juno-cs-r1r2.dtsi | 37 ++++- arch/arm64/boot/dts/arm/juno-r1-scmi.dts | 4 + arch/arm64/boot/dts/arm/juno-r1.dts | 25 ++++ arch/arm64/boot/dts/arm/juno-r2-scmi.dts | 4 + arch/arm64/boot/dts/arm/juno-r2.dts | 25 ++++ arch/arm64/boot/dts/arm/juno-scmi.dtsi | 25 ++++ arch/arm64/boot/dts/arm/juno.dts | 25 ++++ 8 files changed, 302 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/arm/juno-base.dtsi b/arch/arm64/boot/dts/arm/juno-base.dtsi index 446c8f476eec..4f40a5c8f565 100644 --- a/arch/arm64/boot/dts/arm/juno-base.dtsi +++ b/arch/arm64/boot/dts/arm/juno-base.dtsi @@ -117,7 +117,7 @@ * The actual size is just 4K though 64K is reserved. Access to the * unmapped reserved region results in a DECERR response. */ - etf@20010000 { /* etf0 */ + etf_sys0: etf@20010000 { /* etf0 */ compatible = "arm,coresight-tmc", "arm,primecell"; reg = <0 0x20010000 0 0x1000>; @@ -141,7 +141,7 @@ }; }; - tpiu@20030000 { + tpiu_sys: tpiu@20030000 { compatible = "arm,coresight-tpiu", "arm,primecell"; reg = <0 0x20030000 0 0x1000>; @@ -194,7 +194,7 @@ }; }; - etr@20070000 { + etr_sys: etr@20070000 { compatible = "arm,coresight-tmc", "arm,primecell"; reg = <0 0x20070000 0 0x1000>; iommus = <&smmu_etr 0>; @@ -212,7 +212,7 @@ }; }; - stm@20100000 { + stm_sys: stm@20100000 { compatible = "arm,coresight-stm", "arm,primecell"; reg = <0 0x20100000 0 0x1000>, <0 0x28000000 0 0x1000000>; @@ -289,6 +289,18 @@ }; }; + cti0: cti@22020000 { + compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti", + "arm,primecell"; + reg = <0 0x22020000 0 0x1000>; + + clocks = <&soc_smc50mhz>; + clock-names = "apb_pclk"; + power-domains = <&scpi_devpd 0>; + + arm,cs-dev-assoc = <&etm0>; + }; + funnel@220c0000 { /* cluster0 funnel */ compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; reg = <0 0x220c0000 0 0x1000>; @@ -349,6 +361,18 @@ }; }; + cti1: cti@22120000 { + compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti", + "arm,primecell"; + reg = <0 0x22120000 0 0x1000>; + + clocks = <&soc_smc50mhz>; + clock-names = "apb_pclk"; + power-domains = <&scpi_devpd 0>; + + arm,cs-dev-assoc = <&etm1>; + }; + cpu_debug2: cpu-debug@23010000 { compatible = "arm,coresight-cpu-debug", "arm,primecell"; reg = <0x0 0x23010000 0x0 0x1000>; @@ -374,6 +398,18 @@ }; }; + cti2: cti@23020000 { + compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti", + "arm,primecell"; + reg = <0 0x23020000 0 0x1000>; + + clocks = <&soc_smc50mhz>; + clock-names = "apb_pclk"; + power-domains = <&scpi_devpd 0>; + + arm,cs-dev-assoc = <&etm2>; + }; + funnel@230c0000 { /* cluster1 funnel */ compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; reg = <0 0x230c0000 0 0x1000>; @@ -446,6 +482,18 @@ }; }; + cti3: cti@23120000 { + compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti", + "arm,primecell"; + reg = <0 0x23120000 0 0x1000>; + + clocks = <&soc_smc50mhz>; + clock-names = "apb_pclk"; + power-domains = <&scpi_devpd 0>; + + arm,cs-dev-assoc = <&etm3>; + }; + cpu_debug4: cpu-debug@23210000 { compatible = "arm,coresight-cpu-debug", "arm,primecell"; reg = <0x0 0x23210000 0x0 0x1000>; @@ -471,6 +519,18 @@ }; }; + cti4: cti@23220000 { + compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti", + "arm,primecell"; + reg = <0 0x23220000 0 0x1000>; + + clocks = <&soc_smc50mhz>; + clock-names = "apb_pclk"; + power-domains = <&scpi_devpd 0>; + + arm,cs-dev-assoc = <&etm4>; + }; + cpu_debug5: cpu-debug@23310000 { compatible = "arm,coresight-cpu-debug", "arm,primecell"; reg = <0x0 0x23310000 0x0 0x1000>; @@ -496,6 +556,100 @@ }; }; + cti5: cti@23320000 { + compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti", + "arm,primecell"; + reg = <0 0x23320000 0 0x1000>; + + clocks = <&soc_smc50mhz>; + clock-names = "apb_pclk"; + power-domains = <&scpi_devpd 0>; + + arm,cs-dev-assoc = <&etm5>; + }; + + cti_sys0: cti@20020000 { /* sys_cti_0 */ + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0 0x20020000 0 0x1000>; + + clocks = <&soc_smc50mhz>; + clock-names = "apb_pclk"; + power-domains = <&scpi_devpd 0>; + + #address-cells = <1>; + #size-cells = <0>; + + trig-conns@0 { + reg = <0>; + arm,trig-in-sigs=<2 3>; + arm,trig-in-types=<SNK_FULL SNK_ACQCOMP>; + arm,trig-out-sigs=<0 1>; + arm,trig-out-types=<SNK_FLUSHIN SNK_TRIGIN>; + arm,cs-dev-assoc = <&etr_sys>; + }; + + trig-conns@1 { + reg = <1>; + arm,trig-in-sigs=<0 1>; + arm,trig-in-types=<SNK_FULL SNK_ACQCOMP>; + arm,trig-out-sigs=<7 6>; + arm,trig-out-types=<SNK_FLUSHIN SNK_TRIGIN>; + arm,cs-dev-assoc = <&etf_sys0>; + }; + + trig-conns@2 { + reg = <2>; + arm,trig-in-sigs=<4 5 6 7>; + arm,trig-in-types=<STM_TOUT_SPTE STM_TOUT_SW + STM_TOUT_HETE STM_ASYNCOUT>; + arm,trig-out-sigs=<4 5>; + arm,trig-out-types=<STM_HWEVENT STM_HWEVENT>; + arm,cs-dev-assoc = <&stm_sys>; + }; + + trig-conns@3 { + reg = <3>; + arm,trig-out-sigs=<2 3>; + arm,trig-out-types=<SNK_FLUSHIN SNK_TRIGIN>; + arm,cs-dev-assoc = <&tpiu_sys>; + }; + }; + + cti_sys1: cti@20110000 { /* sys_cti_1 */ + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0 0x20110000 0 0x1000>; + + clocks = <&soc_smc50mhz>; + clock-names = "apb_pclk"; + power-domains = <&scpi_devpd 0>; + + #address-cells = <1>; + #size-cells = <0>; + + trig-conns@0 { + reg = <0>; + arm,trig-in-sigs=<0>; + arm,trig-in-types=<GEN_INTREQ>; + arm,trig-out-sigs=<0>; + arm,trig-out-types=<GEN_HALTREQ>; + arm,trig-conn-name = "sys_profiler"; + }; + + trig-conns@1 { + reg = <1>; + arm,trig-out-sigs=<2 3>; + arm,trig-out-types=<GEN_HALTREQ GEN_RESTARTREQ>; + arm,trig-conn-name = "watchdog"; + }; + + trig-conns@2 { + reg = <2>; + arm,trig-out-sigs=<1 6>; + arm,trig-out-types=<GEN_HALTREQ GEN_RESTARTREQ>; + arm,trig-conn-name = "g_counter"; + }; + }; + gpu: gpu@2d000000 { compatible = "arm,juno-mali", "arm,mali-t624"; reg = <0 0x2d000000 0 0x10000>; diff --git a/arch/arm64/boot/dts/arm/juno-cs-r1r2.dtsi b/arch/arm64/boot/dts/arm/juno-cs-r1r2.dtsi index eda3d9e18af6..2e43f4531308 100644 --- a/arch/arm64/boot/dts/arm/juno-cs-r1r2.dtsi +++ b/arch/arm64/boot/dts/arm/juno-cs-r1r2.dtsi @@ -23,7 +23,7 @@ }; }; - etf@20140000 { /* etf1 */ + etf_sys1: etf@20140000 { /* etf1 */ compatible = "arm,coresight-tmc", "arm,primecell"; reg = <0 0x20140000 0 0x1000>; @@ -82,4 +82,39 @@ }; }; + + cti_sys2: cti@20160000 { /* sys_cti_2 */ + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0 0x20160000 0 0x1000>; + + clocks = <&soc_smc50mhz>; + clock-names = "apb_pclk"; + power-domains = <&scpi_devpd 0>; + + #address-cells = <1>; + #size-cells = <0>; + + trig-conns@0 { + reg = <0>; + arm,trig-in-sigs=<0 1>; + arm,trig-in-types=<SNK_FULL SNK_ACQCOMP>; + arm,trig-out-sigs=<0 1>; + arm,trig-out-types=<SNK_FLUSHIN SNK_TRIGIN>; + arm,cs-dev-assoc = <&etf_sys1>; + }; + + trig-conns@1 { + reg = <1>; + arm,trig-in-sigs=<2 3 4>; + arm,trig-in-types=<ELA_DBGREQ ELA_TSTART ELA_TSTOP>; + arm,trig-conn-name = "ela_clus_0"; + }; + + trig-conns@2 { + reg = <2>; + arm,trig-in-sigs=<5 6 7>; + arm,trig-in-types=<ELA_DBGREQ ELA_TSTART ELA_TSTOP>; + arm,trig-conn-name = "ela_clus_1"; + }; + }; }; diff --git a/arch/arm64/boot/dts/arm/juno-r1-scmi.dts b/arch/arm64/boot/dts/arm/juno-r1-scmi.dts index fd1f0d26d751..dd9ea69f086f 100644 --- a/arch/arm64/boot/dts/arm/juno-r1-scmi.dts +++ b/arch/arm64/boot/dts/arm/juno-r1-scmi.dts @@ -15,6 +15,10 @@ }; }; +&cti_sys2 { + power-domains = <&scmi_devpd 8>; +}; + &A57_0 { clocks = <&scmi_dvfs 0>; }; diff --git a/arch/arm64/boot/dts/arm/juno-r1.dts b/arch/arm64/boot/dts/arm/juno-r1.dts index 0e24e29eb9b1..f099fb611d4e 100644 --- a/arch/arm64/boot/dts/arm/juno-r1.dts +++ b/arch/arm64/boot/dts/arm/juno-r1.dts @@ -9,6 +9,7 @@ /dts-v1/; #include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/arm/coresight-cti-dt.h> #include "juno-base.dtsi" #include "juno-cs-r1r2.dtsi" @@ -313,3 +314,27 @@ &cpu_debug5 { cpu = <&A53_3>; }; + +&cti0 { + cpu = <&A57_0>; +}; + +&cti1 { + cpu = <&A57_1>; +}; + +&cti2 { + cpu = <&A53_0>; +}; + +&cti3 { + cpu = <&A53_1>; +}; + +&cti4 { + cpu = <&A53_2>; +}; + +&cti5 { + cpu = <&A53_3>; +}; diff --git a/arch/arm64/boot/dts/arm/juno-r2-scmi.dts b/arch/arm64/boot/dts/arm/juno-r2-scmi.dts index 35e6d4762c46..de2cbac1d1c3 100644 --- a/arch/arm64/boot/dts/arm/juno-r2-scmi.dts +++ b/arch/arm64/boot/dts/arm/juno-r2-scmi.dts @@ -15,6 +15,10 @@ }; }; +&cti_sys2 { + power-domains = <&scmi_devpd 8>; +}; + &A72_0 { clocks = <&scmi_dvfs 0>; }; diff --git a/arch/arm64/boot/dts/arm/juno-r2.dts b/arch/arm64/boot/dts/arm/juno-r2.dts index e609420ce3e4..709389582ae3 100644 --- a/arch/arm64/boot/dts/arm/juno-r2.dts +++ b/arch/arm64/boot/dts/arm/juno-r2.dts @@ -9,6 +9,7 @@ /dts-v1/; #include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/arm/coresight-cti-dt.h> #include "juno-base.dtsi" #include "juno-cs-r1r2.dtsi" @@ -319,3 +320,27 @@ &cpu_debug5 { cpu = <&A53_3>; }; + +&cti0 { + cpu = <&A72_0>; +}; + +&cti1 { + cpu = <&A72_1>; +}; + +&cti2 { + cpu = <&A53_0>; +}; + +&cti3 { + cpu = <&A53_1>; +}; + +&cti4 { + cpu = <&A53_2>; +}; + +&cti5 { + cpu = <&A53_3>; +}; diff --git a/arch/arm64/boot/dts/arm/juno-scmi.dtsi b/arch/arm64/boot/dts/arm/juno-scmi.dtsi index d72dcff9bf06..4135d62e44a2 100644 --- a/arch/arm64/boot/dts/arm/juno-scmi.dtsi +++ b/arch/arm64/boot/dts/arm/juno-scmi.dtsi @@ -154,6 +154,31 @@ power-domains = <&scmi_devpd 8>; }; +&cti0 { + power-domains = <&scmi_devpd 8>; +}; +&cti1 { + power-domains = <&scmi_devpd 8>; +}; +&cti2 { + power-domains = <&scmi_devpd 8>; +}; +&cti3 { + power-domains = <&scmi_devpd 8>; +}; +&cti4 { + power-domains = <&scmi_devpd 8>; +}; +&cti5 { + power-domains = <&scmi_devpd 8>; +}; +&cti_sys0 { + power-domains = <&scmi_devpd 8>; +}; +&cti_sys1 { + power-domains = <&scmi_devpd 8>; +}; + &gpu { clocks = <&scmi_dvfs 2>; power-domains = <&scmi_devpd 9>; diff --git a/arch/arm64/boot/dts/arm/juno.dts b/arch/arm64/boot/dts/arm/juno.dts index f00cffbd032c..dbc22e70b62c 100644 --- a/arch/arm64/boot/dts/arm/juno.dts +++ b/arch/arm64/boot/dts/arm/juno.dts @@ -9,6 +9,7 @@ /dts-v1/; #include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/arm/coresight-cti-dt.h> #include "juno-base.dtsi" / { @@ -295,3 +296,27 @@ &cpu_debug5 { cpu = <&A53_3>; }; + +&cti0 { + cpu = <&A57_0>; +}; + +&cti1 { + cpu = <&A57_1>; +}; + +&cti2 { + cpu = <&A53_0>; +}; + +&cti3 { + cpu = <&A53_1>; +}; + +&cti4 { + cpu = <&A53_2>; +}; + +&cti5 { + cpu = <&A53_3>; +}; -- 2.17.1

3 years, 7 months

Reference platform

by Hugh O'Keeffe

Hi Mike and Al, Any suggestions for a reference platform that we could start some OpenCSD and CSAL investigative engineering working on? Ideally: - Multi-core with SoC-600 and ELA-600 CoreSight - SoC-600 trace streaming interface between host and target using USB3.1 (i.e. no debug probe necessary) - Linux/Android Would appreciate your inputs Thanks Hugh -----Original Message----- From: Al Grant <Al.Grant(a)arm.com> Sent: Monday 28 March 2022 16:25 To: Mike Leach <mike.leach(a)linaro.org>; Hugh O'Keeffe <hugh.okeeffe(a)ashling.com> Cc: coresight(a)lists.linaro.org Subject: RE: CoreSight ELA-600 Embedded Logic Analyzer > -----Original Message----- > From: Mike Leach <mike.leach(a)linaro.org<mailto:mike.leach@linaro.org>> > Sent: 28 March 2022 12:44 > To: Hugh O'Keeffe <hugh.okeeffe(a)ashling.com<mailto:hugh.okeeffe@ashling.com>> > Cc: Al Grant <Al.Grant(a)arm.com<mailto:Al.Grant@arm.com>>; coresight(a)lists.linaro.org<mailto:coresight@lists.linaro.org> > Subject: Re: CoreSight ELA-600 Embedded Logic Analyzer > > Hi Hugh, > > On Mon, 28 Mar 2022 at 11:41, Hugh O'Keeffe <hugh.okeeffe(a)ashling.com<mailto:hugh.okeeffe@ashling.com>> > wrote: > > > > Hi Al and Mike, > > > > Appreciate your response. It seems that OpenCSD and CSAL are very > similar. Are they two different approaches to solving the same problem > OR in fact are they inherently different? I note that OpenCSD appears > to actually decode trace as well (which CSAL does not appear to support). > > > > CSAL primarily configures and programs CoreSight components using the > memory interface. Either bare metal, or under linux if the correct > memory access is allowed by the kernel configuration. It also has a > bunch of example programs demonstrating usage of the library, and > extracting trace on certain platforms. > > OpenCSD decodes any collected trace. It does not do any configuration > - but requires certain trace configuration values to be provided in > order to do the decode - alongside memory images if full CPU > instruction trace decode is required. > It does not do any data presentation or correlation - that is for any > client application to do - though it does have packet printing > routines that will give a human readable version of the decoded packets. > > OpenCSD is used by perf in linux to do all the decode for this tool. > > OpenCSD does come with its own standalone test program trc_pkt_lister > - which will decode trace snapshots and output packets in the readable > format mentioned above. These snapshots consist of trace data buffers > + a set of .ini type files that contain the configuration of the > hardware, and the memory images needed for full decode. If packet > decode only is required then the memory images can be omitted. The > specification for trace snapshots is provided in the OpenCSD github > repository, and example snapshots are also in the repository. > > There is no current ELA600 driver in the kernel - and I am unsure if > there is one in development. > If your ELA600 is configured to output to the Coresight trace bus - > then configuring using CSAL / decoding using OpenCSD would be a possible path. > If it is configured to use its own internal RAMs then OpenCSD will not help. > > As Al mentions, the actual format of any given ELA data is SoC > specific - so interpretation will have to be customized. > > Assuming you configure and get the device to trace into an ETR / ETF > then this data will be multiplexed into the CoreSight frame format - > on an ATID basis. > OpenCSD could help here in that the front end will demultiplex the > data to produce a byte stream input for a decoder based on the ATID. > OpenCSD contains an API that allows custom decoders to be registered > with the library. > Thus an ELA decoder can be registered, then an instance attached to > the ATID being used for the ELA600 and the library would feed the > demultiplexed stream to the decoder. Alternatively, it should be > relatively easy to write a simple program using the library demux > components to take in a formatted buffer and output a binary file of raw data for a given ATID. > > Regards > > Mike > > > Would appreciate any pointers or comments as to how they compare and > what would be my best starting point. Further to Mike's excellent summary, CSAL is really a few different things: - a pure C library for CoreSight configuration, suitable for embedding in firmware, RTOS, boot code etc. It can run over Linux /dev/mem, but this is more for general testing than expectation anyone would want to run it this way, especially now that Linux has its own drivers for ETM. In theory this could be combined with OpenCSD, i.e. use CSAL to configure a trace device and OpenCSD to decode it. I don't know that anyone has done that as CSAL's really designed for more limited targets where you’d likely decode the trace offline. - in coresight-tools (csscan.py and some kernel modules): tools for CoreSight device and topology discovery, and status reporting. The discovery phase is usally something that you'd only do once when you get a new target, as it may leave the target in odd states. Status reporting is harmless though and may be useful when diagnosing issues with kernel drivers, or even external debug. These Python tools can write to the CoreSight devices. This is required for topology discovery, but any kind of programming is possible if you know the register offsets and values. - for testing, there's a daemon (devmemd) which can run on a target to do the low-level register access, allowing all the complicated stuff done by CSAL and csscan.py to be run on your development machine where it may be easier to experiment with it. We also have some Python modules for decoding trace but these currentlly aren't upstream - you wouldn't want to use these for a production tool (you should use OpenCSD) but they may be useful when experimenting - I will look at getting them upstream. Al > > > > Thanks > > Hugh > > > > > > > > > > > > > > > > -----Original Message----- > > From: Al Grant <Al.Grant(a)arm.com<mailto:Al.Grant@arm.com>> > > Sent: Friday 25 March 2022 09:49 > > To: Mike Leach <mike.leach(a)linaro.org<mailto:mike.leach@linaro.org>>; Hugh O'Keeffe > > <hugh.okeeffe(a)ashling.com<mailto:hugh.okeeffe@ashling.com>> > > Cc: coresight(a)lists.linaro.org<mailto:coresight@lists.linaro.org> > > Subject: RE: CoreSight ELA-600 Embedded Logic Analyzer > > > > > On Thu, 24 Mar 2022 at 17:47, Hugh O'Keeffe > > > <hugh.okeeffe(a)ashling.com<mailto:hugh.okeeffe@ashling.com>> > > > wrote: > > > > > > > > Hi All, > > > > > > > > Couple of questions: > > > > > > > > 1. Does anyone know of any other software options other than > > > > DS-5 for > > > configuring, capturing and viewing data using the ELA-600 ? > > > > In https://github.com/ARM-software/CSAL, the csscan.py script has > > some > basic support for reading the ELA config and dumping its SRAM buffer. > No support for decoding ELA capture out of a CoreSight trace stream > though, as it was only tested on ELA-500. > > > > The assignment of input signals may be SoC-specific and there may > > also be > SoC-specific obfuscation applied to the data - this is one of those > "ask your SoC vendor" situations. The scripts that have gone upstream > don't reveal anything that is not already public. > > > > Al > > > > > > > > > > > > 2. I could roll my own but I don't think OpenCSD has support for > > > > the > > > > ELA- > > > 600. Correct ? > > > > > > > > > > As I maintain OpenCSD I can answer this second question.... > > > > > > No - there is not an ELA specific decoder in OpenCSD. Nor are > > > there plans to add one at present. > > > That said the the OpenCSD infrastucture should allow a new decode > > > module to be added easily. > > > > > > Regards > > > > > > Mike > > > > > > > > > > Thanks in advance > > > > > > > > Hugh > > > > > > > > > > > > > > > > > > > > > > > > -----Original Message----- > > > > From: coresight-request(a)lists.linaro.org<mailto:coresight-request@lists.linaro.org> > > > > <coresight-request(a)lists.linaro.org<mailto:coresight-request@lists.linaro.org>> > > > > Sent: Thursday 24 March 2022 17:36 > > > > To: Hugh O'Keeffe <hugh.okeeffe(a)ashling.com<mailto:hugh.okeeffe@ashling.com>> > > > > Subject: Welcome to the "CoreSight" mailing list > > > > > > > > Welcome to the "CoreSight" mailing list! > > > > > > > > To post to this list, send your message to: > > > > > > > > coresight(a)lists.linaro.org<mailto:coresight@lists.linaro.org> > > > > > > > > You can unsubscribe or make adjustments to your options via > > > > email by > > > sending a message to: > > > > > > > > coresight-request(a)lists.linaro.org<mailto:coresight-request@lists.linaro.org> > > > > > > > > with the word 'help' in the subject or body (don't include the > > > > quotes), and > > > you will get back a message with instructions. You will need your > > > password to change your options, but for security purposes, this > > > password is not included here. If you have forgotten your > > > password you will need to reset it via the web UI. > > > > _______________________________________________ > > > > CoreSight mailing list -- coresight(a)lists.linaro.org<mailto:coresight@lists.linaro.org> To > > > > unsubscribe send an email to coresight-leave(a)lists.linaro.org<mailto:coresight-leave@lists.linaro.org> > > > > > > > > > > > > -- > > > Mike Leach > > > Principal Engineer, ARM Ltd. > > > Manchester Design Centre. UK > > > _______________________________________________ > > > CoreSight mailing list -- coresight(a)lists.linaro.org<mailto:coresight@lists.linaro.org> To > > > unsubscribe send an email to coresight-leave(a)lists.linaro.org<mailto:coresight-leave@lists.linaro.org> > > > > -- > Mike Leach > Principal Engineer, ARM Ltd. > Manchester Design Centre. UK

3 years, 7 months

Re: [PATCH v4 01/10] Use IDR to maintain all the enabled sources' paths.

by Jinlong Mao

Hi Greg, Thanks for your review. On 3/24/2022 8:26 PM, Greg Kroah-Hartman wrote: > On Thu, Mar 24, 2022 at 08:17:25PM +0800, Mao Jinlong wrote: >> Use hash length of the source's device name to map to the pointer >> of the enabled path. Using IDR will be more efficient than using >> the list. And there could be other sources except STM and CPU etms >> in the new HWs. It is better to maintain all the paths together. >> >> Signed-off-by: Mao Jinlong <quic_jinlmao(a)quicinc.com> >> --- >> drivers/hwtracing/coresight/coresight-core.c | 75 +++++++------------- >> 1 file changed, 26 insertions(+), 49 deletions(-) > Your subject line is odd. Please put back the driver subsystem in the > subject line so that it makes more sense. I will update the subject in next version. > > And how have you measured "more efficient"? Using IDR would be better than doing a sequential search as there will be much more device in future. > > thanks, > > greg k-h Thanks Jinlong Mao

3 years, 7 months

Re: [PATCH v4 01/10] Use IDR to maintain all the enabled sources' paths.

by Jinlong Mao

Hi Greg, On 3/25/2022 1:06 AM, Greg Kroah-Hartman wrote: > On Thu, Mar 24, 2022 at 10:23:19PM +0800, Jinlong Mao wrote: >> Hi Greg, >> >> Thanks for your review. >> >> On 3/24/2022 8:26 PM, Greg Kroah-Hartman wrote: >>> On Thu, Mar 24, 2022 at 08:17:25PM +0800, Mao Jinlong wrote: >>>> Use hash length of the source's device name to map to the pointer >>>> of the enabled path. Using IDR will be more efficient than using >>>> the list. And there could be other sources except STM and CPU etms >>>> in the new HWs. It is better to maintain all the paths together. >>>> >>>> Signed-off-by: Mao Jinlong <quic_jinlmao(a)quicinc.com> >>>> --- >>>> drivers/hwtracing/coresight/coresight-core.c | 75 +++++++------------- >>>> 1 file changed, 26 insertions(+), 49 deletions(-) >>> Your subject line is odd. Please put back the driver subsystem in the >>> subject line so that it makes more sense. >> I will update the subject in next version. >>> And how have you measured "more efficient"? >> Using IDR would be better than doing a sequential search as there will be >> much more device in future. > How many "more"? Where does the trade off of speed for complexity help? > How much faster is this really? You can't claim performance > improvements without any proof :) There is about 40 trace sources in our internal device. I believe there will be more cpu cores, then there will be more etm sources. IDR here is used to store the path of both etm sources and other sources which aren't associated with CPU. Use IDR is not more complicated than using list. It will also save the time of searching the path when coresight_disable. I tested in internal device. The test case is that enable all the sources, disable the source one by one to check the search time. Use list to store paths: sh-7687 [005] .... 342.113099: __coresight_disable: ====search path start==== source_0 sh-7687 [005] .... 342.113127: __coresight_disable: ====search path end==== source_0 sh-7693 [005] .... 342.542216: __coresight_disable: ====search path start==== source_1 sh-7693 [005] .... 342.542244: __coresight_disable: ====search path end==== source_1 sh-7699 [005] .... 342.929083: __coresight_disable: ====search path start==== source_2 sh-7699 [005] .... 342.929106: __coresight_disable: ====search path end==== source_2 sh-7711 [005] .... 343.760688: __coresight_disable: ====search path start==== source_3 sh-7711 [005] .... 343.760713: __coresight_disable: ====search path end==== source_3 sh-7717 [005] .... 344.172353: __coresight_disable: ====search path start==== source_4 sh-7717 [005] .... 344.172381: __coresight_disable: ====search path end==== source_4 Use IDR to store paths: sh-7156 [006] .... 223.294228: __coresight_disable: ====search path start==== source_0 sh-7156 [006] .... 223.294237: __coresight_disable: ====search path end==== source_0 sh-7162 [006] .... 223.690153: __coresight_disable: ====search path start==== source_1 sh-7162 [006] .... 223.690163: __coresight_disable: ====search path end==== source_1 sh-7168 [006] .... 224.110670: __coresight_disable: ====search path start==== source_2 sh-7168 [006] .... 224.110679: __coresight_disable: ====search path end==== source_2 <...>-7180 [006] .... 224.929315: __coresight_disable: ====search path start==== source_3 <...>-7180 [006] .... 224.929324: __coresight_disable: ====search path end==== source_3 <...>-7186 [006] .... 225.343617: __coresight_disable: ====search path start==== source_4 <...>-7186 [006] .... 225.343626: __coresight_disable: ====search path end==== source_4 From the log, Searching the path from the IDR takes about 9us for each source. Searching the path from the list takes about 23 ~ 28us for the source. Use IDR saves much time. Thanks Jinlong Mao > > thanks, > > greg k-h

3 years, 7 months

CoreSight ELA-600 Embedded Logic Analyzer

by Hugh O'Keeffe

Hi All, Couple of questions: 1. Does anyone know of any other software options other than DS-5 for configuring, capturing and viewing data using the ELA-600 ? 2. I could roll my own but I don't think OpenCSD has support for the ELA-600. Correct ? Thanks in advance Hugh -----Original Message----- From: coresight-request(a)lists.linaro.org <coresight-request(a)lists.linaro.org> Sent: Thursday 24 March 2022 17:36 To: Hugh O'Keeffe <hugh.okeeffe(a)ashling.com> Subject: Welcome to the "CoreSight" mailing list Welcome to the "CoreSight" mailing list! To post to this list, send your message to: coresight(a)lists.linaro.org You can unsubscribe or make adjustments to your options via email by sending a message to: coresight-request(a)lists.linaro.org with the word 'help' in the subject or body (don't include the quotes), and you will get back a message with instructions. You will need your password to change your options, but for security purposes, this password is not included here. If you have forgotten your password you will need to reset it via the web UI.

3 years, 7 months

[PATCH v4] drivers/coresight: Add Ultrasoc System Memory Buffer driver

by Qi Liu

This patch adds driver for Ultrasoc SMB(System Memory Buffer) device. SMB provides a way to buffer messages from ETM, and store these CPU instructions in system memory. SMB is developed by Ultrasoc technology, which is acquired by Siemens, and we still use "Ultrasoc" to name driver. Signed-off-by: Qi Liu <liuqi115(a)huawei.com> Tested-by: JunHao He <hejunhao2(a)hisilicon.com> --- Change since v3: - Modify the file header according to community specifications. - Address the comments from Mathieu. - Link:https://lore.kernel.org/linux-arm-kernel/20211118110016.40398-1-liuqi1… Change since v2: - Move ultrasoc driver to drivers/hwtracing/coresight. - Link:https://lists.linaro.org/pipermail/coresight/2021-November/007310.html Change since v1: - Drop the document of Ultrasoc according to Mathieu's comment. - Add comments to explain some private hardware settings. - Address the comments from Mathieu. - Link: https://lists.linaro.org/pipermail/coresight/2021-August/006842.html Change since RFC: - Move ultrasoc driver to drivers/hwtracing/coresight/ultrasoc. - Remove ultrasoc-axi-com.c, as AXI-COM doesn't need to be configured in basic tracing function. - Remove ultrasoc.c as SMB does not need to register with the ultrasoc core. - Address the comments from Mathieu and Suzuki. - Link: https://lists.linaro.org/pipermail/coresight/2021-June/006535.html drivers/hwtracing/coresight/Kconfig | 10 + drivers/hwtracing/coresight/Makefile | 1 + drivers/hwtracing/coresight/ultrasoc-smb.c | 602 +++++++++++++++++++++ drivers/hwtracing/coresight/ultrasoc-smb.h | 100 ++++ 4 files changed, 713 insertions(+) create mode 100644 drivers/hwtracing/coresight/ultrasoc-smb.c create mode 100644 drivers/hwtracing/coresight/ultrasoc-smb.h diff --git a/drivers/hwtracing/coresight/Kconfig b/drivers/hwtracing/coresight/Kconfig index 514a9b8086e3..32b87df9994a 100644 --- a/drivers/hwtracing/coresight/Kconfig +++ b/drivers/hwtracing/coresight/Kconfig @@ -201,4 +201,14 @@ config CORESIGHT_TRBE To compile this driver as a module, choose M here: the module will be called coresight-trbe. +config ULTRASOC_SMB + tristate "Ultrasoc system memory buffer drivers" + depends on ARM64 && CORESIGHT_LINKS_AND_SINKS + help + This driver provides support for the Ultrasoc system memory buffer (SMB). + SMB is responsible for receiving the trace data from Coresight ETM devices + and storing them to a system buffer. + + To compile this driver as a module, choose M here: the module will be + called ultrasoc-smb. endif diff --git a/drivers/hwtracing/coresight/Makefile b/drivers/hwtracing/coresight/Makefile index b6c4a48140ec..344dba8d6ff8 100644 --- a/drivers/hwtracing/coresight/Makefile +++ b/drivers/hwtracing/coresight/Makefile @@ -27,3 +27,4 @@ obj-$(CONFIG_CORESIGHT_CTI) += coresight-cti.o obj-$(CONFIG_CORESIGHT_TRBE) += coresight-trbe.o coresight-cti-y := coresight-cti-core.o coresight-cti-platform.o \ coresight-cti-sysfs.o +obj-$(CONFIG_ULTRASOC_SMB) += ultrasoc-smb.o diff --git a/drivers/hwtracing/coresight/ultrasoc-smb.c b/drivers/hwtracing/coresight/ultrasoc-smb.c new file mode 100644 index 000000000000..a18d061aab61 --- /dev/null +++ b/drivers/hwtracing/coresight/ultrasoc-smb.c @@ -0,0 +1,602 @@ +// SPDX-License-Identifier: MIT/GPL +/* + * Siemens System Memory Buffer driver. + * Copyright(c) 2022, HiSilicon Limited. + */ + +#include <linux/acpi.h> +#include <linux/circ_buf.h> +#include <linux/err.h> +#include <linux/module.h> +#include <linux/mod_devicetable.h> +#include <linux/platform_device.h> + +#include "ultrasoc-smb.h" + +DEFINE_CORESIGHT_DEVLIST(sink_devs, "smb"); + +static bool smb_buffer_is_empty(struct smb_drv_data *drvdata) +{ + u32 buf_status = readl(drvdata->base + SMB_LB_INT_STS); + + return buf_status & BIT(0) ? false : true; +} + +static bool smb_buffer_cmp_pointer(struct smb_drv_data *drvdata) +{ + u32 wr_offset, rd_offset; + + wr_offset = readl(drvdata->base + SMB_LB_WR_ADDR); + rd_offset = readl(drvdata->base + SMB_LB_RD_ADDR); + return wr_offset == rd_offset; +} + +static void smb_reset_buffer_status(struct smb_drv_data *drvdata) +{ + writel(0xf, drvdata->base + SMB_LB_INT_STS); +} + +/* Purge data remaining in hardware path to SMB. */ +static void smb_purge_data(struct smb_drv_data *drvdata) +{ + writel(0x1, drvdata->base + SMB_LB_PURGE); +} + +static void smb_update_data_size(struct smb_drv_data *drvdata) +{ + struct smb_data_buffer *sdb = &drvdata->sdb; + u32 write_offset; + + smb_purge_data(drvdata); + if (smb_buffer_cmp_pointer(drvdata)) { + if (smb_buffer_is_empty(drvdata)) + sdb->data_size = 0; + else + sdb->data_size = sdb->buf_size; + return; + } + + write_offset = readl(drvdata->base + SMB_LB_WR_ADDR) - sdb->start_addr; + sdb->data_size = CIRC_CNT(write_offset, sdb->rd_offset, sdb->buf_size); +} + +static int smb_open(struct inode *inode, struct file *file) +{ + struct smb_drv_data *drvdata = container_of(file->private_data, + struct smb_drv_data, miscdev); + + if (local_cmpxchg(&drvdata->reading, 0, 1)) + return -EBUSY; + + return 0; +} + +static ssize_t smb_read(struct file *file, char __user *data, size_t len, loff_t *ppos) +{ + struct smb_drv_data *drvdata = container_of(file->private_data, + struct smb_drv_data, miscdev); + struct smb_data_buffer *sdb = &drvdata->sdb; + struct device *dev = &drvdata->csdev->dev; + unsigned long flags; + int to_copy = 0; + + spin_lock_irqsave(&drvdata->spinlock, flags); + + if (!sdb->data_size) { + smb_update_data_size(drvdata); + if (!sdb->data_size) + goto out; + } + + if (atomic_read(drvdata->csdev->refcnt)) { + to_copy = -EBUSY; + goto out; + } + + to_copy = min(sdb->data_size, len); + + /* Copy parts of trace data when the read pointer will wrap around SMB buffer. */ + if (sdb->rd_offset + to_copy > sdb->buf_size) + to_copy = sdb->buf_size - sdb->rd_offset; + + if (copy_to_user(data, (void *)sdb->buf_base + sdb->rd_offset, to_copy)) { + dev_dbg(dev, "Failed to copy data to user\n"); + to_copy = -EFAULT; + goto out; + } + + *ppos += to_copy; + sdb->data_size -= to_copy; + sdb->rd_offset += to_copy; + sdb->rd_offset %= sdb->buf_size; + writel(sdb->start_addr + sdb->rd_offset, drvdata->base + SMB_LB_RD_ADDR); + dev_dbg(dev, "%d bytes copied\n", to_copy); +out: + if (!sdb->data_size) + smb_reset_buffer_status(drvdata); + spin_unlock_irqrestore(&drvdata->spinlock, flags); + return to_copy; +} + +static int smb_release(struct inode *inode, struct file *file) +{ + struct smb_drv_data *drvdata = container_of(file->private_data, + struct smb_drv_data, miscdev); + local_set(&drvdata->reading, 0); + return 0; +} + +static const struct file_operations smb_fops = { + .owner = THIS_MODULE, + .open = smb_open, + .read = smb_read, + .release = smb_release, + .llseek = no_llseek, +}; + +smb_reg(read_pos, SMB_LB_RD_ADDR); +smb_reg(write_pos, SMB_LB_WR_ADDR); +smb_reg(buf_status, SMB_LB_INT_STS); + +static ssize_t buf_size_show(struct device *dev, struct device_attribute *attr, char *buf) +{ + struct smb_drv_data *drvdata = dev_get_drvdata(dev->parent); + + return sysfs_emit(buf, "0x%lx\n", drvdata->sdb.buf_size); +} +static DEVICE_ATTR_RO(buf_size); + +static struct attribute *smb_sink_attrs[] = { + &dev_attr_read_pos.attr, + &dev_attr_write_pos.attr, + &dev_attr_buf_status.attr, + &dev_attr_buf_size.attr, + NULL, +}; + +static const struct attribute_group smb_sink_group = { + .attrs = smb_sink_attrs, + .name = "status", +}; + +static const struct attribute_group *smb_sink_groups[] = { + &smb_sink_group, + NULL, +}; + +static int smb_set_perf_buffer(struct perf_output_handle *handle) +{ + struct cs_buffers *buf = etm_perf_sink_config(handle); + u32 head; + + if (!buf) + return -EINVAL; + + /* Wrap head around to the amount of space we have */ + head = handle->head & ((buf->nr_pages << PAGE_SHIFT) - 1); + + /* Find the page to write to and offset within that page */ + buf->cur = head / PAGE_SIZE; + buf->offset = head % PAGE_SIZE; + + local_set(&buf->data_size, 0); + + return 0; +} + +static void smb_enable_hw(struct smb_drv_data *drvdata) +{ + writel(0x1, drvdata->base + SMB_GLOBAL_EN); +} + +static void smb_disable_hw(struct smb_drv_data *drvdata) +{ + writel(0x0, drvdata->base + SMB_GLOBAL_EN); +} + +static int smb_enable_sysfs(struct smb_drv_data *drvdata) +{ + if (drvdata->mode == CS_MODE_PERF) + return -EBUSY; + + if (drvdata->mode == CS_MODE_SYSFS) + return 0; + + smb_enable_hw(drvdata); + drvdata->mode = CS_MODE_SYSFS; + return 0; +} + +static int smb_enable_perf(struct smb_drv_data *drvdata, void *data) +{ + struct device *dev = &drvdata->csdev->dev; + struct perf_output_handle *handle = data; + pid_t pid; + + if (drvdata->mode == CS_MODE_SYSFS) { + dev_err(dev, "Device is already in used by sysfs\n"); + return -EBUSY; + } + + /* Get a handle on the pid of the target process*/ + pid = task_pid_nr(handle->event->owner); + if (drvdata->pid != -1 && drvdata->pid != pid) { + dev_err(dev, "Device is already in used by other session\n"); + return -EBUSY; + } + /* The sink is already enabled by this session. */ + if (drvdata->pid == pid) + return 0; + + if (smb_set_perf_buffer(handle)) + return -EINVAL; + + smb_enable_hw(drvdata); + drvdata->pid = pid; + drvdata->mode = CS_MODE_PERF; + + return 0; +} + +static int smb_enable(struct coresight_device *csdev, u32 mode, void *data) +{ + struct smb_drv_data *drvdata = dev_get_drvdata(csdev->dev.parent); + unsigned long flags; + int ret = -EINVAL; + + /* Do nothing if trace data is reading by other interface now. */ + if (local_read(&drvdata->reading)) + return -EBUSY; + + spin_lock_irqsave(&drvdata->spinlock, flags); + + if (mode == CS_MODE_SYSFS) + ret = smb_enable_sysfs(drvdata); + + if (mode == CS_MODE_PERF) + ret = smb_enable_perf(drvdata, data); + + spin_unlock_irqrestore(&drvdata->spinlock, flags); + + if (ret) + return ret; + + atomic_inc(csdev->refcnt); + dev_dbg(&csdev->dev, "Ultrasoc SMB enabled\n"); + + return 0; +} + +static int smb_disable(struct coresight_device *csdev) +{ + struct smb_drv_data *drvdata = dev_get_drvdata(csdev->dev.parent); + unsigned long flags; + + spin_lock_irqsave(&drvdata->spinlock, flags); + + if (atomic_dec_return(csdev->refcnt)) { + spin_unlock_irqrestore(&drvdata->spinlock, flags); + return -EBUSY; + } + + WARN_ON_ONCE(drvdata->mode == CS_MODE_DISABLED); + smb_disable_hw(drvdata); + + /* + * Data remaining in hardware path will be sent to SMB after purge, so needs to + * synchronize the read pointer to write pointer in perf mode. + */ + smb_purge_data(drvdata); + if (drvdata->mode == CS_MODE_PERF) + writel(readl(drvdata->base + SMB_LB_WR_ADDR), drvdata->base + SMB_LB_RD_ADDR); + + /* Dissociate from the target process. */ + drvdata->pid = -1; + drvdata->mode = CS_MODE_DISABLED; + spin_unlock_irqrestore(&drvdata->spinlock, flags); + + dev_dbg(&csdev->dev, "Ultrasoc SMB disabled\n"); + return 0; +} + +static void *smb_alloc_buffer(struct coresight_device *csdev, + struct perf_event *event, void **pages, + int nr_pages, bool overwrite) +{ + struct cs_buffers *buf; + int node; + + node = (event->cpu == -1) ? NUMA_NO_NODE : cpu_to_node(event->cpu); + buf = kzalloc_node(sizeof(*buf), GFP_KERNEL, node); + if (!buf) + return NULL; + + buf->snapshot = overwrite; + buf->nr_pages = nr_pages; + buf->data_pages = pages; + + return buf; +} + +static void smb_free_buffer(void *config) +{ + struct cs_buffers *buf = config; + + kfree(buf); +} + +static void smb_sync_perf_buffer(struct smb_drv_data *drvdata, + struct cs_buffers *buf, unsigned long data_size) +{ + struct smb_data_buffer *sdb = &drvdata->sdb; + char **dst_pages = (char **)buf->data_pages; + unsigned long buf_offset = buf->offset; + unsigned int cur = buf->cur; + unsigned long to_copy; + + while (data_size) { + /* Copy parts of trace data when the read pointer will wrap around SMB buffer. */ + if (sdb->rd_offset + PAGE_SIZE - buf_offset > sdb->buf_size) + to_copy = sdb->buf_size - sdb->rd_offset; + else + to_copy = min(data_size, PAGE_SIZE - buf_offset); + + memcpy_fromio(dst_pages[cur] + buf_offset, sdb->buf_base + sdb->rd_offset, to_copy); + + buf_offset += to_copy; + if (buf_offset >= PAGE_SIZE) { + buf_offset = 0; + cur++; + cur %= buf->nr_pages; + } + data_size -= to_copy; + /* ensure memcpy finished before update the read pointer */ + sdb->rd_offset += to_copy; + sdb->rd_offset %= sdb->buf_size; + } + + sdb->data_size = 0; + writel(sdb->start_addr + sdb->rd_offset, drvdata->base + SMB_LB_RD_ADDR); + smb_reset_buffer_status(drvdata); +} + +static unsigned long smb_update_buffer(struct coresight_device *csdev, + struct perf_output_handle *handle, + void *sink_config) +{ + struct smb_drv_data *drvdata = dev_get_drvdata(csdev->dev.parent); + struct smb_data_buffer *sdb = &drvdata->sdb; + struct cs_buffers *buf = sink_config; + unsigned long data_size = 0; + unsigned long flags; + bool lost = false; + + if (!buf) + return 0; + + spin_lock_irqsave(&drvdata->spinlock, flags); + + /* Don't do anything if another tracer is using this sink. */ + if (atomic_read(csdev->refcnt) != 1) + goto out; + + smb_update_data_size(drvdata); + data_size = sdb->data_size; + if (data_size > handle->size) { + sdb->rd_offset += data_size - handle->size; + sdb->rd_offset %= sdb->buf_size; + data_size = handle->size; + lost = true; + } + + smb_sync_perf_buffer(drvdata, buf, data_size); + if (!buf->snapshot && lost) + perf_aux_output_flag(handle, PERF_AUX_FLAG_TRUNCATED); + +out: + spin_unlock_irqrestore(&drvdata->spinlock, flags); + return data_size; +} + +static const struct coresight_ops_sink smb_cs_ops = { + .enable = smb_enable, + .disable = smb_disable, + .alloc_buffer = smb_alloc_buffer, + .free_buffer = smb_free_buffer, + .update_buffer = smb_update_buffer, +}; + +static const struct coresight_ops cs_ops = { + .sink_ops = &smb_cs_ops, +}; + +static int smb_init_data_buffer(struct platform_device *pdev, struct smb_data_buffer *sdb) +{ + struct resource *res; + void __iomem *base; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 1); + if (IS_ERR(res)) { + dev_err(&pdev->dev, "SMB device failed to get resource\n"); + return -EINVAL; + } + + sdb->start_addr = res->start & SMB_BASE_LOW_MASK; + sdb->buf_size = resource_size(res); + if (sdb->buf_size == 0) + return -EINVAL; + + base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(base)) + return PTR_ERR(base); + + sdb->buf_base = base; + + return 0; +} + +static void smb_init_hw(struct smb_drv_data *drvdata) +{ + u32 value; + + /* First disable smb and clear the status of SMB buffer */ + smb_reset_buffer_status(drvdata); + smb_disable_hw(drvdata); + smb_purge_data(drvdata); + + /* Using smb in single-end mode, and set other configures default */ + value = SMB_BUF_CFG_STREAMING | SMB_BUF_SINGLE_END | SMB_BUF_EN; + writel(value, drvdata->base + SMB_LB_CFG_LO); + value = SMB_MSG_FILTER(0x0, 0xff); + writel(value, drvdata->base + SMB_LB_CFG_HI); + + writel(SMB_GLOBAL_CFG, drvdata->base + SMB_CFG_REG); + writel(SMB_GLB_INT_CFG, drvdata->base + SMB_GLOBAL_INT); + writel(SMB_BUF_INT_CFG, drvdata->base + SMB_LB_INT_CTRL); +} + +static int smb_register_sink(struct platform_device *pdev, struct smb_drv_data *drvdata) +{ + struct coresight_platform_data *pdata = NULL; + struct coresight_desc desc = { 0 }; + int ret; + + pdata = coresight_get_platform_data(&pdev->dev); + if (IS_ERR(pdata)) + return PTR_ERR(pdata); + + desc.type = CORESIGHT_DEV_TYPE_SINK; + desc.subtype.sink_subtype = CORESIGHT_DEV_SUBTYPE_SINK_BUFFER; + desc.ops = &cs_ops; + desc.pdata = pdata; + desc.dev = &pdev->dev; + desc.groups = smb_sink_groups; + desc.name = coresight_alloc_device_name(&sink_devs, &pdev->dev); + if (!desc.name) { + dev_err(&pdev->dev, "Failed to alloc coresight device name"); + return -ENOMEM; + } + + drvdata->csdev = coresight_register(&desc); + if (IS_ERR(drvdata->csdev)) + return PTR_ERR(drvdata->csdev); + + drvdata->miscdev.name = desc.name; + drvdata->miscdev.minor = MISC_DYNAMIC_MINOR; + drvdata->miscdev.fops = &smb_fops; + ret = misc_register(&drvdata->miscdev); + if (ret) { + coresight_unregister(drvdata->csdev); + dev_err(&pdev->dev, "Failed to register misc: %d\n", ret); + } + + return ret; +} + +static void smb_unregister_sink(struct smb_drv_data *drvdata) +{ + misc_deregister(&drvdata->miscdev); + coresight_unregister(drvdata->csdev); +} + +/* + * Send ultrasoc messge to control hardwares on the tracing path, + * using DSM calls to avoid exposing ultrasoc message format. + */ +static int smb_config_inport(struct device *dev, bool enable) +{ + u32 flag = enable ? 1 : 0; + union acpi_object *obj; + guid_t guid; + + if (guid_parse("82ae1283-7f6a-4cbe-aa06-53e8fb24db18", &guid)) { + dev_err(dev, "Get GUID failed\n"); + return -EINVAL; + } + + obj = acpi_evaluate_dsm(ACPI_HANDLE(dev), &guid, 0, flag, NULL); + if (!obj) + dev_err(dev, "ACPI handle failed\n"); + else + ACPI_FREE(obj); + + return 0; +} + +static int smb_probe(struct platform_device *pdev) +{ + struct smb_drv_data *drvdata; + int ret; + + drvdata = devm_kzalloc(&pdev->dev, sizeof(*drvdata), GFP_KERNEL); + if (!drvdata) + return -ENOMEM; + + drvdata->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(drvdata->base)) { + dev_err(&pdev->dev, "Failed to ioremap resource\n"); + return PTR_ERR(drvdata->base); + } + + ret = smb_init_data_buffer(pdev, &drvdata->sdb); + if (ret) { + dev_err(&pdev->dev, "Failed to init buffer: %d\n", ret); + return ret; + } + + smb_init_hw(drvdata); + spin_lock_init(&drvdata->spinlock); + drvdata->pid = -1; + + ret = smb_register_sink(pdev, drvdata); + if (ret) { + dev_err(&pdev->dev, "Failed to register smb sink\n"); + return ret; + } + + ret = smb_config_inport(&pdev->dev, true); + if (ret) { + smb_unregister_sink(drvdata); + return ret; + } + + platform_set_drvdata(pdev, drvdata); + return 0; +} + +static int smb_remove(struct platform_device *pdev) +{ + struct smb_drv_data *drvdata = platform_get_drvdata(pdev); + int ret; + + ret = smb_config_inport(&pdev->dev, false); + if (ret) + return ret; + + smb_unregister_sink(drvdata); + return 0; +} + +#ifdef CONFIG_ACPI +static const struct acpi_device_id ultrasoc_smb_acpi_match[] = { + {"HISI03A1", 0}, + {}, +}; +MODULE_DEVICE_TABLE(acpi, ultrasoc_smb_acpi_match); +#endif + +static struct platform_driver smb_driver = { + .driver = { + .name = "ultrasoc-smb", + .acpi_match_table = ACPI_PTR(ultrasoc_smb_acpi_match), + .suppress_bind_attrs = true, + }, + .probe = smb_probe, + .remove = smb_remove, +}; +module_platform_driver(smb_driver); + +MODULE_DESCRIPTION("Ultrasoc smb driver"); +MODULE_LICENSE("Dual MIT/GPL"); +MODULE_AUTHOR("Jonathan Zhou <jonathan.zhouwen(a)huawei.com>"); +MODULE_AUTHOR("Qi Liu <liuqi115(a)huawei.com>"); diff --git a/drivers/hwtracing/coresight/ultrasoc-smb.h b/drivers/hwtracing/coresight/ultrasoc-smb.h new file mode 100644 index 000000000000..a7c76140ee46 --- /dev/null +++ b/drivers/hwtracing/coresight/ultrasoc-smb.h @@ -0,0 +1,100 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Siemens System Memory Buffer driver. + * Copyright(c) 2022, HiSilicon Limited. + */ + +#ifndef _ULTRASOC_SMB_H +#define _ULTRASOC_SMB_H + +#include <linux/coresight.h> +#include <linux/list.h> +#include <linux/miscdevice.h> + +#include "coresight-etm-perf.h" +#include "coresight-priv.h" + +/* Offset of SMB logical buffer registers */ +#define SMB_CFG_REG 0X0 +#define SMB_GLOBAL_EN 0X4 +#define SMB_GLOBAL_INT 0X8 +#define SMB_LB_CFG_LO 0X40 +#define SMB_LB_CFG_HI 0X44 +#define SMB_LB_INT_CTRL 0X48 +#define SMB_LB_INT_STS 0X4C +#define SMB_LB_LIMIT 0X58 +#define SMB_LB_RD_ADDR 0X5C +#define SMB_LB_WR_ADDR 0X60 +#define SMB_LB_PURGE 0X64 + +/* Set SMB_CFG_REG register */ +#define SMB_IDLE_PRD(period) ((((period) - 216) & 0xf) << 12) +#define SMB_MEM_WR(credit, rate) (((credit) << 16) | ((rate) << 18)) +#define SMB_MEM_RD(credit, rate) (((credit) << 22) | ((rate) << 24)) +#define SMB_BURST_LEN(len) (((len) - 1) << 4) +#define SMB_GLOBAL_CFG (SMB_IDLE_PRD(231) | SMB_MEM_WR(0x3, 0x0) | \ + SMB_MEM_RD(0x3, 0x6) | SMB_BURST_LEN(16)) + +/* Set SMB_GLOBAL_INT register */ +#define SMB_INT_EN BIT(0) +#define SMB_INT_TYPE_PULSE BIT(1) +#define SMB_INT_POLARITY_HIGH BIT(2) +#define SMB_GLB_INT_CFG (SMB_INT_EN | SMB_INT_TYPE_PULSE | SMB_INT_POLARITY_HIGH) + +/* Set SMB_LB_CFG_LO register */ +#define SMB_BUF_EN BIT(0) +#define SMB_BUF_SINGLE_END BIT(1) +#define SMB_BUF_INIT BIT(8) +#define SMB_BUF_CONTINUOUS BIT(11) +#define SMB_FLOW_MASK GENMASK(19, 16) +#define SMB_BUF_CFG_STREAMING (SMB_BUF_INIT | SMB_BUF_CONTINUOUS | SMB_FLOW_MASK) +#define SMB_BASE_LOW_MASK GENMASK(31, 0) + +/* Set SMB_LB_CFG_HI register */ +#define SMB_MSG_FILTER(lower, upper) (((lower) & 0xff) | (((upper) & 0xff) << 8)) +#define SMB_BUF_INT_EN BIT(0) +#define SMB_BUF_NOTE_MASK GENMASK(11, 8) +#define SMB_BUF_INT_CFG (SMB_BUF_INT_EN | SMB_BUF_NOTE_MASK) + +/** + * struct smb_data_buffer - Details of the buffer used by SMB + * @buf_base : Memory mapped base address of SMB. + * @start_addr : SMB buffer start Physical address. + * @buf_size : Size of the buffer. + * @data_size : Size of Trace data copy to userspace. + * @rd_offset : Offset of the read pointer in the buffer. + */ +struct smb_data_buffer { + void __iomem *buf_base; + u32 start_addr; + unsigned long buf_size; + unsigned long data_size; + unsigned long rd_offset; +}; + +/** + * struct smb_drv_data - specifics associated to an SMB component + * @base : Memory mapped base address for SMB component. + * @csdev : Component vitals needed by the framework. + * @sdb : Data buffer for SMB. + * @miscdev : Specifics to handle "/dev/smb" entry. + * @spinlock : Only one at a time pls. + * @reading : Synchronise user space access to SMB buffer. + * @pid : Process ID of the process being monitored by the session + * that is using this component. + * @mode : how this SMB is being used, perf mode or sysfs mode. + */ +struct smb_drv_data { + void __iomem *base; + struct coresight_device *csdev; + struct smb_data_buffer sdb; + struct miscdevice miscdev; + spinlock_t spinlock; + local_t reading; + pid_t pid; + u32 mode; +}; + +#define smb_reg(name, offset) coresight_simple_reg32(struct smb_drv_data, name, offset) + +#endif -- 2.24.0

3 years, 7 months

Re: [PATCH v4 05/10] coresight-tpdm: Add integration test support

by Jinlong Mao

Hi Greg, On 3/24/2022 8:28 PM, Greg Kroah-Hartman wrote: > On Thu, Mar 24, 2022 at 08:17:29PM +0800, Mao Jinlong wrote: >> Integration test for tpdm can help to generate the data for >> verification of the topology during TPDM software bring up. >> >> Sample: >> echo 1 > /sys/bus/coresight/devices/tmc_etf0/enable_sink >> echo 1 > /sys/bus/coresight/devices/tpdm1/enable_source >> echo 1 > /sys/bus/coresight/devices/tpdm1/integration_test >> echo 2 > /sys/bus/coresight/devices/tpdm1/integration_test >> cat /dev/tmc_etf0 > /data/etf-tpdm1.bin >> >> Signed-off-by: Tao Zhang <quic_taozha(a)quicinc.com> >> Signed-off-by: Mao Jinlong <quic_jinlmao(a)quicinc.com> >> --- >> drivers/hwtracing/coresight/Kconfig | 9 ++++ >> drivers/hwtracing/coresight/coresight-tpdm.c | 56 +++++++++++++++++++- >> drivers/hwtracing/coresight/coresight-tpdm.h | 8 +++ >> 3 files changed, 72 insertions(+), 1 deletion(-) >> >> diff --git a/drivers/hwtracing/coresight/Kconfig b/drivers/hwtracing/coresight/Kconfig >> index 5c506a1cd08f..60248fef4089 100644 >> --- a/drivers/hwtracing/coresight/Kconfig >> +++ b/drivers/hwtracing/coresight/Kconfig >> @@ -214,4 +214,13 @@ config CORESIGHT_TPDM >> To compile this driver as a module, choose M here: the module will be >> called coresight-tpdm. >> >> +config CORESIGHT_TPDM_INTEGRATION_TEST >> + bool "Enable CoreSight Integration Test For TPDM" >> + depends on CORESIGHT_TPDM >> + help >> + This option adds support for the CoreSight integration test on this >> + devie. Coresight architecture provides integration control modes of >> + operation to facilitate integration testing and software bringup >> + and/or to instrument topology discovery. The TPDM utilizes integration >> + mode to accomplish integration testing and software bringup. > Why is this a Kconfig option? Why would you never not want this? I refer to "CONFIG_CORESIGHT_CTI_INTEGRATION_REGS" for integration mode. > >> endif >> diff --git a/drivers/hwtracing/coresight/coresight-tpdm.c b/drivers/hwtracing/coresight/coresight-tpdm.c >> index a8d257a591f3..cddd398be0cd 100644 >> --- a/drivers/hwtracing/coresight/coresight-tpdm.c >> +++ b/drivers/hwtracing/coresight/coresight-tpdm.c >> @@ -124,7 +124,60 @@ static void tpdm_init_default_data(struct tpdm_drvdata *drvdata) >> __set_bit(i, drvdata->datasets); >> } >> CS_LOCK(drvdata->base); >> - } >> +} >> + >> +#ifdef CONFIG_CORESIGHT_TPDM_INTEGRATION_TEST > Try to keep #ifdefs out of .c files please. I will check to see if it is possible for the integration test function. >> +static ssize_t integration_test_store(struct device *dev, >> + struct device_attribute *attr, >> + const char *buf, >> + size_t size) >> +{ >> + int i, ret = 0; >> + unsigned long val; >> + struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent); >> + >> + ret = kstrtoul(buf, 10, &val); >> + if (ret) >> + return ret; >> + >> + if (val != 1 && val != 2) >> + return -EINVAL; >> + >> + if (!drvdata->enable) >> + return -EINVAL; >> + >> + if (val == 1) >> + val = ATBCNTRL_VAL_64; >> + else >> + val = ATBCNTRL_VAL_32; >> + CS_UNLOCK(drvdata->base); >> + writel_relaxed(0x1, drvdata->base + TPDM_ITCNTRL); >> + >> + for (i = 1; i < 5; i++) >> + writel_relaxed(val, drvdata->base + TPDM_ITATBCNTRL); >> + >> + writel_relaxed(0, drvdata->base + TPDM_ITCNTRL); >> + CS_LOCK(drvdata->base); >> + return size; >> +} >> +static DEVICE_ATTR_WO(integration_test); >> +#endif /* CORESIGHT_TPDM_INTEGRATION_TEST */ >> + >> +static struct attribute *tpdm_attrs[] = { >> +#ifdef CONFIG_CORESIGHT_TPDM_INTEGRATION_TEST >> + &dev_attr_integration_test.attr, >> +#endif /* CORESIGHT_TPDM_INTEGRATION_TEST */ >> + NULL, >> +}; >> + >> +static struct attribute_group tpdm_attr_grp = { >> + .attrs = tpdm_attrs, >> +}; >> + >> +static const struct attribute_group *tpdm_attr_grps[] = { >> + &tpdm_attr_grp, >> + NULL, >> +}; > ATTRIBUTE_GROUPS()? > > thanks, > > greg k-h Thanks Jinlong Mao

3 years, 7 months

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