CoreSight

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[PATCH v6 00/14] perf: test: Add trace data quality tests for CoreSight

by carsten.haitzler＠foss.arm.com

From: "Carsten Haitzler (Rasterman)" <raster(a)rasterman.com> This is a prelude to adding more tests to shell tests and in order to support putting those tests into subdirectories, I need to change the test code that scans/finds and runs them. To support subdirs I have to recurse so it's time to refactor the code to allow this and centralize the shell script finding into one location and only one single scan that builds a list of all the found tests in memory instead of it being duplicated in 3 places. This code also optimizes things like knowing the max width of desciption strings (as we can do that while we scan instead of a whole new pass of opening files). It also more cleanly filters scripts to see only *.sh files thus skipping random other files in directories like *~ backup files, other random junk/data files that may appear and the scripts must be executable to make the cut (this ensures the script lib dir is not seen as scripts to run). This avoids perf test running previous older versions of test scripts that are editor backup files as well as skipping perf.data files that may appear and so on. Signed-off-by: Carsten Haitzler <carsten.haitzler(a)arm.com> Carsten Haitzler (Rasterman) (14): perf test: Refactor shell tests allowing subdirs perf test: Add CoreSight shell lib shared code for future tests perf test: Add build infra for perf test tools for CoreSight tests perf test: Add asm pureloop test tool perf test: Add asm pureloop test shell script perf test: Add git ignore for perf data generated by the CoreSight tests perf test: Add memcpy thread test tool perf test: Add memcpy thread test shell script perf test: Add thread loop test tool perf test: Add thread loop test shell scripts perf test: Add unroll thread test tool perf test: Add unroll thread test shell script perf test: Add git ignore for tmp and output files of CoreSight tests perf test: Add relevant documentation about CoreSight testing .../trace/coresight/coresight-perf.rst | 158 +++++++++++++ MAINTAINERS | 1 + tools/perf/.gitignore | 6 +- .../perf/Documentation/perf-arm-coresight.txt | 5 + tools/perf/Makefile.config | 2 + tools/perf/Makefile.perf | 17 +- tools/perf/tests/Build | 1 + tools/perf/tests/builtin-test-list.c | 207 ++++++++++++++++++ tools/perf/tests/builtin-test-list.h | 12 + tools/perf/tests/builtin-test.c | 152 ++----------- tools/perf/tests/shell/coresight/Makefile | 30 +++ .../tests/shell/coresight/Makefile.miniconfig | 14 ++ .../tests/shell/coresight/asm_pure_loop.sh | 18 ++ .../shell/coresight/asm_pure_loop/.gitignore | 1 + .../shell/coresight/asm_pure_loop/Makefile | 34 +++ .../coresight/asm_pure_loop/asm_pure_loop.S | 28 +++ .../shell/coresight/memcpy_thread/.gitignore | 1 + .../shell/coresight/memcpy_thread/Makefile | 33 +++ .../coresight/memcpy_thread/memcpy_thread.c | 79 +++++++ .../shell/coresight/memcpy_thread_16k_10.sh | 18 ++ .../shell/coresight/thread_loop/.gitignore | 1 + .../shell/coresight/thread_loop/Makefile | 33 +++ .../shell/coresight/thread_loop/thread_loop.c | 86 ++++++++ .../coresight/thread_loop_check_tid_10.sh | 19 ++ .../coresight/thread_loop_check_tid_2.sh | 19 ++ .../coresight/unroll_loop_thread/.gitignore | 1 + .../coresight/unroll_loop_thread/Makefile | 33 +++ .../unroll_loop_thread/unroll_loop_thread.c | 74 +++++++ .../shell/coresight/unroll_loop_thread_10.sh | 18 ++ tools/perf/tests/shell/lib/coresight.sh | 132 +++++++++++ 30 files changed, 1094 insertions(+), 139 deletions(-) create mode 100644 Documentation/trace/coresight/coresight-perf.rst create mode 100644 tools/perf/Documentation/perf-arm-coresight.txt create mode 100644 tools/perf/tests/builtin-test-list.c create mode 100644 tools/perf/tests/builtin-test-list.h create mode 100644 tools/perf/tests/shell/coresight/Makefile create mode 100644 tools/perf/tests/shell/coresight/Makefile.miniconfig create mode 100755 tools/perf/tests/shell/coresight/asm_pure_loop.sh create mode 100644 tools/perf/tests/shell/coresight/asm_pure_loop/.gitignore create mode 100644 tools/perf/tests/shell/coresight/asm_pure_loop/Makefile create mode 100644 tools/perf/tests/shell/coresight/asm_pure_loop/asm_pure_loop.S create mode 100644 tools/perf/tests/shell/coresight/memcpy_thread/.gitignore create mode 100644 tools/perf/tests/shell/coresight/memcpy_thread/Makefile create mode 100644 tools/perf/tests/shell/coresight/memcpy_thread/memcpy_thread.c create mode 100755 tools/perf/tests/shell/coresight/memcpy_thread_16k_10.sh create mode 100644 tools/perf/tests/shell/coresight/thread_loop/.gitignore create mode 100644 tools/perf/tests/shell/coresight/thread_loop/Makefile create mode 100644 tools/perf/tests/shell/coresight/thread_loop/thread_loop.c create mode 100755 tools/perf/tests/shell/coresight/thread_loop_check_tid_10.sh create mode 100755 tools/perf/tests/shell/coresight/thread_loop_check_tid_2.sh create mode 100644 tools/perf/tests/shell/coresight/unroll_loop_thread/.gitignore create mode 100644 tools/perf/tests/shell/coresight/unroll_loop_thread/Makefile create mode 100644 tools/perf/tests/shell/coresight/unroll_loop_thread/unroll_loop_thread.c create mode 100755 tools/perf/tests/shell/coresight/unroll_loop_thread_10.sh create mode 100644 tools/perf/tests/shell/lib/coresight.sh -- 2.32.0

2 years, 10 months

[PATCH v5 00/14] A patch series improving data quality of perf test for CoreSight

by carsten.haitzler＠foss.arm.com

From: "Carsten Haitzler (Rasterman)" <raster(a)rasterman.com> This is a prelude to adding more tests to shell tests and in order to support putting those tests into subdirectories, I need to change the test code that scans/finds and runs them. To support subdirs I have to recurse so it's time to refactor the code to allow this and centralize the shell script finding into one location and only one single scan that builds a list of all the found tests in memory instead of it being duplicated in 3 places. This code also optimizes things like knowing the max width of desciption strings (as we can do that while we scan instead of a whole new pass of opening files). It also more cleanly filters scripts to see only *.sh files thus skipping random other files in directories like *~ backup files, other random junk/data files that may appear and the scripts must be executable to make the cut (this ensures the script lib dir is not seen as scripts to run). This avoids perf test running previous older versions of test scripts that are editor backup files as well as skipping perf.data files that may appear and so on. Signed-off-by: Carsten Haitzler <carsten.haitzler(a)arm.com> Carsten Haitzler (Rasterman) (14): perf test: Refactor shell tests allowing subdirs perf test: Add CoreSight shell lib shared code for future tests perf test: Add build infra for perf test tools for CoreSight tests perf test: Add asm pureloop test tool perf test: Add asm pureloop test shell script perf test: Add git ignore for perf data generated by the CoreSight tests perf test: Add memcpy thread test tool perf test: Add memcpy thread test shell script perf test: Add thread loop test tool perf test: Add thread loop test shell scripts perf test: Add unroll thread test tool perf test: Add unroll thread test shell script perf test: Add git ignore for tmp and output files of CoreSight tests perf test: Add relevant documentation about CoreSight testing .../trace/coresight/coresight-perf.rst | 160 ++++++++++++++ MAINTAINERS | 1 + tools/perf/.gitignore | 6 +- tools/perf/Documentation/arm-coresight.txt | 5 + tools/perf/Makefile.perf | 18 +- tools/perf/tests/Build | 1 + tools/perf/tests/builtin-test-list.c | 207 ++++++++++++++++++ tools/perf/tests/builtin-test-list.h | 12 + tools/perf/tests/builtin-test.c | 152 ++----------- tools/perf/tests/shell/coresight/Makefile | 30 +++ .../tests/shell/coresight/Makefile.miniconfig | 24 ++ .../tests/shell/coresight/asm_pure_loop.sh | 18 ++ .../shell/coresight/asm_pure_loop/.gitignore | 1 + .../shell/coresight/asm_pure_loop/Makefile | 34 +++ .../coresight/asm_pure_loop/asm_pure_loop.S | 28 +++ .../shell/coresight/memcpy_thread/.gitignore | 1 + .../shell/coresight/memcpy_thread/Makefile | 33 +++ .../coresight/memcpy_thread/memcpy_thread.c | 79 +++++++ .../shell/coresight/memcpy_thread_16k_10.sh | 18 ++ .../shell/coresight/thread_loop/.gitignore | 1 + .../shell/coresight/thread_loop/Makefile | 33 +++ .../shell/coresight/thread_loop/thread_loop.c | 86 ++++++++ .../coresight/thread_loop_check_tid_10.sh | 19 ++ .../coresight/thread_loop_check_tid_2.sh | 19 ++ .../coresight/unroll_loop_thread/.gitignore | 1 + .../coresight/unroll_loop_thread/Makefile | 33 +++ .../unroll_loop_thread/unroll_loop_thread.c | 74 +++++++ .../shell/coresight/unroll_loop_thread_10.sh | 18 ++ tools/perf/tests/shell/lib/coresight.sh | 132 +++++++++++ 29 files changed, 1105 insertions(+), 139 deletions(-) create mode 100644 Documentation/trace/coresight/coresight-perf.rst create mode 100644 tools/perf/Documentation/arm-coresight.txt create mode 100644 tools/perf/tests/builtin-test-list.c create mode 100644 tools/perf/tests/builtin-test-list.h create mode 100644 tools/perf/tests/shell/coresight/Makefile create mode 100644 tools/perf/tests/shell/coresight/Makefile.miniconfig create mode 100755 tools/perf/tests/shell/coresight/asm_pure_loop.sh create mode 100644 tools/perf/tests/shell/coresight/asm_pure_loop/.gitignore create mode 100644 tools/perf/tests/shell/coresight/asm_pure_loop/Makefile create mode 100644 tools/perf/tests/shell/coresight/asm_pure_loop/asm_pure_loop.S create mode 100644 tools/perf/tests/shell/coresight/memcpy_thread/.gitignore create mode 100644 tools/perf/tests/shell/coresight/memcpy_thread/Makefile create mode 100644 tools/perf/tests/shell/coresight/memcpy_thread/memcpy_thread.c create mode 100755 tools/perf/tests/shell/coresight/memcpy_thread_16k_10.sh create mode 100644 tools/perf/tests/shell/coresight/thread_loop/.gitignore create mode 100644 tools/perf/tests/shell/coresight/thread_loop/Makefile create mode 100644 tools/perf/tests/shell/coresight/thread_loop/thread_loop.c create mode 100755 tools/perf/tests/shell/coresight/thread_loop_check_tid_10.sh create mode 100755 tools/perf/tests/shell/coresight/thread_loop_check_tid_2.sh create mode 100644 tools/perf/tests/shell/coresight/unroll_loop_thread/.gitignore create mode 100644 tools/perf/tests/shell/coresight/unroll_loop_thread/Makefile create mode 100644 tools/perf/tests/shell/coresight/unroll_loop_thread/unroll_loop_thread.c create mode 100755 tools/perf/tests/shell/coresight/unroll_loop_thread_10.sh create mode 100644 tools/perf/tests/shell/lib/coresight.sh -- 2.32.0

2 years, 10 months

Re: [PATCH v2 2/2] arm64: dts: qcom: sm8250: Add Coresight support

by Anshuman Khandual

On 9/24/21 15:36, Tao Zhang wrote: > Add the basic coresight components found on Qualcomm SM8250 Soc. The > basic coresight components include ETF, ETMs,STM and the related > funnels. Hello, Seems like this patch never merged mainline, what happened ? This change is required to enable coresight devices on RB5 platform. - Anshuman > > Signed-off-by: Tao Zhang <quic_taozha(a)quicinc.com> > --- > arch/arm64/boot/dts/qcom/qrb5165-rb5.dts | 439 +++++++++++++++++++++++++++++++ > 1 file changed, 439 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts > index 5f41de2..1e1579a 100644 > --- a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts > +++ b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts > @@ -223,6 +223,445 @@ > regulator-max-microvolt = <1800000>; > regulator-always-on; > }; > + > + stm@6002000 { > + compatible = "arm,coresight-stm", "arm,primecell"; > + reg = <0 0x06002000 0 0x1000>, > + <0 0x16280000 0 0x180000>; > + reg-names = "stm-base", "stm-stimulus-base"; > + > + clocks = <&aoss_qmp>; > + clock-names = "apb_pclk"; > + > + out-ports { > + port { > + stm_out: endpoint { > + remote-endpoint = > + <&funnel0_in7>; > + }; > + }; > + }; > + }; > + > + funnel@6041000 { > + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; > + reg = <0 0x06041000 0 0x1000>; > + > + clocks = <&aoss_qmp>; > + clock-names = "apb_pclk"; > + > + out-ports { > + port { > + funnel0_out: endpoint { > + remote-endpoint = > + <&merge_funnel_in0>; > + }; > + }; > + }; > + > + in-ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@7 { > + reg = <7>; > + funnel0_in7: endpoint { > + remote-endpoint = <&stm_out>; > + }; > + }; > + }; > + }; > + > + funnel@6042000 { > + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; > + reg = <0 0x06042000 0 0x1000>; > + > + clocks = <&aoss_qmp>; > + clock-names = "apb_pclk"; > + > + out-ports { > + port { > + funnel2_out: endpoint { > + remote-endpoint = > + <&merge_funnel_in2>; > + }; > + }; > + }; > + > + in-ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@4 { > + reg = <4>; > + funnel2_in5: endpoint { > + remote-endpoint = > + <&apss_merge_funnel_out>; > + }; > + }; > + }; > + }; > + > + funnel@6b04000 { > + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; > + arm,primecell-periphid = <0x000bb908>; > + > + reg = <0 0x6b04000 0 0x1000>; > + reg-names = "funnel-base"; > + > + clocks = <&aoss_qmp>; > + clock-names = "apb_pclk"; > + > + out-ports { > + port { > + merge_funnel_out: endpoint { > + remote-endpoint = > + <&etf_in>; > + }; > + }; > + }; > + > + in-ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@7 { > + reg = <7>; > + swao_funnel_in7: endpoint { > + slave-mode; > + remote-endpoint= > + <&merg_funnel_out>; > + }; > + }; > + }; > + > + }; > + > + funnel@6045000 { > + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; > + reg = <0 0x06045000 0 0x1000>; > + > + clocks = <&aoss_qmp>; > + clock-names = "apb_pclk"; > + > + out-ports { > + port { > + merg_funnel_out: endpoint { > + remote-endpoint = <&swao_funnel_in7>; > + }; > + }; > + }; > + > + in-ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@0 { > + reg = <0>; > + merge_funnel_in0: endpoint { > + remote-endpoint = > + <&funnel0_out>; > + }; > + }; > + > + port@1 { > + reg = <1>; > + merge_funnel_in2: endpoint { > + remote-endpoint = > + <&funnel2_out>; > + }; > + }; > + }; > + }; > + > + etf@6b05000 { > + compatible = "arm,coresight-tmc", "arm,primecell"; > + reg = <0 0x06b05000 0 0x1000>; > + > + clocks = <&aoss_qmp>; > + clock-names = "apb_pclk"; > + > + in-ports { > + port { > + etf_in: endpoint { > + remote-endpoint = > + <&merge_funnel_out>; > + }; > + }; > + }; > + }; > + > + etm@7040000 { > + compatible = "arm,coresight-etm4x", "arm,primecell"; > + reg = <0 0x07040000 0 0x1000>; > + > + cpu = <&CPU0>; > + > + clocks = <&aoss_qmp>; > + clock-names = "apb_pclk"; > + arm,coresight-loses-context-with-cpu; > + > + out-ports { > + port { > + etm0_out: endpoint { > + remote-endpoint = > + <&apss_funnel_in0>; > + }; > + }; > + }; > + }; > + > + etm@7140000 { > + compatible = "arm,coresight-etm4x", "arm,primecell"; > + reg = <0 0x07140000 0 0x1000>; > + > + cpu = <&CPU1>; > + > + clocks = <&aoss_qmp>; > + clock-names = "apb_pclk"; > + arm,coresight-loses-context-with-cpu; > + > + out-ports { > + port { > + etm1_out: endpoint { > + remote-endpoint = > + <&apss_funnel_in1>; > + }; > + }; > + }; > + }; > + > + etm@7240000 { > + compatible = "arm,coresight-etm4x", "arm,primecell"; > + reg = <0 0x07240000 0 0x1000>; > + > + cpu = <&CPU2>; > + > + clocks = <&aoss_qmp>; > + clock-names = "apb_pclk"; > + arm,coresight-loses-context-with-cpu; > + > + out-ports { > + port { > + etm2_out: endpoint { > + remote-endpoint = > + <&apss_funnel_in2>; > + }; > + }; > + }; > + }; > + > + etm@7340000 { > + compatible = "arm,coresight-etm4x", "arm,primecell"; > + reg = <0 0x07340000 0 0x1000>; > + > + cpu = <&CPU3>; > + > + clocks = <&aoss_qmp>; > + clock-names = "apb_pclk"; > + arm,coresight-loses-context-with-cpu; > + > + out-ports { > + port { > + etm3_out: endpoint { > + remote-endpoint = > + <&apss_funnel_in3>; > + }; > + }; > + }; > + }; > + > + etm@7440000 { > + compatible = "arm,coresight-etm4x", "arm,primecell"; > + reg = <0 0x07440000 0 0x1000>; > + > + cpu = <&CPU4>; > + > + clocks = <&aoss_qmp>; > + clock-names = "apb_pclk"; > + arm,coresight-loses-context-with-cpu; > + > + out-ports { > + port { > + etm4_out: endpoint { > + remote-endpoint = > + <&apss_funnel_in4>; > + }; > + }; > + }; > + }; > + > + etm@7540000 { > + compatible = "arm,coresight-etm4x", "arm,primecell"; > + reg = <0 0x07540000 0 0x1000>; > + > + cpu = <&CPU5>; > + > + clocks = <&aoss_qmp>; > + clock-names = "apb_pclk"; > + arm,coresight-loses-context-with-cpu; > + > + out-ports { > + port { > + etm5_out: endpoint { > + remote-endpoint = > + <&apss_funnel_in5>; > + }; > + }; > + }; > + }; > + > + etm@7640000 { > + compatible = "arm,coresight-etm4x", "arm,primecell"; > + reg = <0 0x07640000 0 0x1000>; > + > + cpu = <&CPU6>; > + > + clocks = <&aoss_qmp>; > + clock-names = "apb_pclk"; > + arm,coresight-loses-context-with-cpu; > + > + out-ports { > + port { > + etm6_out: endpoint { > + remote-endpoint = > + <&apss_funnel_in6>; > + }; > + }; > + }; > + }; > + > + etm@7740000 { > + compatible = "arm,coresight-etm4x", "arm,primecell"; > + reg = <0 0x07740000 0 0x1000>; > + > + cpu = <&CPU7>; > + > + clocks = <&aoss_qmp>; > + clock-names = "apb_pclk"; > + arm,coresight-loses-context-with-cpu; > + > + out-ports { > + port { > + etm7_out: endpoint { > + remote-endpoint = > + <&apss_funnel_in7>; > + }; > + }; > + }; > + }; > + > + funnel@7800000 { > + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; > + reg = <0 0x07800000 0 0x1000>; > + > + clocks = <&aoss_qmp>; > + clock-names = "apb_pclk"; > + > + out-ports { > + port { > + apss_funnel_out: endpoint { > + remote-endpoint = > + <&apss_merge_funnel_in>; > + }; > + }; > + }; > + > + in-ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@0 { > + reg = <0>; > + apss_funnel_in0: endpoint { > + remote-endpoint = > + <&etm0_out>; > + }; > + }; > + > + port@1 { > + reg = <1>; > + apss_funnel_in1: endpoint { > + remote-endpoint = > + <&etm1_out>; > + }; > + }; > + > + port@2 { > + reg = <2>; > + apss_funnel_in2: endpoint { > + remote-endpoint = > + <&etm2_out>; > + }; > + }; > + > + port@3 { > + reg = <3>; > + apss_funnel_in3: endpoint { > + remote-endpoint = > + <&etm3_out>; > + }; > + }; > + > + port@4 { > + reg = <4>; > + apss_funnel_in4: endpoint { > + remote-endpoint = > + <&etm4_out>; > + }; > + }; > + > + port@5 { > + reg = <5>; > + apss_funnel_in5: endpoint { > + remote-endpoint = > + <&etm5_out>; > + }; > + }; > + > + port@6 { > + reg = <6>; > + apss_funnel_in6: endpoint { > + remote-endpoint = > + <&etm6_out>; > + }; > + }; > + > + port@7 { > + reg = <7>; > + apss_funnel_in7: endpoint { > + remote-endpoint = > + <&etm7_out>; > + }; > + }; > + }; > + }; > + > + funnel@7810000 { > + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; > + reg = <0 0x07810000 0 0x1000>; > + > + clocks = <&aoss_qmp>; > + clock-names = "apb_pclk"; > + > + out-ports { > + port { > + apss_merge_funnel_out: endpoint { > + remote-endpoint = > + <&funnel2_in5>; > + }; > + }; > + }; > + > + in-ports { > + port { > + apss_merge_funnel_in: endpoint { > + remote-endpoint = > + <&apss_funnel_out>; > + }; > + }; > + }; > + }; > }; > > &adsp {

2 years, 10 months

Re: [PATCH v4 7/7] configfs: Fix LOCKDEP nesting issues with fragment semaphores

by Mike Leach

Hi Christoph. [adding in Suzuki and Mathieu who maintain the coresight subsystem & lists] You are correct - in this patchset we are adding the use of a binary attribute to load and unload Coresight configurations and features - which action has a side effect of adding and removing entries in particular sub-directories in our configfs sub-system. Our use case for configfs is somewhat more complex than the other existing usages - such as ACPI, where the format of the directory structure and attributes is static, and known ahead of time. The CoreSight configurations have variable numbers of attributes appearing in the configfs directories - so the attribute arrays are built dynamically at load time. The load process and also result in elements appearing in both the cs-syscfg/configurations and the cs-syscfg/features sub directories. This dynamic nature and split elements means that the traditional mkdir/rmdir configfs paradigm cannot be made to work. We currently have two methods upstreamed for loading configurations, 1 is a configuration directly built into the coresight core code, and the other is to allow configurations to be loaded as kernel loadable modules. However these 2 are dependent on compile time operations, and have kernel dependencies. Hence we have introduced the direct load via configfs binary attribute - which is more portable, flexible and convenient for the end user. I appreciate that this may not be a usage you anticipated for configfs, but it does serve our purposes very well, and as far a I can tell from examination of configfs code and considerable testing, works fine and does not have any operational issues, other than the lockdep warnings on unload, which are caused be the fragment locks (lockdep being confused by holding the fragment for the initial cs-syscfg root system, and the one for the sub-directory we want to unload). I am open to suggestions for a different way of doing this within the established directory structure we need to maintain. Thanks and Regards Mike On Fri, 29 Jul 2022 at 14:24, Christoph Hellwig <hch(a)lst.de> wrote: > > On Fri, Jul 29, 2022 at 07:41:00AM +0100, Mike Leach wrote: > > Sure - see below > > > > Happens during the unload process of the coresight configuration. > > Hmm. It seems like youre bin_attr ->write handler (which gets called > from configfs_release_bin_file) tries to unregister a group. That's > not really how the configfs API is supposed to be used. -- Mike Leach Principal Engineer, ARM Ltd. Manchester Design Centre. UK

2 years, 11 months

Longer traces with limited buffer

by finn.burmester＠student.uni-luebeck.de

Hi all, I have a system that only has an ETF as a trace sink, so I only have 8 kB of memory available for my trace, which limits me to quite small programs. What would be the go-to solution for longer trace-runs, when I want to do on-device-trace-capturing? Is it possible at all with my setup? It is important that I don't loose any trace, I need a trace of the whole execution. For tracing I use CSAL. Best regards, Finn

2 years, 11 months

Re: [PATCH] coresight: etm4x: Fix crash observed on Qcom ETM parts with 'Low power override'

by Suzuki K Poulose

Hi Bhupesh, On 03/08/2022 20:12, Bhupesh Sharma wrote: > Some Qualcomm ETM implementations require skipping powering up > the trace unit, as the ETMs are in the same power domain as > their CPU cores. > > Via commit 5214b563588e ("coresight: etm4x: Add support for > sysreg only devices"), the setting of 'skip_power_up' flag was > moved after the 'etm4_init_arch_data' function is called, whereas > the flag value is itself used inside the function. This causes > a crash when ETM mode 'Low-power state behavior override' is set > on some Qualcomm parts. > > Fix the same. > Thanks for the patch. The patch is correct. But please see my comment below. > Fixes: 5214b563588e ("coresight: etm4x: Add support for sysreg only devices") > Cc: Mike Leach <mike.leach(a)linaro.org> > Cc: Suzuki K Poulose <suzuki.poulose(a)arm.com> > Cc: Mathieu Poirier <mathieu.poirier(a)linaro.org> > Cc: Greg Kroah-Hartman <gregkh(a)linuxfoundation.org> > Signed-off-by: Bhupesh Sharma <bhupesh.sharma(a)linaro.org> > --- > drivers/hwtracing/coresight/coresight-etm4x-core.c | 13 +++++++++++-- > 1 file changed, 11 insertions(+), 2 deletions(-) > > diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c > index d39660a3e50c..cf6254b87fd5 100644 > --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c > +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c > @@ -1943,6 +1943,16 @@ static int etm4_probe(struct device *dev, void __iomem *base, u32 etm_pid) > init_arg.csa = &desc.access; > init_arg.pid = etm_pid; > > + /* > + * Some Qualcomm implementations require skipping powering up the trace unit, > + * as the ETMs are in the same power domain as their CPU cores. > + * > + * Since the 'skip_power_up' flag is used inside 'etm4_init_arch_data' function, > + * initialize it before the function is called. > + */ > + if (fwnode_property_present(dev_fwnode(dev), "qcom,skip-power-up")) > + drvdata->skip_power_up = true; > + > if (smp_call_function_single(drvdata->cpu, > etm4_init_arch_data, &init_arg, 1)) > dev_err(dev, "ETM arch init failed\n"); > @@ -1951,8 +1961,7 @@ static int etm4_probe(struct device *dev, void __iomem *base, u32 etm_pid) > return -EINVAL; > > /* TRCPDCR is not accessible with system instructions. */ > - if (!desc.access.io_mem || > - fwnode_property_present(dev_fwnode(dev), "qcom,skip-power-up")) > + if (!desc.access.io_mem) > drvdata->skip_power_up = true; > Please could you move this setting into "etm4_init_sysreg_access()" ? It looks a bit odd to split the check in the same function. Moving this to the sysreg_access() makes it explicit. Suzuki > major = ETM_ARCH_MAJOR_VERSION(drvdata->arch);

2 years, 11 months

A patch series improving data quality of perf test for CoreSight

by carsten.haitzler＠foss.arm.com

This is a prelude to adding more tests to shell tests and in order to support putting those tests into subdirectories, I need to change the test code that scans/finds and runs them. To support subdirs I have to recurse so it's time to refactor the code to allow this and centralize the shell script finding into one location and only one single scan that builds a list of all the found tests in memory instead of it being duplicated in 3 places. This code also optimizes things like knowing the max width of desciption strings (as we can do that while we scan instead of a whole new pass of opening files). It also more cleanly filters scripts to see only *.sh files thus skipping random other files in directories like *~ backup files, other random junk/data files that may appear and the scripts must be executable to make the cut (this ensures the script lib dir is not seen as scripts to run). This avoids perf test running previous older versions of test scripts that are editor backup files as well as skipping perf.data files that may appear and so on. Signed-off-by: Carsten Haitzler <carsten.haitzler(a)arm.com>

2 years, 11 months

Re: [PATCH] coresight: docs: Fix a broken reference

by James Clark

On 31/07/2022 08:06, Christophe JAILLET wrote: > Since the commit in Fixes: tag, "coresight-cpu-debug.txt" has been turned > into "arm,coresight-cpu-debug.yaml". > > Update the doc accordingly to avoid a 'make htmldocs' warning > > Fixes: 66d052047ca8 ("dt-bindings: arm: Convert CoreSight CPU debug to DT schema") > Signed-off-by: Christophe JAILLET <christophe.jaillet(a)wanadoo.fr> > --- > Documentation/trace/coresight/coresight-cpu-debug.rst | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/Documentation/trace/coresight/coresight-cpu-debug.rst b/Documentation/trace/coresight/coresight-cpu-debug.rst > index 993dd294b81b..836b35532667 100644 > --- a/Documentation/trace/coresight/coresight-cpu-debug.rst > +++ b/Documentation/trace/coresight/coresight-cpu-debug.rst > @@ -117,7 +117,8 @@ divide into below cases: > Device Tree Bindings > -------------------- > > -See Documentation/devicetree/bindings/arm/coresight-cpu-debug.txt for details. > +See Documentation/devicetree/bindings/arm/arm,coresight-cpu-debug.yaml for > +details. LGTM, thanks Reviewed-by: James Clark <james.clark(a)arm.com> > > > How to use the module

2 years, 11 months

Re: [PATCH v12 0/9] Coresight: Add support for TPDM and TPDA

by Suzuki K Poulose

On 02/08/2022 19:09, Trilok Soni wrote: > Hi Suzuki, > > On 8/2/2022 10:43 AM, Suzuki K Poulose wrote: >> Hi Trilok, >> >> On 02/08/2022 18:33, Trilok Soni wrote: >>> >>> >>> On 8/2/2022 7:43 AM, Jinlong Mao wrote: >>>> Hi Reviewers, >>>> >>>> Please help to review V12 series of TPDM/TPDA patches. >>>> >>>> Thanks >>>> >>> >>> Suzuki and Mathieu, we are almost there it seems in getting the >>> acceptance of these patches, so I hope you find the time to review >>> these patches. I guess it is almost a year now for these patches and >>> had a good amount of reviews and revisions :) >> >> This series has been reviewed for the previous versions (which is why >> we have it in v12) and this one depends on a series worked on by Mike >> Leach. We cannot push this without the dynamic Trace ID allocation >> scheme, which is clearly mentioned in the cover letter for this >> series. >> >> As such this series is in a good shape, assuming all the comments >> in the previous version has been addressed. So, we would rather >> get Mike's work priority and pull that in, so that we can eventually >> get this upstream. >> >> > > I believe we have addressed all the comments in v12. Are you ok, if we > post additional features series (around ~2k to ~3k SLOC)? I just want to > make sure we are not creating flood of patches w/ features. You are free to post the patches, as long as you clearly mention the dependencies in the cover letter. Please be mindful about the merge window. Suzuki

2 years, 11 months

Re: [PATCH v12 0/9] Coresight: Add support for TPDM and TPDA

by Suzuki K Poulose

Hi Trilok, On 02/08/2022 18:33, Trilok Soni wrote: > > > On 8/2/2022 7:43 AM, Jinlong Mao wrote: >> Hi Reviewers, >> >> Please help to review V12 series of TPDM/TPDA patches. >> >> Thanks >> > > Suzuki and Mathieu, we are almost there it seems in getting the > acceptance of these patches, so I hope you find the time to review these > patches. I guess it is almost a year now for these patches and had a > good amount of reviews and revisions :) This series has been reviewed for the previous versions (which is why we have it in v12) and this one depends on a series worked on by Mike Leach. We cannot push this without the dynamic Trace ID allocation scheme, which is clearly mentioned in the cover letter for this series. As such this series is in a good shape, assuming all the comments in the previous version has been addressed. So, we would rather get Mike's work priority and pull that in, so that we can eventually get this upstream. Kind regards Suzuki > > ---Trilok Soni

2 years, 11 months

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