CoreSight

coresight@lists.linaro.org

6 participants
2351 discussions

[PATCH v3 0/4] coresight: Add config flag to enable branch broadcast

by James Clark

Apologies for the delay. Changes since v2: * Pick up some of Mike's review tags * Add a comment explaining rationale for not opening the event when BB isn't supported * Extend docs to say that Perf doesn't support decode when binaries are modified * Drop Perf side patches that were already merged Thanks James James Clark (4): coresight: Add config flag to enable branch broadcast Documentation: coresight: Turn numbered subsections into real subsections Documentation: coresight: Link config options to existing documentation Documentation: coresight: Expand branch broadcast documentation .../coresight/coresight-etm4x-reference.rst | 17 +++++- Documentation/trace/coresight/coresight.rst | 56 +++++++++++++++++-- .../hwtracing/coresight/coresight-etm-perf.c | 2 + .../coresight/coresight-etm4x-core.c | 14 +++++ include/linux/coresight-pmu.h | 2 + 5 files changed, 85 insertions(+), 6 deletions(-) -- 2.28.0

2 years, 11 months

Re: arm coresight driver

by Mathieu Poirier

Hi Chenkai, I am taking the liberty of CC'ing the coresight mailing list so that people with more experience with the HW implementation can chime in. On Tue, 24 May 2022 at 05:07, 陈凯 <chenkai.system(a)bytedance.com> wrote: > > Dear Poirier, > I‘m recently read the Linux driver of coresight, I have a question for you about the coresight driver ; That is a lot of reading. > I have a SOC(without arm core) ，in which we integrate the ARM CoreSight; Interesting. > Is the CoreSight driver still compatible for the soc without ETM，beacuse SOC donot include arm core； > and look forwarding to your replay. > The coresight framework does not specifically need an ETM device to work and will transport traces generated by any kind of source that comply with the specification. But you will need to supply your own decoder in the perf tools if you want to take advantage of the perf infrastructure. > > Best regards， > ChenKai

2 years, 11 months

Re: [PATCH v7 08/10] dt-bindings: arm: Adds CoreSight TPDA hardware definitions

by Jinlong Mao

Thanks Rob and Suzuki for the review. I will fix the warning and update in next version. On 5/23/2022 10:24 PM, Rob Herring wrote: > On Mon, May 23, 2022 at 4:44 AM Suzuki K Poulose <suzuki.poulose(a)arm.com> wrote: >> Cc: Rob Herring >> > Will or will not have any effect... > > Please use get_maintainers.pl and send your patches to the right > lists/maintainers. DT patches only get reviewed if sent to DT list. So > please resend to the DT list. But before you do, I can tell this > binding hasn't been tested so fix all the warnings first. > > Rob > >> >> On 09/05/2022 14:39, Mao Jinlong wrote: >>> Adds new coresight-tpda.yaml file describing the bindings required >>> to define tpda in the device trees. >>> >>> Reviewed-by: Mike Leach <mike.leach(a)linaro.org> >>> Signed-off-by: Tao Zhang <quic_taozha(a)quicinc.com> >>> Signed-off-by: Mao Jinlong <quic_jinlmao(a)quicinc.com> >>> --- >>> .../bindings/arm/coresight-tpda.yaml | 119 ++++++++++++++++++ >>> MAINTAINERS | 1 + >>> 2 files changed, 120 insertions(+) >>> create mode 100644 Documentation/devicetree/bindings/arm/coresight-tpda.yaml >>> >>> diff --git a/Documentation/devicetree/bindings/arm/coresight-tpda.yaml b/Documentation/devicetree/bindings/arm/coresight-tpda.yaml >>> new file mode 100644 >>> index 000000000000..4948ac13e7f8 >>> --- /dev/null >>> +++ b/Documentation/devicetree/bindings/arm/coresight-tpda.yaml >>> @@ -0,0 +1,119 @@ >>> +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause >>> +# Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. >>> +%YAML 1.2 >>> +--- >>> +$id: http://devicetree.org/schemas/arm/coresight-tpda.yaml# >>> +$schema: http://devicetree.org/meta-schemas/core.yaml# >>> + >>> +title: Trace, Profiling and Diagnostics Aggregator - TPDA >>> + >>> +description: | >>> + TPDAs are responsible for packetization and timestamping of data sets >>> + utilizing the MIPI STPv2 packet protocol. Pulling data sets from one or >>> + more attached TPDM and pushing the resultant (packetized) data out a >>> + master ATB interface. Performing an arbitrated ATB interleaving (funneling) >>> + task for free-flowing data from TPDM (i.e. CMB and DSB data set flows). >>> + >>> +maintainers: >>> + - Mao Jinlong <quic_jinlmao(a)quicinc.com> >>> + - Tao Zhang <quic_taozha(a)quicinc.com> >>> + >>> +properties: >>> + $nodename: >>> + pattern: "^tpda(@[0-9a-f]+)$" >>> + compatible: >>> + items: >>> + - const: qcom,coresight-tpda >>> + - const: arm,primecell >>> + >>> + reg: >>> + maxItems: 1 >>> + >>> + clocks: >>> + maxItems: 1 >>> + >>> + clock-names: >>> + items: >>> + - const: apb_pclk >>> + >>> + in-ports: >>> + type: object >>> + description: | >>> + Input connections from TPDM to TPDA >>> + $ref: /schemas/graph.yaml#/properties/ports >>> + >> --->8--- >>> + properties: >>> + '#address-cells': >>> + const: 1 >>> + >>> + '#size-cells': >>> + const: 0 >>> + >>> + patternProperties: >>> + "^port@[0-9a-f]+$": >>> + type: object >>> + required: >>> + - reg >>> + >>> + required: >>> + - '#size-cells' >>> + - '#address-cells' >> ---8<--- >> >> I believe the above snippet is not needed and is covered by the generic >> ports. >> >> >>> + >>> + out-ports: >>> + type: object >>> + description: | >>> + Output connections from the TPDA to legacy CoreSight trace bus. >>> + $ref: /schemas/graph.yaml#/properties/ports >>> + >>> + properties: >>> + port: >>> + description: >>> + Output connection from the TPDA to legacy CoreSight Trace bus. >>> + $ref: /schemas/graph.yaml#/properties/port >>> + >>> +required: >>> + - compatible >>> + - reg >>> + - clocks >>> + - clock-names >>> + - in-ports >>> + - out-ports >>> + >>> +additionalProperties: false >>> + >>> +examples: >>> + # minimum tpda definition. >>> + - | >>> + tpda@6004000 { >>> + compatible = "qcom,coresight-tpda", "arm,primecell"; >>> + reg = <0x6004000 0x1000>; >>> + >>> + qcom,tpda-atid = <65>; >>> + >>> + clocks = <&aoss_qmp>; >>> + clock-names = "apb_pclk"; >>> + >>> + in-ports { >>> + #address-cells = <1>; >>> + #size-cells = <0>; >>> + >>> + port@0 { >>> + reg = <0>; >>> + tpda_qdss_0_in_tpdm_dcc: endpoint { >>> + remote-endpoint = >>> + <&tpdm_dcc_out_tpda_qdss_0>; >>> + }; >>> + }; >>> + }; >>> + >>> + out-ports { >>> + port { >>> + tpda_qdss_out_funnel_in0: endpoint { >>> + remote-endpoint = >>> + <&funnel_in0_in_tpda_qdss>; >>> + }; >>> + }; >>> + }; >>> + }; >>> + >>> +... >>> diff --git a/MAINTAINERS b/MAINTAINERS >>> index 28d32b3f3f5c..5d2d8c0ee340 100644 >>> --- a/MAINTAINERS >>> +++ b/MAINTAINERS >>> @@ -1978,6 +1978,7 @@ T: git git://git.kernel.org/pub/scm/linux/kernel/git/coresight/linux.git >>> F: Documentation/ABI/testing/sysfs-bus-coresight-devices-* >>> F: Documentation/devicetree/bindings/arm/coresight-cpu-debug.txt >>> F: Documentation/devicetree/bindings/arm/coresight-cti.yaml >>> +F: Documentation/devicetree/bindings/arm/coresight-tpda.yaml >>> F: Documentation/devicetree/bindings/arm/coresight-tpdm.yaml >>> F: Documentation/devicetree/bindings/arm/coresight.txt >>> F: Documentation/devicetree/bindings/arm/ete.yaml >> Otherwise looks good to me. >> >> Suzuki

2 years, 11 months

Re: [PATCH 1/2] dt-bindings: arm: Convert CoreSight bindings to DT schema

by Suzuki K Poulose

Hi Rob, Thanks a lot for converting these to yaml. Some minor comments below. In general, the "clocks" and "clock-names" are optional (e.g, for etm4 with system register access). On 20/05/2022 22:44, Rob Herring wrote: > Each CoreSight component has slightly different requirements and > nothing applies to every component, so each CoreSight component has its > own schema document. > > Signed-off-by: Rob Herring <robh(a)kernel.org> > --- > .../bindings/arm/arm,coresight-catu.yaml | 101 +++++ > .../arm/arm,coresight-dynamic-funnel.yaml | 126 ++++++ > .../bindings/arm/arm,coresight-etb10.yaml | 92 ++++ > .../bindings/arm/arm,coresight-etm.yaml | 156 +++++++ > .../arm/arm,coresight-static-replicator.yaml | 90 ++++ > .../bindings/arm/arm,coresight-stm.yaml | 101 +++++ > .../bindings/arm/arm,coresight-tmc.yaml | 132 ++++++ > .../bindings/arm/arm,coresight-tpiu.yaml | 91 ++++ > .../devicetree/bindings/arm/coresight.txt | 402 ------------------ > 9 files changed, 889 insertions(+), 402 deletions(-) > create mode 100644 Documentation/devicetree/bindings/arm/arm,coresight-catu.yaml > create mode 100644 Documentation/devicetree/bindings/arm/arm,coresight-dynamic-funnel.yaml > create mode 100644 Documentation/devicetree/bindings/arm/arm,coresight-etb10.yaml > create mode 100644 Documentation/devicetree/bindings/arm/arm,coresight-etm.yaml > create mode 100644 Documentation/devicetree/bindings/arm/arm,coresight-static-replicator.yaml > create mode 100644 Documentation/devicetree/bindings/arm/arm,coresight-stm.yaml > create mode 100644 Documentation/devicetree/bindings/arm/arm,coresight-tmc.yaml > create mode 100644 Documentation/devicetree/bindings/arm/arm,coresight-tpiu.yaml > delete mode 100644 Documentation/devicetree/bindings/arm/coresight.txt ... > diff --git a/Documentation/devicetree/bindings/arm/arm,coresight-tmc.yaml b/Documentation/devicetree/bindings/arm/arm,coresight-tmc.yaml > new file mode 100644 > index 000000000000..ee1ce47225be > --- /dev/null > +++ b/Documentation/devicetree/bindings/arm/arm,coresight-tmc.yaml > @@ -0,0 +1,132 @@ > +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/arm/arm,coresight-tmc.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Arm CoreSight Trace Memory Controller > + ... > + out-ports: > + $ref: /schemas/graph.yaml#/properties/ports > + additionalProperties: false > + > + properties: > + port: > + description: AXI Master output connection. Used for ETR and ETF > + configurations. nit: This is only for ETRs. Never for ETFs. Suzuki

2 years, 11 months

[PATCH 00/10] coresight: Add new API to allocate trace source ID values

by Mike Leach

The current method for allocating trace source ID values to sources is to use a fixed algorithm for CPU based sources of (cpu_num * 2 + 0x10). The STM is allocated ID 0x1. This fixed algorithm is used in both the CoreSight driver code, and by perf when writing the trace metadata in the AUXTRACE_INFO record. The method needs replacing as currently:- 1. It is inefficient in using available IDs. 2. Does not scale to larger systems with many cores and the algorithm has no limits so will generate invalid trace IDs for cpu number > 44. Additionally requirements to allocate additional system IDs on some systems have been seen. This patch set introduces an API that allows the allocation of trace IDs in a dynamic manner. Architecturally reserved IDs are never allocated, and the system is limited to allocating only valid IDs. Each of the current trace sources ETM3.x, ETM4.x and STM is updated to use the new API. perf handling is changed so that the ID associated with the CPU is read from sysfs. The ID allocator is notified when perf events start and stop so CPU based IDs are kept constant throughout any perf session. For the ETMx.x devices IDs are allocated on certain events a) When using sysfs, an ID will be allocated on hardware enable, and freed when the sysfs reset is written. b) When using perf, ID is allocated on hardware enable, and freed on hardware disable. For both cases the ID is allocated when sysfs is read to get the current trace ID. This ensures that consistent decode metadata can be extracted from the system where this read occurs before device enable. Note: This patchset breaks backward compatibility for perf record. Because the method for generating the AUXTRACE_INFO meta data has changed, using an older perf record will result in metadata that does not match the trace IDs used in the recorded trace data. This mismatch will cause subsequent decode to fail. Older versions of perf will still be able to decode data generated by the updated system. Applies to coresight/next [b54f53bc11a5] Tested on DB410c Mike Leach (10): coresight: trace-id: Add API to dynamically assign trace ID values coresight: trace-id: Set up source trace ID map for system coresight: stm: Update STM driver to use Trace ID api coresight: etm4x: Use trace ID API to dynamically allocate trace ID coresight: etm3x: Use trace ID API to allocate IDs coresight: perf: traceid: Add perf notifiers for trace ID perf: cs-etm: Update event to read trace ID from sysfs coresight: Remove legacy Trace ID allocation mechanism coresight: etmX.X: stm: Remove unused legacy source trace ID ops coresight: trace-id: Add debug & test macros to trace id allocation drivers/hwtracing/coresight/Makefile | 2 +- drivers/hwtracing/coresight/coresight-core.c | 64 ++--- .../hwtracing/coresight/coresight-etm-perf.c | 16 +- drivers/hwtracing/coresight/coresight-etm.h | 3 +- .../coresight/coresight-etm3x-core.c | 93 ++++--- .../coresight/coresight-etm3x-sysfs.c | 28 +- .../coresight/coresight-etm4x-core.c | 63 ++++- .../coresight/coresight-etm4x-sysfs.c | 32 ++- drivers/hwtracing/coresight/coresight-etm4x.h | 3 + drivers/hwtracing/coresight/coresight-priv.h | 1 + drivers/hwtracing/coresight/coresight-stm.c | 49 +--- .../hwtracing/coresight/coresight-trace-id.c | 255 ++++++++++++++++++ .../hwtracing/coresight/coresight-trace-id.h | 69 +++++ include/linux/coresight-pmu.h | 12 - include/linux/coresight.h | 3 - tools/perf/arch/arm/util/cs-etm.c | 12 +- 16 files changed, 530 insertions(+), 175 deletions(-) create mode 100644 drivers/hwtracing/coresight/coresight-trace-id.c create mode 100644 drivers/hwtracing/coresight/coresight-trace-id.h -- 2.17.1

2 years, 12 months

Enquiry on Using Coresight on Android (SM8450+Android 12+Linux 5.10)

by zengshun.wu＠outlook.com

HI ： I am currently using coresight ETM features on Android to try and improve performance. I compiled perf on aarch64 host and pushed it to android. The version of perf and linux kernel are the same. 1. Information about the device SM8450 + Android 12 Linux localhost 5.10.66-qki-consolidate-g14f56d7c5ad6 #1 SMP PREEMPT Tue May 10 11:18:19 UTC 2022 aarch64 2. I ran into some trouble 1) perf encountered syntax error when executing the command. 2) Unable to decode 3. The whole process of my test execution (1) PS C:\Users\wzs>adb push perf /data/local/tmp (2) PS C:\Users\wzs>adb shell chmod 0777 /data/local/tmp/perf (3) PS C:\Users\wzs>adb shell #ls /sys/bus/event_source/devices/cs_etm/sinks/ coresight-eud coresight-tmc-etf coresight-tmc-etr coresight-tmc-etr1 (4) #cd /data/local/tmp/perf #HOME=/data/local/tmp #./perf --buildid-dir /data/local/tmp/.debug record -e cs_etm/@coresight-tmc-etr/u --filter 'filter 0x15f0/0x40(a)/system/lib64/libcstest.so' --per-thread ./main event syntax error: 'cs_etm/@coresight-tmc-etr/u' \___ parser error Run 'perf list' for a list of valid events Usage: perf record [<options>] [<command>] or: perf record [<options>] -- <command> [<options>] -e, --event <event> event selector. use 'perf list' to list available events There is a syntax error here, I think it is because the perf parser thinks that the symbol "-" in the string "coresight-tmc-etr" is illegal. But I don't know how to fix it, so I did the following. Use tmc_etr, but replace it with coresight-tmc-etr in the code. --- a/tools/perf/util/parse-events2.c +++ b/tools/perf/util/parse-events.c @@ -2916,6 +2916,8 @@ int parse_events__is_hardcoded_term(struct parse_events_term *term) return term->type_term != PARSE_EVENTS__TERM_TYPE_USER; } +char *cs_str;//"coresight-tmc-etr" + static int new_term(struct parse_events_term **_term, struct parse_events_term *temp, char *str, u64 num) @@ -2925,6 +2927,12 @@ static int new_term(struct parse_events_term **_term, term = malloc(sizeof(*term)); if (!term) return -ENOMEM; + if (str && !strcmp(str, "tmc_etr")) { + cs_str = (char*)malloc(30); + strcpy(cs_str, "coresight-tmc-etr"); + str = cs_str; + } *term = *temp; INIT_LIST_HEAD(&term->list); term->weak = false; Will continue. (5) #./perf --buildid-dir /data/local/tmp/.debug record -e cs_etm/@tmc_etr/u --per-thread ./main val: 20 [ perf record: Woken up 1 times to write data ] BFD: /apex/com.android.runtime/bin/linker64: unknown type [0x13] section `.relr.dyn' BFD: /apex/com.android.runtime/lib64/bionic/libm.so: unknown type [0x13] section `.relr.dyn' BFD: /system/lib64/libutils.so: unknown type [0x13] section `.relr.dyn' BFD: /system/lib64/libnetd_client.so: unknown type [0x13] section `.relr.dyn' BFD: /system/lib64/libcgrouprc.so: unknown type [0x13] section `.relr.dyn' BFD: /system/lib64/libvndksupport.so: unknown type [0x13] section `.relr.dyn' BFD: /system/lib64/liblog.so: unknown type [0x13] section `.relr.dyn' BFD: /system/lib64/libc++.so: unknown type [0x13] section `.relr.dyn' [ perf record: Captured and wrote 1.316 MB perf.data ] (6) # ls -al total 1861311 drwxrwx--x 3 shell shell 8192 2022-01-05 05:37 . drwxr-x--x 5 root root 3452 2022-01-04 05:56 .. drwxr-xr-x 418 root root 24576 2022-01-05 04:31 .debug -rw-rw-rw- 1 root root 1859414850 2022-01-05 04:36 cs_example.tgz -rwxrwxrwx 1 root root 42944200 2022-05-14 16:15 perf -rw------- 1 root root 1425940 2022-01-05 05:37 perf.data (7) #./perf report --stdio # To display the perf.data header info, please use --header/--header-only options. # Error: The perf.data data has no samples! An exception has been shown here, no data was sampled. (8) #tar czf cs_example.tgz perf.data ~/.debug It will then be decoded on my host via OpenCSD. (9) wzs@ubuntu:~/perf/windows_path/test-cs/cs-decode$ cat disasm.sh EXEC_PATH=/home/wzs/perf/sm8450_kernel_src/tools/perf/ SCRIPT_PATH=/home/wzs/perf/sm8450_kernel_src/tools/perf/scripts/python/ XTOOLS_PATH=/home/wzs/android-ndk/toolchains/llvm/prebuilt/linux-x86_64/bin/llvm-objdump ./perf --exec-path=${EXEC_PATH} script --script=python:${SCRIPT_PATH}/arm-cs-trace-disasm.py -- -d $XTOOLS_PATH -k ./vmlinux -v (10) wzs@ubuntu:~/perf/windows_path/test-cs/cs-decode$ ./disasm.sh ARM CoreSight Trace Data Assembler Dump parse_mmap = { pid: 19130 dso: /data/local/tmp/main start: 0x5f8d029000 end: 0x5f8d02a000} parse_mmap = { pid: 19130 dso: /apex/com.android.runtime/bin/linker64 start: 0x7eaafab000 end: 0x7eab096000} parse_mmap = { pid: 19130 dso: [vdso] start: 0x7eaaf72000 end: 0x7eaaf73000} parse_mmap = { pid: 19130 dso: /system/lib64/libcstest.so start: 0x7ea9c62000 end: 0x7ea9c63000} parse_mmap = { pid: 19130 dso: /apex/com.android.runtime/lib64/bionic/libc.so start: 0x7ea6f70000 end: 0x7ea702d000} parse_mmap = { pid: 19130 dso: /apex/com.android.runtime/lib64/bionic/libc.so start: 0x7ea6f70000 end: 0x7ea702d000} parse_mmap = { pid: 19130 dso: /apex/com.android.runtime/lib64/bionic/libdl.so start: 0x7ea9c0e000 end: 0x7ea9c0f000} parse_mmap = { pid: 19130 dso: /apex/com.android.runtime/lib64/bionic/libdl.so start: 0x7ea9c0e000 end: 0x7ea9c0f000} parse_mmap = { pid: 19130 dso: /system/lib64/libc++.so start: 0x7ea9a8a000 end: 0x7ea9ae7000} parse_mmap = { pid: 19130 dso: /system/lib64/libc++.so start: 0x7ea9a8a000 end: 0x7ea9ae7000} parse_mmap = { pid: 19130 dso: /system/lib64/libcutils.so start: 0x7ea6ef0000 end: 0x7ea6ef8000} parse_mmap = { pid: 19130 dso: /system/lib64/libcutils.so start: 0x7ea6ef0000 end: 0x7ea6ef8000} parse_mmap = { pid: 19130 dso: /system/lib64/libcgrouprc.so start: 0x7ea6e8f000 end: 0x7ea6e90000} parse_mmap = { pid: 19130 dso: /system/lib64/libcgrouprc.so start: 0x7ea6e8f000 end: 0x7ea6e90000} parse_mmap = { pid: 19130 dso: /system/lib64/libprocessgroup.so start: 0x7c96da5000 end: 0x7c96dd8000} parse_mmap = { pid: 19130 dso: /system/lib64/libprocessgroup.so start: 0x7c96da5000 end: 0x7c96dd8000} parse_mmap = { pid: 19130 dso: /apex/com.android.runtime/lib64/bionic/libm.so start: 0x7ea6e52000 end: 0x7ea6e75000} parse_mmap = { pid: 19130 dso: /apex/com.android.runtime/lib64/bionic/libm.so start: 0x7ea6e52000 end: 0x7ea6e75000} parse_mmap = { pid: 19130 dso: /system/lib64/libbase.so start: 0x7c96d53000 end: 0x7c96d7c000} parse_mmap = { pid: 19130 dso: /system/lib64/libbase.so start: 0x7c96d53000 end: 0x7c96d7c000} parse_mmap = { pid: 19130 dso: /system/lib64/liblog.so start: 0x7c96d2a000 end: 0x7c96d35000} parse_mmap = { pid: 19130 dso: /system/lib64/liblog.so start: 0x7c96d2a000 end: 0x7c96d35000} parse_mmap = { pid: 19130 dso: /apex/com.android.runtime/lib64/bionic/libdl_android.so start: 0x7c96ced000 end: 0x7c96cee000} parse_mmap = { pid: 19130 dso: /apex/com.android.runtime/lib64/bionic/libdl_android.so start: 0x7c96ced000 end: 0x7c96cee000} parse_mmap = { pid: 19130 dso: /system/lib64/libutils.so start: 0x7c96caa000 end: 0x7c96cb7000} parse_mmap = { pid: 19130 dso: /system/lib64/libutils.so start: 0x7c96caa000 end: 0x7c96cb7000} parse_mmap = { pid: 19130 dso: /system/lib64/libvndksupport.so start: 0x7c96c4d000 end: 0x7c96c4e000} parse_mmap = { pid: 19130 dso: /system/lib64/libvndksupport.so start: 0x7c96c4d000 end: 0x7c96c4e000} parse_mmap = { pid: 19130 dso: /system/lib64/libnetd_client.so start: 0x7c96c36000 end: 0x7c96c3c000} parse_mmap = { pid: 19130 dso: /system/lib64/libnetd_client.so start: 0x7c96c36000 end: 0x7c96c3c000} End At step 7 it shows no sampled data, and at step 10 there really isn't any output. I think it should be at step 5 that it doesn't work, but perf doesn't actually report an error. Please give me some advice, I would be happy to make this function work successfully on android. This would be helpful for debugging and performance related work. Thanks.

2 years, 12 months

[ISSUE] trace_id of ETM will be invalid when there are more than 48 CPUs on chip

by liuqi (BA)

Hi all, My colleague Junhao He noticed this issue when tracing CPU48 on Kunpeng920 platform, log as follows: [root@localhost ~]# perf record -e cs_etm/@sink_smb1/ -C 48 -o perf.data taskset -c 48 uname -a [root@localhost ~]# perf report -D --stdio -i perf.data > perf_48.log 0x270 [0xc8]: failed to process type: 70 [Invalid argument] Error: failed to process sample [root@localhost ~]# perf -v perf version 5.17.rc4.gdeea22e4af29 [root@localhost ~]# ldd /usr/bin/perf | grep opencsd libopencsd_c_api.so.1 => /root/lib/libopencsd_c_api.so.1 libopencsd.so.1 => /root/lib/libopencsd.so.1 As (CORESIGHT_ETM_PMU_SEED + (cpu * 2)) is used in coresight_get_trace_id() to cacualate trace_id, if there are more than 48 CPUs on chip, we will have some ETM device which trace id is invalid(trace_id = 0 or trace_id > 0x6F). In this situation, we cannot parse trace data using perf tool. Perhaps we should make trace_id in the range of 1 to 0x6F in coresight_get_trace_id()? But there also might be parsing problem if duplicate trace ID is used during collection. Any response will be highly appreciated. Thanks, Qi

2 years, 12 months

Re: [PATCH v5 2/2] perf scripts python: Support Arm CoreSight trace data disassembly

by Leo Yan

On Sun, May 15, 2022 at 02:18:53PM -0700, Ian Rogers wrote: [...] > This looks good to me and will run on python 2. The code would be more > idiomatic in python3 using f-strings. I'd rather the code was > idiomatic from the beginning, but others may disagree and prefer > python 2 compatibility (python 2 is now end of life). f-strings are > python 3.6+ and so have been supported for 5 years. Using f-string is the right thing for me, will update. Thanks for reviewing and suggestion! Leo

3 years

[PATCH v5 0/2] perf script python: Add script for CoreSight disassembly

by Leo Yan

This patch set is to restart the upstreaming for CoreSight disassembly script [1], the python script can be used to dump assembly, source line and symbols so it can be easier for humans inspecting. The first patch changes python script engine to expose more information for DSO and maps, so it's helpful for disassembly with objdump program. The second patch is to introduce the python script for CoreSight trace data disassembly for branch samples. It also can dump source line and symbol info for instruction samples. This patch set has been tested on Arm64 Juno board: # perf script -s scripts/python/arm-cs-trace-disasm.py ... main 6728/6728 [004] 0.000000000 main+0x40 /root/coresight_test/main.c for (i = 0; i < 10000; i++) { main 6728/6728 [004] 0.000000000 main+0x20 /root/coresight_test/main.c val = lib_loop_test(100); main 6728/6728 [004] 0.000000000 lib_loop_test@plt+0xc /root/coresight_test/main main 6728/6728 [004] 0.000000000 lib_loop_test+0xc /root/coresight_test/libcstest.c for (i = 0; i < 5; i++) main 6728/6728 [004] 0.000000000 lib_loop_test+0x30 main 6728/6728 [004] 0.000000000 lib_loop_test+0x30 main 6728/6728 [004] 0.000000000 lib_loop_test+0x30 main 6728/6728 [004] 0.000000000 lib_loop_test+0x30 main 6728/6728 [004] 0.000000000 lib_loop_test+0x30 main 6728/6728 [004] 0.000000000 lib_loop_test+0x3c /root/coresight_test/libcstest.c } # perf script -s scripts/python/arm-cs-trace-disasm.py -- -d llvm-objdump-11 -k ./vmlinux ARM CoreSight Trace Data Assembler Dump ffff800008eb3198 <etm4_enable_hw>: ffff800008eb3310: c0 38 00 35 cbnz w0, 0xffff800008eb3a28 <etm4_enable_hw+0x890> ffff800008eb3314: 9f 3f 03 d5 dsb sy ffff800008eb3318: df 3f 03 d5 isb ffff800008eb331c: f5 5b 42 a9 ldp x21, x22, [sp, #32] ffff800008eb3320: fb 73 45 a9 ldp x27, x28, [sp, #80] ffff800008eb3324: e0 82 40 39 ldrb w0, [x23, #32] ffff800008eb3328: 60 00 00 34 cbz w0, 0xffff800008eb3334 <etm4_enable_hw+0x19c> ffff800008eb332c: e0 03 19 aa mov x0, x25 ffff800008eb3330: 8c fe ff 97 bl 0xffff800008eb2d60 <etm4_cs_lock.isra.0.part.0> main 6055/6055 [004] 0.000000000 etm4_enable_hw+0x198 [kernel.kallsyms] ffff800008eb2d60 <etm4_cs_lock.isra.0.part.0>: ffff800008eb2d60: 1f 20 03 d5 nop ffff800008eb2d64: 1f 20 03 d5 nop ffff800008eb2d68: 3f 23 03 d5 hint #25 ffff800008eb2d6c: 00 00 40 f9 ldr x0, [x0] ffff800008eb2d70: 9f 3f 03 d5 dsb sy ffff800008eb2d74: 00 c0 3e 91 add x0, x0, #4016 ffff800008eb2d78: 1f 00 00 b9 str wzr, [x0] ffff800008eb2d7c: bf 23 03 d5 hint #29 ffff800008eb2d80: c0 03 5f d6 ret main 6055/6055 [004] 0.000000000 etm4_cs_lock.isra.0.part.0+0x20 # perf script -s scripts/python/arm-cs-trace-disasm.py -- -d objdump -k ./vmlinux ARM CoreSight Trace Data Assembler Dump ffff800008eb3310 <etm4_enable_hw+0x178>: ffff800008eb3310: 350038c0 cbnz w0, ffff800008eb3a28 <etm4_enable_hw+0x890> ffff800008eb3314: d5033f9f dsb sy ffff800008eb3318: d5033fdf isb ffff800008eb331c: a9425bf5 ldp x21, x22, [sp, #32] ffff800008eb3320: a94573fb ldp x27, x28, [sp, #80] ffff800008eb3324: 394082e0 ldrb w0, [x23, #32] ffff800008eb3328: 34000060 cbz w0, ffff800008eb3334 <etm4_enable_hw+0x19c> ffff800008eb332c: aa1903e0 mov x0, x25 ffff800008eb3330: 97fffe8c bl ffff800008eb2d60 <etm4_cs_lock.isra.0.part.0> main 6055/6055 [004] 0.000000000 etm4_enable_hw+0x198 [kernel.kallsyms] ffff800008eb2d60 <etm4_cs_lock.isra.0.part.0>: ffff800008eb2d60: d503201f nop ffff800008eb2d64: d503201f nop ffff800008eb2d68: d503233f paciasp ffff800008eb2d6c: f9400000 ldr x0, [x0] ffff800008eb2d70: d5033f9f dsb sy ffff800008eb2d74: 913ec000 add x0, x0, #0xfb0 ffff800008eb2d78: b900001f str wzr, [x0] ffff800008eb2d7c: d50323bf autiasp ffff800008eb2d80: d65f03c0 ret main 6055/6055 [004] 0.000000000 etm4_cs_lock.isra.0.part.0+0x20 [1] https://lists.linaro.org/archives/list/coresight@lists.linaro.org/thread/GI… Changes from v4: * Enhanced python script engine for DSO and map infos; * Rewrote the python script, added support for symbol and source line dumping. Leo Yan (2): perf scripting python: Expose dso and map information perf scripts python: Support Arm CoreSight trace data disassembly .../scripts/python/arm-cs-trace-disasm.py | 275 ++++++++++++++++++ .../scripting-engines/trace-event-python.c | 21 +- 2 files changed, 292 insertions(+), 4 deletions(-) create mode 100755 tools/perf/scripts/python/arm-cs-trace-disasm.py -- 2.25.1

3 years

[GIT PULL] Coresight changes for v5.19

by Mathieu Poirier

The following changes since commit ce522ba9ef7e2d9fb22a39eb3371c0c64e2a433e: Linux 5.18-rc2 (2022-04-10 14:21:36 -1000) are available in the Git repository at: git@gitolite.kernel.org:pub/scm/linux/kernel/git/coresight/linux.git tags/coresight-next-v5.19 for you to fetch changes up to 1adff542d67a2ed1120955cb219bfff8a9c53f59: coresight: cpu-debug: Replace mutex with mutex_trylock on panic notifier (2022-05-09 16:03:24 +0100) ---------------------------------------------------------------- Coresight changes for v5.19 Good day Greg, Please consider those for the the upcoming v5.19 merge window when you have time. This pull request includes: - Work to uniformise access to the ETMv4 registers, making it easier to look for and change register accesses. - A correction to a probing failure when looking for links between devices. - The replacement of a call to mutex_lock() with a mutex_trylock() in the panic notifier of the cpu-debug infrastructure to avoid a possible deadlock. Signed-off-by: Mathieu Poirier <mathieu.poirier(a)linaro.org> ---------------------------------------------------------------- Guilherme G. Piccoli (1): coresight: cpu-debug: Replace mutex with mutex_trylock on panic notifier James Clark (15): coresight: etm4x: Cleanup TRCIDR0 register accesses coresight: etm4x: Cleanup TRCIDR2 register accesses coresight: etm4x: Cleanup TRCIDR3 register accesses coresight: etm4x: Cleanup TRCIDR4 register accesses coresight: etm4x: Cleanup TRCIDR5 register accesses coresight: etm4x: Cleanup TRCCONFIGR register accesses coresight: etm4x: Cleanup TRCEVENTCTL1R register accesses coresight: etm4x: Cleanup TRCSTALLCTLR register accesses coresight: etm4x: Cleanup TRCVICTLR register accesses coresight: etm3x: Cleanup ETMTECR1 register accesses coresight: etm4x: Cleanup TRCACATRn register accesses coresight: etm4x: Cleanup TRCSSCCRn and TRCSSCSRn register accesses coresight: etm4x: Cleanup TRCSSPCICRn register accesses coresight: etm4x: Cleanup TRCBBCTLR register accesses coresight: etm4x: Cleanup TRCRSCTLRn register accesses Mao Jinlong (1): coresight: core: Fix coresight device probe failure issue drivers/hwtracing/coresight/coresight-core.c | 33 ++-- drivers/hwtracing/coresight/coresight-cpu-debug.c | 7 +- drivers/hwtracing/coresight/coresight-etm3x-core.c | 2 +- .../hwtracing/coresight/coresight-etm3x-sysfs.c | 2 +- drivers/hwtracing/coresight/coresight-etm4x-core.c | 136 +++++----------- .../hwtracing/coresight/coresight-etm4x-sysfs.c | 180 +++++++++++---------- drivers/hwtracing/coresight/coresight-etm4x.h | 120 +++++++++++--- 7 files changed, 268 insertions(+), 212 deletions(-)

3 years

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