Tcwg-commits February 2023

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[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_gnu_cross_check_gcc/master-aarch64 updated (5aa7287c72 -> 525de04ba5)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_gnu_cross_check_gcc/master-aarch64 in repository toolchain/ci/base-artifacts. discards 5aa7287c72 385: onsuccess: #2636: 1: Success after binutils/gcc/gdb: 10 [...] discards 19ea960744 384: onsuccess: #2635: 1: Success after binutils/gcc/gdb: 10 [...] discards 9c7f17dccf 383: onsuccess: #2634: 1: Success after binutils/gcc/linux/g [...] discards dce2839b00 382: onsuccess: #2633: 1: Success after binutils/gcc/linux/g [...] discards dff5e9a053 381: onsuccess: #2632: 1: Success after binutils/gcc/gdb/qem [...] discards 3814cf1f8e 380: onsuccess: #2631: 1: Success after binutils/gcc/linux/g [...] discards 9999eb775c 379: onsuccess: #2630: 1: Success after binutils/gcc/linux/g [...] discards 2404ed3b16 378: onsuccess: #2629: 1: Success after binutils/gcc/glibc/g [...] discards adb91d158a 377: onsuccess: #2627: 1: Success after basepoints/gcc-13-57 [...] discards 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That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (5aa7287c72) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_gnu_cross_check_gcc/mast [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 102 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log.xz | Bin 1800 -> 1760 bytes 02-prepare_abe/console.log.xz | Bin 2776 -> 2764 bytes 03-build_abe-binutils/console.log.xz | Bin 31264 -> 31160 bytes 04-build_abe-stage1/console.log.xz | Bin 73616 -> 72792 bytes 06-build_abe-linux/console.log.xz | Bin 8672 -> 8664 bytes 07-build_abe-glibc/console.log.xz | Bin 245396 -> 244716 bytes 08-build_abe-stage2/console.log.xz | Bin 205112 -> 204000 bytes 09-build_abe-gdb/console.log.xz | Bin 38448 -> 38484 bytes 10-build_abe-qemu/console.log.xz | Bin 31688 -> 31368 bytes 11-build_abe-dejagnu/console.log.xz | Bin 3904 -> 3888 bytes 12-build_abe-check_gcc/console.log.xz | Bin 3324 -> 2644 bytes 13-check_regression/console.log.xz | Bin 5964 -> 6336 bytes 13-check_regression/extra-bisect-params | 2 +- 13-check_regression/fails.sum | 15 +- 13-check_regression/mail-body.txt | 67 +- 13-check_regression/results.compare | 41 +- 13-check_regression/results.compare2 | 54 +- 13-check_regression/results.regressions | 41 +- 14-update_baseline/console.log | 64 +- dashboard/dashboard-generate.sh | 2 +- git/binutils_rev | 2 +- git/gcc_rev | 2 +- git/gdb_rev | 2 +- git/linux_rev | 2 +- mail/jira-body.txt | 2 +- mail/mail-body.txt | 69 +- mail/mail-subject.txt | 2 +- manifest.sh | 36 +- results | 41 +- sumfiles/g++.log.xz | Bin 3417028 -> 3395232 bytes sumfiles/g++.sum | 18 +- sumfiles/gcc.log.xz | Bin 3023156 -> 3017024 bytes sumfiles/gcc.sum | 4838 +++++++++++++++---------------- sumfiles/gfortran.log.xz | Bin 1044640 -> 1035656 bytes sumfiles/gfortran.sum | 6 +- sumfiles/libatomic.log.xz | Bin 2288 -> 2292 bytes sumfiles/libatomic.sum | 2 +- sumfiles/libgomp.log.xz | Bin 217592 -> 217520 bytes sumfiles/libgomp.sum | 7 +- sumfiles/libitm.log.xz | Bin 2652 -> 2660 bytes sumfiles/libitm.sum | 2 +- sumfiles/libstdc++.log.xz | Bin 435536 -> 431104 bytes sumfiles/libstdc++.sum | 47 +- 43 files changed, 2768 insertions(+), 2596 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

1 year, 9 months

[gcc] branch master updated (b7e4f61c3e7 -> 79ef372fa41)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository gcc. from b7e4f61c3e7 RISC-V: Add vadc C++ API tests new dca23bf0bbe RISC-V: Add vmadc/vmsbc C/C++ API support new c8c7b4b32d8 RISC-V: Add vmadc C API tests new bd5c5d2eaf1 RISC-V: Add vmsbc C API tests new 485c710b4e6 RISC-V: Add vmadc C++ API tests new 30eedd6a4fc RISC-V: Add vmsbc C++ API tests new 6271a07219a RISC-V: Add vnsrl/vnsra/vncvt/vmerge/vmv C/C++ support new 10e999a3abd RISC-V: Add vnsrl C API tests new eeec45d2923 RISC-V: Add vnsra C API tests new fb03f2acfb7 RISC-V: Add vncvt C API tests new c1294253310 RISC-V: Add vmv C API tests new 4852c719a1a RISC-V: Add vmv.v.x C API tests new c0ea34be11c RISC-V: Add vmerge C API tests new 0b7dd2f4799 RISC-V: Add vnsrl C++ API tests new 484ea18ffae RISC-V: Add vnsra C++ API tests new 9a1c81afd55 RISC-V: Add vncvt/vmv C++ API tests new 79ef372fa41 RISC-V: Add vmerge C++ API test The 16 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: gcc/config/riscv/constraints.md | 13 - gcc/config/riscv/predicates.md | 7 +- gcc/config/riscv/riscv-vector-builtins-bases.cc | 140 ++++ gcc/config/riscv/riscv-vector-builtins-bases.h | 7 + .../riscv/riscv-vector-builtins-functions.def | 25 +- gcc/config/riscv/riscv-vector-builtins-shapes.cc | 82 +++ gcc/config/riscv/riscv-vector-builtins-shapes.h | 3 + gcc/config/riscv/riscv-vector-builtins.cc | 149 ++++- gcc/config/riscv/riscv-vector-builtins.def | 5 +- gcc/config/riscv/riscv-vector-builtins.h | 11 + gcc/config/riscv/riscv.cc | 42 +- gcc/config/riscv/vector-iterators.md | 6 + gcc/config/riscv/vector.md | 733 ++++++++++++++++++++- .../g++.target/riscv/rvv/base/vmadc_vv-1.C | 292 ++++++++ .../g++.target/riscv/rvv/base/vmadc_vv-2.C | 292 ++++++++ .../g++.target/riscv/rvv/base/vmadc_vv-3.C | 292 ++++++++ .../g++.target/riscv/rvv/base/vmadc_vvm-1.C | 292 ++++++++ .../g++.target/riscv/rvv/base/vmadc_vvm-2.C | 292 ++++++++ .../g++.target/riscv/rvv/base/vmadc_vvm-3.C | 292 ++++++++ .../g++.target/riscv/rvv/base/vmadc_vx_rv32-1.C | 289 ++++++++ .../g++.target/riscv/rvv/base/vmadc_vx_rv32-2.C | 289 ++++++++ .../g++.target/riscv/rvv/base/vmadc_vx_rv32-3.C | 289 ++++++++ .../g++.target/riscv/rvv/base/vmadc_vx_rv64-1.C | 292 ++++++++ .../g++.target/riscv/rvv/base/vmadc_vx_rv64-2.C | 292 ++++++++ .../g++.target/riscv/rvv/base/vmadc_vx_rv64-3.C | 292 ++++++++ .../g++.target/riscv/rvv/base/vmadc_vxm_rv32-1.C | 289 ++++++++ .../g++.target/riscv/rvv/base/vmadc_vxm_rv32-2.C | 289 ++++++++ .../g++.target/riscv/rvv/base/vmadc_vxm_rv32-3.C | 289 ++++++++ .../g++.target/riscv/rvv/base/vmadc_vxm_rv64-1.C | 292 ++++++++ .../g++.target/riscv/rvv/base/vmadc_vxm_rv64-2.C | 292 ++++++++ .../g++.target/riscv/rvv/base/vmadc_vxm_rv64-3.C | 292 ++++++++ .../g++.target/riscv/rvv/base/vmerge_vvm-1.C | 292 ++++++++ .../g++.target/riscv/rvv/base/vmerge_vvm-2.C | 292 ++++++++ .../g++.target/riscv/rvv/base/vmerge_vvm-3.C | 292 ++++++++ .../g++.target/riscv/rvv/base/vmerge_vvm-4.C | 292 ++++++++ .../g++.target/riscv/rvv/base/vmerge_vvm-5.C | 292 ++++++++ .../g++.target/riscv/rvv/base/vmerge_vvm-6.C | 292 ++++++++ .../g++.target/riscv/rvv/base/vmerge_vvm_tu-1.C | 292 ++++++++ .../g++.target/riscv/rvv/base/vmerge_vvm_tu-2.C | 292 ++++++++ .../g++.target/riscv/rvv/base/vmerge_vvm_tu-3.C | 292 ++++++++ .../g++.target/riscv/rvv/base/vmerge_vvm_tu-4.C | 292 ++++++++ .../g++.target/riscv/rvv/base/vmerge_vvm_tu-5.C | 292 ++++++++ .../g++.target/riscv/rvv/base/vmerge_vvm_tu-6.C | 292 ++++++++ .../g++.target/riscv/rvv/base/vmerge_vxm_rv32-1.C | 289 ++++++++ .../g++.target/riscv/rvv/base/vmerge_vxm_rv32-2.C | 289 ++++++++ .../g++.target/riscv/rvv/base/vmerge_vxm_rv32-3.C | 289 ++++++++ .../g++.target/riscv/rvv/base/vmerge_vxm_rv64-1.C | 292 ++++++++ .../g++.target/riscv/rvv/base/vmerge_vxm_rv64-2.C | 292 ++++++++ .../g++.target/riscv/rvv/base/vmerge_vxm_rv64-3.C | 292 ++++++++ .../riscv/rvv/base/vmerge_vxm_tu_rv32-1.C | 289 ++++++++ .../riscv/rvv/base/vmerge_vxm_tu_rv32-2.C | 289 ++++++++ .../riscv/rvv/base/vmerge_vxm_tu_rv32-3.C | 289 ++++++++ .../riscv/rvv/base/vmerge_vxm_tu_rv64-1.C | 292 ++++++++ .../riscv/rvv/base/vmerge_vxm_tu_rv64-2.C | 292 ++++++++ .../riscv/rvv/base/vmerge_vxm_tu_rv64-3.C | 292 ++++++++ .../g++.target/riscv/rvv/base/vmsbc_vv-1.C | 292 ++++++++ .../g++.target/riscv/rvv/base/vmsbc_vv-2.C | 292 ++++++++ .../g++.target/riscv/rvv/base/vmsbc_vv-3.C | 292 ++++++++ .../g++.target/riscv/rvv/base/vmsbc_vvm-1.C | 292 ++++++++ .../g++.target/riscv/rvv/base/vmsbc_vvm-2.C | 292 ++++++++ .../g++.target/riscv/rvv/base/vmsbc_vvm-3.C | 292 ++++++++ .../g++.target/riscv/rvv/base/vmsbc_vx_rv32-1.C | 289 ++++++++ .../g++.target/riscv/rvv/base/vmsbc_vx_rv32-2.C | 289 ++++++++ .../g++.target/riscv/rvv/base/vmsbc_vx_rv32-3.C | 289 ++++++++ .../g++.target/riscv/rvv/base/vmsbc_vx_rv64-1.C | 292 ++++++++ .../g++.target/riscv/rvv/base/vmsbc_vx_rv64-2.C | 292 ++++++++ .../g++.target/riscv/rvv/base/vmsbc_vx_rv64-3.C | 292 ++++++++ .../g++.target/riscv/rvv/base/vmsbc_vxm_rv32-1.C | 289 ++++++++ .../g++.target/riscv/rvv/base/vmsbc_vxm_rv32-2.C | 289 ++++++++ .../g++.target/riscv/rvv/base/vmsbc_vxm_rv32-3.C | 289 ++++++++ .../g++.target/riscv/rvv/base/vmsbc_vxm_rv64-1.C | 292 ++++++++ .../g++.target/riscv/rvv/base/vmsbc_vxm_rv64-2.C | 292 ++++++++ .../g++.target/riscv/rvv/base/vmsbc_vxm_rv64-3.C | 292 ++++++++ gcc/testsuite/g++.target/riscv/rvv/base/vmv_v-1.C | 392 +++++++++++ .../g++.target/riscv/rvv/base/vmv_v_tu-1.C | 392 +++++++++++ .../g++.target/riscv/rvv/base/vmv_v_x_rv32-1.C | 289 ++++++++ .../g++.target/riscv/rvv/base/vmv_v_x_rv32-2.C | 289 ++++++++ .../g++.target/riscv/rvv/base/vmv_v_x_rv32-3.C | 289 ++++++++ .../g++.target/riscv/rvv/base/vmv_v_x_rv64-1.C | 292 ++++++++ .../g++.target/riscv/rvv/base/vmv_v_x_rv64-2.C | 292 ++++++++ .../g++.target/riscv/rvv/base/vmv_v_x_rv64-3.C | 292 ++++++++ .../g++.target/riscv/rvv/base/vncvt_x-1.C | 396 +++++++++++ .../g++.target/riscv/rvv/base/vncvt_x-2.C | 396 +++++++++++ .../g++.target/riscv/rvv/base/vncvt_x-3.C | 396 +++++++++++ .../g++.target/riscv/rvv/base/vncvt_x_mu-1.C | 201 ++++++ .../g++.target/riscv/rvv/base/vncvt_x_mu-2.C | 201 ++++++ .../g++.target/riscv/rvv/base/vncvt_x_mu-3.C | 201 ++++++ .../g++.target/riscv/rvv/base/vncvt_x_tu-1.C | 201 ++++++ .../g++.target/riscv/rvv/base/vncvt_x_tu-2.C | 201 ++++++ .../g++.target/riscv/rvv/base/vncvt_x_tu-3.C | 201 ++++++ .../g++.target/riscv/rvv/base/vncvt_x_tum-1.C | 201 ++++++ .../g++.target/riscv/rvv/base/vncvt_x_tum-2.C | 201 ++++++ .../g++.target/riscv/rvv/base/vncvt_x_tum-3.C | 201 ++++++ .../g++.target/riscv/rvv/base/vncvt_x_tumu-1.C | 201 ++++++ .../g++.target/riscv/rvv/base/vncvt_x_tumu-2.C | 201 ++++++ .../g++.target/riscv/rvv/base/vncvt_x_tumu-3.C | 201 ++++++ .../g++.target/riscv/rvv/base/vnsra_vv-1.C | 216 ++++++ .../g++.target/riscv/rvv/base/vnsra_vv-2.C | 216 ++++++ .../g++.target/riscv/rvv/base/vnsra_vv-3.C | 216 ++++++ .../g++.target/riscv/rvv/base/vnsra_vv_mu-1.C | 111 ++++ .../g++.target/riscv/rvv/base/vnsra_vv_mu-2.C | 111 ++++ .../g++.target/riscv/rvv/base/vnsra_vv_mu-3.C | 111 ++++ .../g++.target/riscv/rvv/base/vnsra_vv_tu-1.C | 111 ++++ .../g++.target/riscv/rvv/base/vnsra_vv_tu-2.C | 111 ++++ .../g++.target/riscv/rvv/base/vnsra_vv_tu-3.C | 111 ++++ .../g++.target/riscv/rvv/base/vnsra_vv_tum-1.C | 111 ++++ .../g++.target/riscv/rvv/base/vnsra_vv_tum-2.C | 111 ++++ .../g++.target/riscv/rvv/base/vnsra_vv_tum-3.C | 111 ++++ .../g++.target/riscv/rvv/base/vnsra_vv_tumu-1.C | 111 ++++ .../g++.target/riscv/rvv/base/vnsra_vv_tumu-2.C | 111 ++++ .../g++.target/riscv/rvv/base/vnsra_vv_tumu-3.C | 111 ++++ .../g++.target/riscv/rvv/base/vnsra_vx-1.C | 216 ++++++ .../g++.target/riscv/rvv/base/vnsra_vx-2.C | 216 ++++++ .../g++.target/riscv/rvv/base/vnsra_vx-3.C | 216 ++++++ .../g++.target/riscv/rvv/base/vnsra_vx_mu-1.C | 111 ++++ .../g++.target/riscv/rvv/base/vnsra_vx_mu-2.C | 111 ++++ .../g++.target/riscv/rvv/base/vnsra_vx_mu-3.C | 111 ++++ .../g++.target/riscv/rvv/base/vnsra_vx_tu-1.C | 111 ++++ .../g++.target/riscv/rvv/base/vnsra_vx_tu-2.C | 111 ++++ .../g++.target/riscv/rvv/base/vnsra_vx_tu-3.C | 111 ++++ .../g++.target/riscv/rvv/base/vnsra_vx_tum-1.C | 111 ++++ .../g++.target/riscv/rvv/base/vnsra_vx_tum-2.C | 111 ++++ .../g++.target/riscv/rvv/base/vnsra_vx_tum-3.C | 111 ++++ .../g++.target/riscv/rvv/base/vnsra_vx_tumu-1.C | 111 ++++ .../g++.target/riscv/rvv/base/vnsra_vx_tumu-2.C | 111 ++++ .../g++.target/riscv/rvv/base/vnsra_vx_tumu-3.C | 111 ++++ .../g++.target/riscv/rvv/base/vnsrl_vv-1.C | 216 ++++++ .../g++.target/riscv/rvv/base/vnsrl_vv-2.C | 216 ++++++ .../g++.target/riscv/rvv/base/vnsrl_vv-3.C | 216 ++++++ .../g++.target/riscv/rvv/base/vnsrl_vv_mu-1.C | 111 ++++ .../g++.target/riscv/rvv/base/vnsrl_vv_mu-2.C | 111 ++++ .../g++.target/riscv/rvv/base/vnsrl_vv_mu-3.C | 111 ++++ .../g++.target/riscv/rvv/base/vnsrl_vv_tu-1.C | 111 ++++ .../g++.target/riscv/rvv/base/vnsrl_vv_tu-2.C | 111 ++++ .../g++.target/riscv/rvv/base/vnsrl_vv_tu-3.C | 111 ++++ .../g++.target/riscv/rvv/base/vnsrl_vv_tum-1.C | 111 ++++ .../g++.target/riscv/rvv/base/vnsrl_vv_tum-2.C | 111 ++++ .../g++.target/riscv/rvv/base/vnsrl_vv_tum-3.C | 111 ++++ .../g++.target/riscv/rvv/base/vnsrl_vv_tumu-1.C | 111 ++++ .../g++.target/riscv/rvv/base/vnsrl_vv_tumu-2.C | 111 ++++ .../g++.target/riscv/rvv/base/vnsrl_vv_tumu-3.C | 111 ++++ .../g++.target/riscv/rvv/base/vnsrl_vx-1.C | 216 ++++++ .../g++.target/riscv/rvv/base/vnsrl_vx-2.C | 216 ++++++ .../g++.target/riscv/rvv/base/vnsrl_vx-3.C | 216 ++++++ .../g++.target/riscv/rvv/base/vnsrl_vx_mu-1.C | 111 ++++ .../g++.target/riscv/rvv/base/vnsrl_vx_mu-2.C | 111 ++++ .../g++.target/riscv/rvv/base/vnsrl_vx_mu-3.C | 111 ++++ .../g++.target/riscv/rvv/base/vnsrl_vx_tu-1.C | 111 ++++ .../g++.target/riscv/rvv/base/vnsrl_vx_tu-2.C | 111 ++++ .../g++.target/riscv/rvv/base/vnsrl_vx_tu-3.C | 111 ++++ .../g++.target/riscv/rvv/base/vnsrl_vx_tum-1.C | 111 ++++ .../g++.target/riscv/rvv/base/vnsrl_vx_tum-2.C | 111 ++++ .../g++.target/riscv/rvv/base/vnsrl_vx_tum-3.C | 111 ++++ .../g++.target/riscv/rvv/base/vnsrl_vx_tumu-1.C | 111 ++++ .../g++.target/riscv/rvv/base/vnsrl_vx_tumu-2.C | 111 ++++ .../g++.target/riscv/rvv/base/vnsrl_vx_tumu-3.C | 111 ++++ .../riscv/rvv/base/{vadc-1.c => vmadc-1.c} | 12 +- gcc/testsuite/gcc.target/riscv/rvv/base/vmadc-2.c | 43 ++ .../riscv/rvv/base/{vadc-3.c => vmadc-3.c} | 48 +- .../riscv/rvv/base/{vadc-4.c => vmadc-4.c} | 50 +- .../riscv/rvv/base/{vadc-1.c => vmadc-5.c} | 13 +- gcc/testsuite/gcc.target/riscv/rvv/base/vmadc-6.c | 43 ++ gcc/testsuite/gcc.target/riscv/rvv/base/vmadc-7.c | 85 +++ gcc/testsuite/gcc.target/riscv/rvv/base/vmadc-8.c | 86 +++ .../gcc.target/riscv/rvv/base/vmadc_vv-1.c | 292 ++++++++ .../gcc.target/riscv/rvv/base/vmadc_vv-2.c | 292 ++++++++ .../gcc.target/riscv/rvv/base/vmadc_vv-3.c | 292 ++++++++ .../gcc.target/riscv/rvv/base/vmadc_vvm-1.c | 292 ++++++++ .../gcc.target/riscv/rvv/base/vmadc_vvm-2.c | 292 ++++++++ .../gcc.target/riscv/rvv/base/vmadc_vvm-3.c | 292 ++++++++ .../gcc.target/riscv/rvv/base/vmadc_vx_rv32-1.c | 289 ++++++++ .../gcc.target/riscv/rvv/base/vmadc_vx_rv32-2.c | 289 ++++++++ .../gcc.target/riscv/rvv/base/vmadc_vx_rv32-3.c | 289 ++++++++ .../gcc.target/riscv/rvv/base/vmadc_vx_rv64-1.c | 292 ++++++++ .../gcc.target/riscv/rvv/base/vmadc_vx_rv64-2.c | 292 ++++++++ .../gcc.target/riscv/rvv/base/vmadc_vx_rv64-3.c | 292 ++++++++ .../gcc.target/riscv/rvv/base/vmadc_vxm_rv32-1.c | 289 ++++++++ .../gcc.target/riscv/rvv/base/vmadc_vxm_rv32-2.c | 289 ++++++++ .../gcc.target/riscv/rvv/base/vmadc_vxm_rv32-3.c | 289 ++++++++ .../gcc.target/riscv/rvv/base/vmadc_vxm_rv64-1.c | 292 ++++++++ .../gcc.target/riscv/rvv/base/vmadc_vxm_rv64-2.c | 292 ++++++++ .../gcc.target/riscv/rvv/base/vmadc_vxm_rv64-3.c | 292 ++++++++ .../riscv/rvv/base/{vadc-1.c => vmerge-1.c} | 10 +- .../riscv/rvv/base/{vadc-2.c => vmerge-2.c} | 23 +- .../riscv/rvv/base/{vadc-3.c => vmerge-3.c} | 34 +- .../riscv/rvv/base/{vadc-4.c => vmerge-4.c} | 36 +- .../gcc.target/riscv/rvv/base/vmerge_vvm-1.c | 69 ++ .../gcc.target/riscv/rvv/base/vmerge_vvm-2.c | 69 ++ .../gcc.target/riscv/rvv/base/vmerge_vvm-3.c | 69 ++ .../gcc.target/riscv/rvv/base/vmerge_vvm-4.c | 292 ++++++++ .../gcc.target/riscv/rvv/base/vmerge_vvm-5.c | 292 ++++++++ .../gcc.target/riscv/rvv/base/vmerge_vvm-6.c | 292 ++++++++ .../gcc.target/riscv/rvv/base/vmerge_vvm_tu-1.c | 69 ++ .../gcc.target/riscv/rvv/base/vmerge_vvm_tu-2.c | 69 ++ .../gcc.target/riscv/rvv/base/vmerge_vvm_tu-3.c | 69 ++ .../gcc.target/riscv/rvv/base/vmerge_vvm_tu-4.c | 292 ++++++++ .../gcc.target/riscv/rvv/base/vmerge_vvm_tu-5.c | 292 ++++++++ .../gcc.target/riscv/rvv/base/vmerge_vvm_tu-6.c | 292 ++++++++ .../gcc.target/riscv/rvv/base/vmerge_vxm_rv32-1.c | 289 ++++++++ .../gcc.target/riscv/rvv/base/vmerge_vxm_rv32-2.c | 289 ++++++++ .../gcc.target/riscv/rvv/base/vmerge_vxm_rv32-3.c | 289 ++++++++ .../gcc.target/riscv/rvv/base/vmerge_vxm_rv64-1.c | 292 ++++++++ .../gcc.target/riscv/rvv/base/vmerge_vxm_rv64-2.c | 292 ++++++++ .../gcc.target/riscv/rvv/base/vmerge_vxm_rv64-3.c | 292 ++++++++ .../riscv/rvv/base/vmerge_vxm_tu_rv32-1.c | 289 ++++++++ .../riscv/rvv/base/vmerge_vxm_tu_rv32-2.c | 289 ++++++++ .../riscv/rvv/base/vmerge_vxm_tu_rv32-3.c | 289 ++++++++ .../riscv/rvv/base/vmerge_vxm_tu_rv64-1.c | 292 ++++++++ .../riscv/rvv/base/vmerge_vxm_tu_rv64-2.c | 292 ++++++++ .../riscv/rvv/base/vmerge_vxm_tu_rv64-3.c | 292 ++++++++ .../riscv/rvv/base/{vadc-1.c => vmsbc-1.c} | 12 +- gcc/testsuite/gcc.target/riscv/rvv/base/vmsbc-2.c | 42 ++ .../riscv/rvv/base/{vsbc-3.c => vmsbc-3.c} | 46 +- .../riscv/rvv/base/{vsbc-4.c => vmsbc-4.c} | 48 +- .../riscv/rvv/base/{vadc-1.c => vmsbc-5.c} | 13 +- gcc/testsuite/gcc.target/riscv/rvv/base/vmsbc-6.c | 42 ++ gcc/testsuite/gcc.target/riscv/rvv/base/vmsbc-7.c | 84 +++ gcc/testsuite/gcc.target/riscv/rvv/base/vmsbc-8.c | 84 +++ .../gcc.target/riscv/rvv/base/vmsbc_vv-1.c | 292 ++++++++ .../gcc.target/riscv/rvv/base/vmsbc_vv-2.c | 292 ++++++++ .../gcc.target/riscv/rvv/base/vmsbc_vv-3.c | 292 ++++++++ .../gcc.target/riscv/rvv/base/vmsbc_vvm-1.c | 292 ++++++++ .../gcc.target/riscv/rvv/base/vmsbc_vvm-2.c | 292 ++++++++ .../gcc.target/riscv/rvv/base/vmsbc_vvm-3.c | 292 ++++++++ .../gcc.target/riscv/rvv/base/vmsbc_vx_rv32-1.c | 289 ++++++++ .../gcc.target/riscv/rvv/base/vmsbc_vx_rv32-2.c | 289 ++++++++ .../gcc.target/riscv/rvv/base/vmsbc_vx_rv32-3.c | 289 ++++++++ .../gcc.target/riscv/rvv/base/vmsbc_vx_rv64-1.c | 292 ++++++++ .../gcc.target/riscv/rvv/base/vmsbc_vx_rv64-2.c | 292 ++++++++ .../gcc.target/riscv/rvv/base/vmsbc_vx_rv64-3.c | 292 ++++++++ .../gcc.target/riscv/rvv/base/vmsbc_vxm_rv32-1.c | 289 ++++++++ .../gcc.target/riscv/rvv/base/vmsbc_vxm_rv32-2.c | 289 ++++++++ .../gcc.target/riscv/rvv/base/vmsbc_vxm_rv32-3.c | 289 ++++++++ .../gcc.target/riscv/rvv/base/vmsbc_vxm_rv64-1.c | 292 ++++++++ .../gcc.target/riscv/rvv/base/vmsbc_vxm_rv64-2.c | 292 ++++++++ .../gcc.target/riscv/rvv/base/vmsbc_vxm_rv64-3.c | 292 ++++++++ .../gcc.target/riscv/rvv/base/vmv_v_v-1.c | 276 ++++++++ .../gcc.target/riscv/rvv/base/vmv_v_v-2.c | 276 ++++++++ .../gcc.target/riscv/rvv/base/vmv_v_v-3.c | 276 ++++++++ .../gcc.target/riscv/rvv/base/vmv_v_v_tu-1.c | 276 ++++++++ .../gcc.target/riscv/rvv/base/vmv_v_v_tu-2.c | 276 ++++++++ .../gcc.target/riscv/rvv/base/vmv_v_v_tu-3.c | 276 ++++++++ .../gcc.target/riscv/rvv/base/vmv_v_x_rv32-1.c | 289 ++++++++ .../gcc.target/riscv/rvv/base/vmv_v_x_rv32-2.c | 289 ++++++++ .../gcc.target/riscv/rvv/base/vmv_v_x_rv32-3.c | 289 ++++++++ .../gcc.target/riscv/rvv/base/vmv_v_x_rv64-1.c | 292 ++++++++ .../gcc.target/riscv/rvv/base/vmv_v_x_rv64-2.c | 292 ++++++++ .../gcc.target/riscv/rvv/base/vmv_v_x_rv64-3.c | 292 ++++++++ .../gcc.target/riscv/rvv/base/vmv_v_x_tu_rv32-1.c | 289 ++++++++ .../gcc.target/riscv/rvv/base/vmv_v_x_tu_rv32-2.c | 289 ++++++++ .../gcc.target/riscv/rvv/base/vmv_v_x_tu_rv32-3.c | 289 ++++++++ .../gcc.target/riscv/rvv/base/vmv_v_x_tu_rv64-1.c | 292 ++++++++ .../gcc.target/riscv/rvv/base/vmv_v_x_tu_rv64-2.c | 292 ++++++++ .../gcc.target/riscv/rvv/base/vmv_v_x_tu_rv64-3.c | 292 ++++++++ .../gcc.target/riscv/rvv/base/vncvt_x-1.c | 201 ++++++ .../gcc.target/riscv/rvv/base/vncvt_x-2.c | 201 ++++++ .../gcc.target/riscv/rvv/base/vncvt_x-3.c | 201 ++++++ .../gcc.target/riscv/rvv/base/vncvt_x_m-1.c | 201 ++++++ .../gcc.target/riscv/rvv/base/vncvt_x_m-2.c | 201 ++++++ .../gcc.target/riscv/rvv/base/vncvt_x_m-3.c | 201 ++++++ .../gcc.target/riscv/rvv/base/vncvt_x_mu-1.c | 201 ++++++ .../gcc.target/riscv/rvv/base/vncvt_x_mu-2.c | 201 ++++++ .../gcc.target/riscv/rvv/base/vncvt_x_mu-3.c | 201 ++++++ .../gcc.target/riscv/rvv/base/vncvt_x_tu-1.c | 201 ++++++ .../gcc.target/riscv/rvv/base/vncvt_x_tu-2.c | 201 ++++++ .../gcc.target/riscv/rvv/base/vncvt_x_tu-3.c | 201 ++++++ .../gcc.target/riscv/rvv/base/vncvt_x_tum-1.c | 201 ++++++ .../gcc.target/riscv/rvv/base/vncvt_x_tum-2.c | 201 ++++++ .../gcc.target/riscv/rvv/base/vncvt_x_tum-3.c | 201 ++++++ .../gcc.target/riscv/rvv/base/vncvt_x_tumu-1.c | 201 ++++++ .../gcc.target/riscv/rvv/base/vncvt_x_tumu-2.c | 201 ++++++ .../gcc.target/riscv/rvv/base/vncvt_x_tumu-3.c | 201 ++++++ .../gcc.target/riscv/rvv/base/vnsra_wv-1.c | 111 ++++ .../gcc.target/riscv/rvv/base/vnsra_wv-2.c | 111 ++++ .../gcc.target/riscv/rvv/base/vnsra_wv-3.c | 111 ++++ .../gcc.target/riscv/rvv/base/vnsra_wv_m-1.c | 111 ++++ .../gcc.target/riscv/rvv/base/vnsra_wv_m-2.c | 111 ++++ .../gcc.target/riscv/rvv/base/vnsra_wv_m-3.c | 111 ++++ .../gcc.target/riscv/rvv/base/vnsra_wv_mu-1.c | 111 ++++ .../gcc.target/riscv/rvv/base/vnsra_wv_mu-2.c | 111 ++++ .../gcc.target/riscv/rvv/base/vnsra_wv_mu-3.c | 111 ++++ .../gcc.target/riscv/rvv/base/vnsra_wv_tu-1.c | 111 ++++ .../gcc.target/riscv/rvv/base/vnsra_wv_tu-2.c | 111 ++++ .../gcc.target/riscv/rvv/base/vnsra_wv_tu-3.c | 111 ++++ .../gcc.target/riscv/rvv/base/vnsra_wv_tum-1.c | 111 ++++ .../gcc.target/riscv/rvv/base/vnsra_wv_tum-2.c | 111 ++++ .../gcc.target/riscv/rvv/base/vnsra_wv_tum-3.c | 111 ++++ .../gcc.target/riscv/rvv/base/vnsra_wv_tumu-1.c | 111 ++++ .../gcc.target/riscv/rvv/base/vnsra_wv_tumu-2.c | 111 ++++ .../gcc.target/riscv/rvv/base/vnsra_wv_tumu-3.c | 111 ++++ .../gcc.target/riscv/rvv/base/vnsra_wx-1.c | 111 ++++ .../gcc.target/riscv/rvv/base/vnsra_wx-2.c | 111 ++++ .../gcc.target/riscv/rvv/base/vnsra_wx-3.c | 111 ++++ .../gcc.target/riscv/rvv/base/vnsra_wx_m-1.c | 111 ++++ .../gcc.target/riscv/rvv/base/vnsra_wx_m-2.c | 111 ++++ .../gcc.target/riscv/rvv/base/vnsra_wx_m-3.c | 111 ++++ .../gcc.target/riscv/rvv/base/vnsra_wx_mu-1.c | 111 ++++ .../gcc.target/riscv/rvv/base/vnsra_wx_mu-2.c | 111 ++++ .../gcc.target/riscv/rvv/base/vnsra_wx_mu-3.c | 111 ++++ .../gcc.target/riscv/rvv/base/vnsra_wx_tu-1.c | 111 ++++ .../gcc.target/riscv/rvv/base/vnsra_wx_tu-2.c | 111 ++++ .../gcc.target/riscv/rvv/base/vnsra_wx_tu-3.c | 111 ++++ .../gcc.target/riscv/rvv/base/vnsra_wx_tum-1.c | 111 ++++ .../gcc.target/riscv/rvv/base/vnsra_wx_tum-2.c | 111 ++++ .../gcc.target/riscv/rvv/base/vnsra_wx_tum-3.c | 111 ++++ .../gcc.target/riscv/rvv/base/vnsra_wx_tumu-1.c | 111 ++++ .../gcc.target/riscv/rvv/base/vnsra_wx_tumu-2.c | 111 ++++ .../gcc.target/riscv/rvv/base/vnsra_wx_tumu-3.c | 111 ++++ .../gcc.target/riscv/rvv/base/vnsrl_wv-1.c | 111 ++++ .../gcc.target/riscv/rvv/base/vnsrl_wv-2.c | 111 ++++ .../gcc.target/riscv/rvv/base/vnsrl_wv-3.c | 111 ++++ .../gcc.target/riscv/rvv/base/vnsrl_wv_m-1.c | 111 ++++ .../gcc.target/riscv/rvv/base/vnsrl_wv_m-2.c | 111 ++++ .../gcc.target/riscv/rvv/base/vnsrl_wv_m-3.c | 111 ++++ .../gcc.target/riscv/rvv/base/vnsrl_wv_mu-1.c | 111 ++++ .../gcc.target/riscv/rvv/base/vnsrl_wv_mu-2.c | 111 ++++ .../gcc.target/riscv/rvv/base/vnsrl_wv_mu-3.c | 111 ++++ .../gcc.target/riscv/rvv/base/vnsrl_wv_tu-1.c | 111 ++++ .../gcc.target/riscv/rvv/base/vnsrl_wv_tu-2.c | 111 ++++ .../gcc.target/riscv/rvv/base/vnsrl_wv_tu-3.c | 111 ++++ .../gcc.target/riscv/rvv/base/vnsrl_wv_tum-1.c | 111 ++++ .../gcc.target/riscv/rvv/base/vnsrl_wv_tum-2.c | 111 ++++ .../gcc.target/riscv/rvv/base/vnsrl_wv_tum-3.c | 111 ++++ .../gcc.target/riscv/rvv/base/vnsrl_wv_tumu-1.c | 111 ++++ .../gcc.target/riscv/rvv/base/vnsrl_wv_tumu-2.c | 111 ++++ .../gcc.target/riscv/rvv/base/vnsrl_wv_tumu-3.c | 111 ++++ .../gcc.target/riscv/rvv/base/vnsrl_wx-1.c | 111 ++++ .../gcc.target/riscv/rvv/base/vnsrl_wx-2.c | 111 ++++ .../gcc.target/riscv/rvv/base/vnsrl_wx-3.c | 111 ++++ .../gcc.target/riscv/rvv/base/vnsrl_wx_m-1.c | 111 ++++ .../gcc.target/riscv/rvv/base/vnsrl_wx_m-2.c | 111 ++++ .../gcc.target/riscv/rvv/base/vnsrl_wx_m-3.c | 111 ++++ .../gcc.target/riscv/rvv/base/vnsrl_wx_mu-1.c | 111 ++++ .../gcc.target/riscv/rvv/base/vnsrl_wx_mu-2.c | 111 ++++ .../gcc.target/riscv/rvv/base/vnsrl_wx_mu-3.c | 111 ++++ .../gcc.target/riscv/rvv/base/vnsrl_wx_tu-1.c | 111 ++++ .../gcc.target/riscv/rvv/base/vnsrl_wx_tu-2.c | 111 ++++ .../gcc.target/riscv/rvv/base/vnsrl_wx_tu-3.c | 111 ++++ .../gcc.target/riscv/rvv/base/vnsrl_wx_tum-1.c | 111 ++++ .../gcc.target/riscv/rvv/base/vnsrl_wx_tum-2.c | 111 ++++ .../gcc.target/riscv/rvv/base/vnsrl_wx_tum-3.c | 111 ++++ .../gcc.target/riscv/rvv/base/vnsrl_wx_tumu-1.c | 111 ++++ .../gcc.target/riscv/rvv/base/vnsrl_wx_tumu-2.c | 111 ++++ .../gcc.target/riscv/rvv/base/vnsrl_wx_tumu-3.c | 111 ++++ 344 files changed, 66241 insertions(+), 229 deletions(-) create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmadc_vv-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmadc_vv-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmadc_vv-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmadc_vvm-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmadc_vvm-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmadc_vvm-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmadc_vx_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmadc_vx_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmadc_vx_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmadc_vx_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmadc_vx_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmadc_vx_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmadc_vxm_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmadc_vxm_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmadc_vxm_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmadc_vxm_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmadc_vxm_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmadc_vxm_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmerge_vvm-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmerge_vvm-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmerge_vvm-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmerge_vvm-4.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmerge_vvm-5.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmerge_vvm-6.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmerge_vvm_tu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmerge_vvm_tu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmerge_vvm_tu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmerge_vvm_tu-4.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmerge_vvm_tu-5.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmerge_vvm_tu-6.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmerge_vxm_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmerge_vxm_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmerge_vxm_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmerge_vxm_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmerge_vxm_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmerge_vxm_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmerge_vxm_tu_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmerge_vxm_tu_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmerge_vxm_tu_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmerge_vxm_tu_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmerge_vxm_tu_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmerge_vxm_tu_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsbc_vv-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsbc_vv-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsbc_vv-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsbc_vvm-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsbc_vvm-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsbc_vvm-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsbc_vx_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsbc_vx_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsbc_vx_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsbc_vx_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsbc_vx_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsbc_vx_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsbc_vxm_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsbc_vxm_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsbc_vxm_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsbc_vxm_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsbc_vxm_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsbc_vxm_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmv_v-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmv_v_tu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmv_v_x_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmv_v_x_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmv_v_x_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmv_v_x_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmv_v_x_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmv_v_x_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vncvt_x-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vncvt_x-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vncvt_x-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vncvt_x_mu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vncvt_x_mu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vncvt_x_mu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vncvt_x_tu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vncvt_x_tu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vncvt_x_tu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vncvt_x_tum-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vncvt_x_tum-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vncvt_x_tum-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vncvt_x_tumu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vncvt_x_tumu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vncvt_x_tumu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnsra_vv-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnsra_vv-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnsra_vv-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnsra_vv_mu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnsra_vv_mu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnsra_vv_mu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnsra_vv_tu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnsra_vv_tu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnsra_vv_tu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnsra_vv_tum-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnsra_vv_tum-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnsra_vv_tum-3.C create mode 100644 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gcc/testsuite/gcc.target/riscv/rvv/base/{vadc-1.c => vmadc-5.c} (51%) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmadc-6.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmadc-7.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmadc-8.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmadc_vv-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmadc_vv-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmadc_vv-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmadc_vvm-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmadc_vvm-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmadc_vvm-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmadc_vx_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmadc_vx_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmadc_vx_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmadc_vx_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmadc_vx_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmadc_vx_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmadc_vxm_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmadc_vxm_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmadc_vxm_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmadc_vxm_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmadc_vxm_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmadc_vxm_rv64-3.c copy gcc/testsuite/gcc.target/riscv/rvv/base/{vadc-1.c => vmerge-1.c} (63%) copy gcc/testsuite/gcc.target/riscv/rvv/base/{vadc-2.c => vmerge-2.c} (56%) copy gcc/testsuite/gcc.target/riscv/rvv/base/{vadc-3.c => vmerge-3.c} (61%) copy gcc/testsuite/gcc.target/riscv/rvv/base/{vadc-4.c => vmerge-4.c} (59%) create mode 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gcc/testsuite/gcc.target/riscv/rvv/base/vmerge_vxm_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmerge_vxm_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmerge_vxm_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmerge_vxm_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmerge_vxm_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmerge_vxm_tu_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmerge_vxm_tu_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmerge_vxm_tu_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmerge_vxm_tu_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmerge_vxm_tu_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmerge_vxm_tu_rv64-3.c copy gcc/testsuite/gcc.target/riscv/rvv/base/{vadc-1.c => vmsbc-1.c} (56%) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsbc-2.c copy gcc/testsuite/gcc.target/riscv/rvv/base/{vsbc-3.c => vmsbc-3.c} (53%) copy gcc/testsuite/gcc.target/riscv/rvv/base/{vsbc-4.c => vmsbc-4.c} (52%) copy gcc/testsuite/gcc.target/riscv/rvv/base/{vadc-1.c => vmsbc-5.c} (51%) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsbc-6.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsbc-7.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsbc-8.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsbc_vv-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsbc_vv-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsbc_vv-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsbc_vvm-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsbc_vvm-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsbc_vvm-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsbc_vx_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsbc_vx_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsbc_vx_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsbc_vx_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsbc_vx_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsbc_vx_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsbc_vxm_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsbc_vxm_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsbc_vxm_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsbc_vxm_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsbc_vxm_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsbc_vxm_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmv_v_v-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmv_v_v-2.c create mode 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gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wx_tumu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wx_tumu-3.c -- To stop receiving notification emails like this one, please contact the administrator of this repository.

1 year, 9 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_gnu_cross_build/master-aarch64 updated (f5811bb45c -> 841f43cbaa)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_gnu_cross_build/master-aarch64 in repository toolchain/ci/base-artifacts. discards f5811bb45c 400: onsuccess: #2103: 7: Success after binutils/gcc/linux/g [...] discards e62a3ce56e 399: onsuccess: #2102: 7: Success after binutils/gcc/gdb: 9 commits discards adbb96bc8b 398: onsuccess: #2101: 7: Success after binutils/gcc/gdb: 6 commits discards b3bb296759 397: onsuccess: #2100: 7: Success after binutils/gcc/gdb: 9 commits discards d514c97052 396: onsuccess: #2099: 7: Success after binutils/gcc/linux/g [...] discards 16d1e24d59 395: onsuccess: #2098: 7: Success after binutils/gcc/linux/g [...] discards 335f3d9644 394: onsuccess: #2097: 7: Success after binutils/gcc/gdb/qem [...] discards 95b7fd1e28 393: onsuccess: #2096: 7: Success after gcc/linux: 45 commits discards 3f3bf707d5 392: onsuccess: #2095: 7: Success after binutils/gcc/linux/g [...] discards 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That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (f5811bb45c) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_gnu_cross_build/master-a [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 102 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log.xz | Bin 1740 -> 1740 bytes 02-prepare_abe/console.log.xz | Bin 2772 -> 2776 bytes 04-build_abe-binutils/console.log.xz | Bin 31168 -> 33736 bytes 05-build_abe-stage1/console.log.xz | Bin 73048 -> 73344 bytes 07-build_abe-linux/console.log.xz | Bin 8640 -> 8692 bytes 08-build_abe-glibc/console.log.xz | Bin 244744 -> 245344 bytes 09-build_abe-stage2/console.log.xz | Bin 204036 -> 205360 bytes 10-build_abe-gdb/console.log.xz | Bin 38452 -> 41080 bytes 11-build_abe-qemu/console.log.xz | Bin 31592 -> 31876 bytes 12-check_regression/console.log.xz | Bin 3708 -> 3692 bytes 13-update_baseline/console.log | 64 +++++++++++++++++------------------ dashboard/dashboard-generate.sh | 2 +- git/binutils_rev | 2 +- git/gcc_rev | 2 +- git/gdb_rev | 2 +- mail/jira-body.txt | 2 +- mail/mail-body.txt | 2 +- mail/mail-subject.txt | 2 +- manifest.sh | 34 +++++++++---------- 19 files changed, 56 insertions(+), 56 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

1 year, 9 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_gcc_check_bootstrap/master-aarch64-check_bootstrap_lto updated (970ed860fd -> ffa0532d58)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_gcc_check_bootstrap/master-aarch64-check_bootstrap_lto in repository toolchain/ci/base-artifacts. discards 970ed860fd 173: onsuccess: #741: 1: Success after binutils/gcc: 82 commits discards bc92fa9b80 172: onsuccess: #740: 1: Success after binutils/gcc: 9 commits discards f7a63ef213 171: onsuccess: #739: 1: Success after binutils/gcc: 41 commits discards d6b22fd963 170: onsuccess: #738: 1: Success after binutils/gcc: 16 commits discards 6100ce1a11 169: onsuccess: #737: 1: Success after binutils/gcc: 30 commits discards 599ee47844 168: onsuccess: #736: 1: Success after binutils/gcc: 8 commits discards 6fbcbbefd3 167: onsuccess: #735: 1: Success after binutils/gcc: 28 commits discards 9c4d305ac8 166: onsuccess: #734: 1: Success after binutils/gcc: 59 commits discards d88e16c45b 165: onsuccess: #733: 1: Success after binutils/gcc: 42 commits discards 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new b96b04bc62 167: onsuccess: #735: 1: Success after binutils/gcc: 28 commits new 21e929c1a6 168: onsuccess: #736: 1: Success after binutils/gcc: 8 commits new 11aaa732cf 169: onsuccess: #737: 1: Success after binutils/gcc: 30 commits new 5013e1463c 170: onsuccess: #738: 1: Success after binutils/gcc: 16 commits new a7a21b2f06 171: onsuccess: #739: 1: Success after binutils/gcc: 41 commits new 396bc240f5 172: onsuccess: #740: 1: Success after binutils/gcc: 9 commits new def52739eb 173: onsuccess: #741: 1: Success after binutils/gcc: 82 commits new ffa0532d58 174: onsuccess: #742: 1: Success after binutils/gcc: 54 commits This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (970ed860fd) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_gcc_check_bootstrap/mast [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 102 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log.xz | Bin 1828 -> 1812 bytes 02-prepare_abe/console.log.xz | Bin 2760 -> 2748 bytes 03-build_abe-binutils/console.log.xz | Bin 38636 -> 38828 bytes 04-build_abe-bootstrap_lto/console.log.xz | Bin 278080 -> 279012 bytes 05-build_abe-dejagnu/console.log.xz | Bin 3900 -> 3848 bytes 06-build_abe-check_bootstrap_lto/console.log.xz | Bin 2508 -> 2696 bytes 07-check_regression/console.log.xz | Bin 6028 -> 5988 bytes 07-check_regression/extra-bisect-params | 1 + 07-check_regression/fails.sum | 7 + 07-check_regression/mail-body.txt | 27 + 07-check_regression/results.compare | 32 +- 07-check_regression/results.compare2 | 155 +- 07-check_regression/results.regressions | 27 + 08-update_baseline/console.log | 64 +- dashboard/dashboard-generate.sh | 2 +- git/binutils_rev | 2 +- git/gcc_rev | 2 +- mail/jira-body.txt | 2 +- mail/mail-body.txt | 29 +- mail/mail-subject.txt | 2 +- manifest.sh | 18 +- results | 27 + sumfiles/g++.log.xz | Bin 3660660 -> 3690008 bytes sumfiles/g++.sum | 124 +- sumfiles/gcc.log.xz | Bin 3236804 -> 3232108 bytes sumfiles/gcc.sum | 4703 ++++++++++++----------- sumfiles/gfortran.log.xz | Bin 1091928 -> 1102652 bytes sumfiles/gfortran.sum | 42 +- sumfiles/libatomic.log.xz | Bin 2348 -> 2352 bytes sumfiles/libatomic.sum | 4 +- sumfiles/libgomp.log.xz | Bin 229008 -> 228768 bytes sumfiles/libgomp.sum | 16 +- sumfiles/libitm.log.xz | Bin 2724 -> 2724 bytes sumfiles/libitm.sum | 6 +- sumfiles/libstdc++.log.xz | Bin 470292 -> 476512 bytes sumfiles/libstdc++.sum | 10 +- 36 files changed, 2677 insertions(+), 2625 deletions(-) create mode 100644 07-check_regression/extra-bisect-params create mode 100644 07-check_regression/fails.sum create mode 100644 07-check_regression/results.regressions -- To stop receiving notification emails like this one, please contact the administrator of this repository.

1 year, 9 months

[binutils-gdb] branch master updated (f0bdf68d3fb -> 8282ad74c30)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository binutils-gdb. from f0bdf68d3fb gdb/c++: fix handling of breakpoints on @plt symbols new 8282ad74c30 gdb: fix describe_other_breakpoints for default task being -1 The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: gdb/breakpoint.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

1 year, 9 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_bmk-code_speed-spec2k6/llvm-arm-master-O3_LTO updated (3b085ca268 -> 5a3dad7bb3)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_bmk-code_speed-spec2k6/llvm-arm-master-O3_LTO in repository toolchain/ci/base-artifacts. from 3b085ca268 60: onsuccess: #20: 1: [TCWG CI] No change after binutils/gc [...] new 5a3dad7bb3 61: onsuccess: #21: 1: [TCWG CI] No change after binutils/gc [...] The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log.xz | Bin 1848 -> 1848 bytes 02-prepare_abe/console.log.xz | Bin 2796 -> 2772 bytes 03-build_abe-binutils/console.log.xz | Bin 31576 -> 31296 bytes 04-build_abe-stage1/console.log.xz | Bin 93120 -> 94300 bytes 06-build_abe-linux/console.log.xz | Bin 8672 -> 8708 bytes 07-build_abe-glibc/console.log.xz | Bin 238380 -> 238068 bytes 08-build_abe-stage2/console.log.xz | Bin 224296 -> 219856 bytes 09-build_llvm-true-false-cflags-/console.log.xz | Bin 63452 -> 63684 bytes 10-benchmark/benchmark-build.log | 130 +- 10-benchmark/benchmark.log | 128 +- 10-benchmark/console.log.xz | Bin 4020 -> 3996 bytes 11-check_regression/console.log.xz | Bin 8128 -> 7692 bytes .../csv-results-vs-first-0/results.csv | 242698 +++++++------- .../csv-results-vs-first-0/size.csv | 250206 +++++++-------- 11-check_regression/csv-results-vs-first-0/sve.csv | 18 +- .../csv-results-vs-first-1/perf.csv | 113 +- .../csv-results-vs-first-1/results.csv | 297465 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18 +- .../squad-vs-first/458.sjeng/results-metadata.json | 18 +- .../squad-vs-first/458.sjeng/results-metrics.json | 2 +- .../462.libquantum/results-metadata.json | 18 +- .../464.h264ref/results-metadata.json | 18 +- .../464.h264ref/results-metrics.json | 2 +- .../squad-vs-first/470.lbm/results-metadata.json | 18 +- .../squad-vs-first/470.lbm/results-metrics.json | 2 +- .../471.omnetpp/results-metadata.json | 18 +- .../471.omnetpp/results-metrics.json | 2 +- .../squad-vs-first/473.astar/results-metadata.json | 18 +- .../482.sphinx3/results-metadata.json | 18 +- .../483.xalancbmk/results-metadata.json | 18 +- .../squad-vs-first/Mean/results-metadata.json | 18 +- dashboard/squad-vs-first/dashboard-push-squad.sh | 82 +- git/binutils_rev | 2 +- git/gcc_rev | 2 +- git/glibc_rev | 2 +- git/linux_rev | 2 +- git/llvm_rev | 2 +- mail/jira-body.txt | 60 +- mail/mail-body.txt | 60 +- mail/mail-subject.txt | 2 +- manifest.sh | 42 +- results_id | 2 +- save-temps/400.perlbench.tar.xz | Bin 401664 -> 2929656 bytes save-temps/401.bzip2.tar.xz | Bin 42728 -> 301040 bytes save-temps/403.gcc.tar.xz | Bin 1214176 -> 7625560 bytes save-temps/410.bwaves.tar.xz | Bin 0 -> 53080 bytes save-temps/416.gamess.tar.xz | Bin 0 -> 17149476 bytes save-temps/429.mcf.tar.xz | Bin 22308 -> 71796 bytes save-temps/433.milc.tar.xz | Bin 58720 -> 370604 bytes save-temps/434.zeusmp.tar.xz | Bin 0 -> 530532 bytes save-temps/435.gromacs.tar.xz | Bin 0 -> 2368288 bytes save-temps/436.cactusADM.tar.xz | Bin 0 -> 1833968 bytes save-temps/437.leslie3d.tar.xz | Bin 0 -> 176528 bytes save-temps/444.namd.tar.xz | Bin 44912 -> 674188 bytes save-temps/445.gobmk.tar.xz | Bin 620148 -> 2723592 bytes save-temps/447.dealII.tar.xz | Bin 878220 -> 11643184 bytes save-temps/450.soplex.tar.xz | Bin 207588 -> 1472664 bytes save-temps/453.povray.tar.xz | Bin 460732 -> 2672576 bytes save-temps/454.calculix.tar.xz | Bin 0 -> 3557816 bytes save-temps/456.hmmer.tar.xz | Bin 123556 -> 988732 bytes save-temps/458.sjeng.tar.xz | Bin 50788 -> 322344 bytes save-temps/459.GemsFDTD.tar.xz | Bin 0 -> 640068 bytes save-temps/462.libquantum.tar.xz | Bin 23760 -> 116332 bytes save-temps/464.h264ref.tar.xz | Bin 176052 -> 3324868 bytes .../results.csv => save-temps/465.tonto.tar.xz | Bin 8490370 -> 8355464 bytes save-temps/470.lbm.tar.xz | Bin 15536 -> 52176 bytes save-temps/471.omnetpp.tar.xz | Bin 369768 -> 1522300 bytes save-temps/473.astar.tar.xz | Bin 41856 -> 160528 bytes .../results.csv => save-temps/481.wrf.tar.xz | Bin 9028569 -> 9113560 bytes save-temps/482.sphinx3.tar.xz | Bin 94416 -> 586712 bytes save-temps/483.xalancbmk.tar.xz | Bin 3181884 -> 17713580 bytes 105 files changed, 1150695 insertions(+), 1133249 deletions(-) create mode 100644 save-temps/410.bwaves.tar.xz create mode 100644 save-temps/416.gamess.tar.xz create mode 100644 save-temps/434.zeusmp.tar.xz create mode 100644 save-temps/435.gromacs.tar.xz create mode 100644 save-temps/436.cactusADM.tar.xz create mode 100644 save-temps/437.leslie3d.tar.xz create mode 100644 save-temps/454.calculix.tar.xz create mode 100644 save-temps/459.GemsFDTD.tar.xz copy 11-check_regression/csv-results-vs-first-1/results.csv => save-temps/465.tont [...] copy 11-check_regression/csv-results-vs-prev-0/results.csv => save-temps/481.wrf.t [...] -- To stop receiving notification emails like this one, please contact the administrator of this repository.

1 year, 9 months

[gcc] branch master updated (316c83b158d -> b7e4f61c3e7)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository gcc. from 316c83b158d RISC-V: Add vwadd v C++ api test new 5e620b36cd3 RISC-V: allow vx instruction use "zero" as scalar register. new cb44a16d212 RISC-V: Add vadc/vsbc C/C++ API support new b5e7450a173 RISC-V: Add vadc.vvm/vadc.vxm C API tests new c2f4dc58105 RISC-V: Add vsbc.vvm/vsbc.vxm C API tests new 6483b831033 RISC-V: Add vsbc C++ API tests new b7e4f61c3e7 RISC-V: Add vadc C++ API tests The 6 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: gcc/config/riscv/riscv-protos.h | 1 + gcc/config/riscv/riscv-v.cc | 2 +- gcc/config/riscv/riscv-vector-builtins-bases.cc | 46 +++ gcc/config/riscv/riscv-vector-builtins-bases.h | 2 + .../riscv/riscv-vector-builtins-functions.def | 4 + gcc/config/riscv/riscv-vector-builtins-shapes.cc | 22 ++ gcc/config/riscv/riscv-vector-builtins-shapes.h | 1 + gcc/config/riscv/riscv-vector-builtins.cc | 50 ++- gcc/config/riscv/riscv-vector-builtins.h | 12 + gcc/config/riscv/vector-iterators.md | 3 + gcc/config/riscv/vector.md | 350 +++++++++++++++++++-- .../g++.target/riscv/rvv/base/vadc_vvm-1.C | 292 +++++++++++++++++ .../g++.target/riscv/rvv/base/vadc_vvm-2.C | 292 +++++++++++++++++ .../g++.target/riscv/rvv/base/vadc_vvm-3.C | 292 +++++++++++++++++ .../g++.target/riscv/rvv/base/vadc_vvm_tu-1.C | 292 +++++++++++++++++ .../g++.target/riscv/rvv/base/vadc_vvm_tu-2.C | 292 +++++++++++++++++ .../g++.target/riscv/rvv/base/vadc_vvm_tu-3.C | 292 +++++++++++++++++ .../g++.target/riscv/rvv/base/vadc_vxm_rv32-1.C | 289 +++++++++++++++++ .../g++.target/riscv/rvv/base/vadc_vxm_rv32-2.C | 289 +++++++++++++++++ .../g++.target/riscv/rvv/base/vadc_vxm_rv32-3.C | 289 +++++++++++++++++ .../g++.target/riscv/rvv/base/vadc_vxm_rv64-1.C | 292 +++++++++++++++++ .../g++.target/riscv/rvv/base/vadc_vxm_rv64-2.C | 292 +++++++++++++++++ .../g++.target/riscv/rvv/base/vadc_vxm_rv64-3.C | 292 +++++++++++++++++ .../g++.target/riscv/rvv/base/vadc_vxm_tu_rv32-1.C | 289 +++++++++++++++++ .../g++.target/riscv/rvv/base/vadc_vxm_tu_rv32-2.C | 289 +++++++++++++++++ .../g++.target/riscv/rvv/base/vadc_vxm_tu_rv32-3.C | 289 +++++++++++++++++ .../g++.target/riscv/rvv/base/vadc_vxm_tu_rv64-1.C | 292 +++++++++++++++++ .../g++.target/riscv/rvv/base/vadc_vxm_tu_rv64-2.C | 292 +++++++++++++++++ .../g++.target/riscv/rvv/base/vadc_vxm_tu_rv64-3.C | 292 +++++++++++++++++ .../g++.target/riscv/rvv/base/vsbc_vvm-1.C | 292 +++++++++++++++++ .../g++.target/riscv/rvv/base/vsbc_vvm-2.C | 292 +++++++++++++++++ .../g++.target/riscv/rvv/base/vsbc_vvm-3.C | 292 +++++++++++++++++ .../g++.target/riscv/rvv/base/vsbc_vvm_tu-1.C | 292 +++++++++++++++++ .../g++.target/riscv/rvv/base/vsbc_vvm_tu-2.C | 292 +++++++++++++++++ .../g++.target/riscv/rvv/base/vsbc_vvm_tu-3.C | 292 +++++++++++++++++ .../g++.target/riscv/rvv/base/vsbc_vxm_rv32-1.C | 289 +++++++++++++++++ .../g++.target/riscv/rvv/base/vsbc_vxm_rv32-2.C | 289 +++++++++++++++++ .../g++.target/riscv/rvv/base/vsbc_vxm_rv32-3.C | 289 +++++++++++++++++ .../g++.target/riscv/rvv/base/vsbc_vxm_rv64-1.C | 292 +++++++++++++++++ .../g++.target/riscv/rvv/base/vsbc_vxm_rv64-2.C | 292 +++++++++++++++++ .../g++.target/riscv/rvv/base/vsbc_vxm_rv64-3.C | 292 +++++++++++++++++ .../g++.target/riscv/rvv/base/vsbc_vxm_tu_rv32-1.C | 289 +++++++++++++++++ .../g++.target/riscv/rvv/base/vsbc_vxm_tu_rv32-2.C | 289 +++++++++++++++++ .../g++.target/riscv/rvv/base/vsbc_vxm_tu_rv32-3.C | 289 +++++++++++++++++ .../g++.target/riscv/rvv/base/vsbc_vxm_tu_rv64-1.C | 292 +++++++++++++++++ .../g++.target/riscv/rvv/base/vsbc_vxm_tu_rv64-2.C | 292 +++++++++++++++++ .../g++.target/riscv/rvv/base/vsbc_vxm_tu_rv64-3.C | 292 +++++++++++++++++ .../riscv/rvv/base/binop_vx_constraint-121.c | 55 ++++ gcc/testsuite/gcc.target/riscv/rvv/base/vadc-1.c | 27 ++ gcc/testsuite/gcc.target/riscv/rvv/base/vadc-2.c | 48 +++ gcc/testsuite/gcc.target/riscv/rvv/base/vadc-3.c | 78 +++++ gcc/testsuite/gcc.target/riscv/rvv/base/vadc-4.c | 79 +++++ .../gcc.target/riscv/rvv/base/vadc_vvm-1.c | 292 +++++++++++++++++ .../gcc.target/riscv/rvv/base/vadc_vvm-2.c | 292 +++++++++++++++++ .../gcc.target/riscv/rvv/base/vadc_vvm-3.c | 292 +++++++++++++++++ .../gcc.target/riscv/rvv/base/vadc_vvm_tu-1.c | 292 +++++++++++++++++ .../gcc.target/riscv/rvv/base/vadc_vvm_tu-2.c | 292 +++++++++++++++++ .../gcc.target/riscv/rvv/base/vadc_vvm_tu-3.c | 292 +++++++++++++++++ .../gcc.target/riscv/rvv/base/vadc_vxm_rv32-1.c | 289 +++++++++++++++++ .../gcc.target/riscv/rvv/base/vadc_vxm_rv32-2.c | 289 +++++++++++++++++ .../gcc.target/riscv/rvv/base/vadc_vxm_rv32-3.c | 289 +++++++++++++++++ .../gcc.target/riscv/rvv/base/vadc_vxm_rv64-1.c | 292 +++++++++++++++++ .../gcc.target/riscv/rvv/base/vadc_vxm_rv64-2.c | 292 +++++++++++++++++ .../gcc.target/riscv/rvv/base/vadc_vxm_rv64-3.c | 292 +++++++++++++++++ .../gcc.target/riscv/rvv/base/vadc_vxm_tu_rv32-1.c | 289 +++++++++++++++++ .../gcc.target/riscv/rvv/base/vadc_vxm_tu_rv32-2.c | 289 +++++++++++++++++ .../gcc.target/riscv/rvv/base/vadc_vxm_tu_rv32-3.c | 289 +++++++++++++++++ .../gcc.target/riscv/rvv/base/vadc_vxm_tu_rv64-1.c | 292 +++++++++++++++++ .../gcc.target/riscv/rvv/base/vadc_vxm_tu_rv64-2.c | 292 +++++++++++++++++ .../gcc.target/riscv/rvv/base/vadc_vxm_tu_rv64-3.c | 292 +++++++++++++++++ gcc/testsuite/gcc.target/riscv/rvv/base/vsbc-1.c | 27 ++ gcc/testsuite/gcc.target/riscv/rvv/base/vsbc-2.c | 56 ++++ gcc/testsuite/gcc.target/riscv/rvv/base/vsbc-3.c | 77 +++++ gcc/testsuite/gcc.target/riscv/rvv/base/vsbc-4.c | 78 +++++ .../gcc.target/riscv/rvv/base/vsbc_vvm-1.c | 292 +++++++++++++++++ .../gcc.target/riscv/rvv/base/vsbc_vvm-2.c | 292 +++++++++++++++++ .../gcc.target/riscv/rvv/base/vsbc_vvm-3.c | 292 +++++++++++++++++ .../gcc.target/riscv/rvv/base/vsbc_vvm_tu-1.c | 292 +++++++++++++++++ .../gcc.target/riscv/rvv/base/vsbc_vvm_tu-2.c | 292 +++++++++++++++++ .../gcc.target/riscv/rvv/base/vsbc_vvm_tu-3.c | 292 +++++++++++++++++ .../gcc.target/riscv/rvv/base/vsbc_vxm_rv32-1.c | 289 +++++++++++++++++ .../gcc.target/riscv/rvv/base/vsbc_vxm_rv32-2.c | 289 +++++++++++++++++ .../gcc.target/riscv/rvv/base/vsbc_vxm_rv32-3.c | 289 +++++++++++++++++ .../gcc.target/riscv/rvv/base/vsbc_vxm_rv64-1.c | 292 +++++++++++++++++ .../gcc.target/riscv/rvv/base/vsbc_vxm_rv64-2.c | 292 +++++++++++++++++ .../gcc.target/riscv/rvv/base/vsbc_vxm_rv64-3.c | 292 +++++++++++++++++ .../gcc.target/riscv/rvv/base/vsbc_vxm_tu_rv32-1.c | 289 +++++++++++++++++ .../gcc.target/riscv/rvv/base/vsbc_vxm_tu_rv32-2.c | 289 +++++++++++++++++ .../gcc.target/riscv/rvv/base/vsbc_vxm_tu_rv32-3.c | 289 +++++++++++++++++ .../gcc.target/riscv/rvv/base/vsbc_vxm_tu_rv64-1.c | 292 +++++++++++++++++ .../gcc.target/riscv/rvv/base/vsbc_vxm_tu_rv64-2.c | 292 +++++++++++++++++ .../gcc.target/riscv/rvv/base/vsbc_vxm_tu_rv64-3.c | 292 +++++++++++++++++ 92 files changed, 21939 insertions(+), 31 deletions(-) create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadc_vvm-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadc_vvm-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadc_vvm-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadc_vvm_tu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadc_vvm_tu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadc_vvm_tu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadc_vxm_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadc_vxm_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadc_vxm_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadc_vxm_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadc_vxm_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadc_vxm_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadc_vxm_tu_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadc_vxm_tu_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadc_vxm_tu_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadc_vxm_tu_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadc_vxm_tu_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadc_vxm_tu_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsbc_vvm-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsbc_vvm-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsbc_vvm-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsbc_vvm_tu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsbc_vvm_tu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsbc_vvm_tu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsbc_vxm_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsbc_vxm_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsbc_vxm_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsbc_vxm_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsbc_vxm_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsbc_vxm_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsbc_vxm_tu_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsbc_vxm_tu_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsbc_vxm_tu_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsbc_vxm_tu_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsbc_vxm_tu_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsbc_vxm_tu_rv64-3.C create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-121.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadc-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadc-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadc-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadc-4.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadc_vvm-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadc_vvm-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadc_vvm-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadc_vvm_tu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadc_vvm_tu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadc_vvm_tu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadc_vxm_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadc_vxm_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadc_vxm_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadc_vxm_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadc_vxm_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadc_vxm_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadc_vxm_tu_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadc_vxm_tu_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadc_vxm_tu_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadc_vxm_tu_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadc_vxm_tu_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadc_vxm_tu_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsbc-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsbc-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsbc-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsbc-4.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsbc_vvm-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsbc_vvm-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsbc_vvm-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsbc_vvm_tu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsbc_vvm_tu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsbc_vvm_tu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsbc_vxm_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsbc_vxm_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsbc_vxm_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsbc_vxm_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsbc_vxm_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsbc_vxm_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsbc_vxm_tu_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsbc_vxm_tu_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsbc_vxm_tu_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsbc_vxm_tu_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsbc_vxm_tu_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsbc_vxm_tu_rv64-3.c -- To stop receiving notification emails like this one, please contact the administrator of this repository.

1 year, 9 months

[gcc] branch master updated (74595dd5181 -> 316c83b158d)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository gcc. from 74595dd5181 RISC-V: Add vsext C++ API tests new 8340bbad6a1 RISC-V: Add vmulh C/C++ support new 87c557e2696 RISC-V: Add vmulhu.vx C API tests new ce756a1392b RISC-V: Add vmulhu.vv C API tests new f95ada62f3f RISC-V: Add vmulhsu.vx C API tests new 956c0c8c7dc RISC-V: Add vmulhsu.vv C API tests new fa07f9da8b7 RISC-V: Add vmulh.vx C API tests new 9ecdd261f72 RISC-V: Add vmulh.vv C API tests new b9eabfee849 RISC-V: Add vmulhu.vx C++ tests new 5a792199d80 RISC-V: Add vmulhsu.vx C++ API tests new b81d711d189 RISC-V: Add vmulhsu.vv C++ API tests new f18e96e6188 RISC-V: Add vmulh.vx C++ API tests new d88110b07e7 RISC-V: Add vmulh.vv C++ API tests new a1e42094e7a RISC-V: Add integer widening instructions new 9aa6c67dea4 RISC-V: Add vwsubu.wx C API tests new f98b4bc59b8 RISC-V: Add vwsubu.wx C API tests new 9b180754891 RISC-V: Add vwsubu.vx C API tests new 8aa1e133b12 RISC-V: Add vwsubu.vv C API tests new 931b3d88313 RISC-V: Add vwsub.wx C API tests new 14ac33c8e03 RISC-V: Add vwsub.wv C API tests new 524e491ab53 RISC-V: Add vwsub.vx C API tests new 2a2ab19d559 RISC-V: Add vwsub.vv C API tests new fcbe69a096a RISC-V: Add vwmulu C API tests new 697a877279b RISC-V: Add vwmulsu C API tests new ee4f91db8ee RISC-V: Add vwmul C api tests new 011ec88dd2b RISC-V: Add vwcvt C API test new f14f44d92f6 RISC-V: Add vwaddu.w C API tests new 2daeb10c609 RISC-V: Add vwaddu.v C API tests new 7df7cbaaf5e RISC-V: Add vwadd.w C API tests new c12ea7136ad RISC-V: Add vwadd.v C API tests new 345b2aa4eb3 RISC-V: Add constraint tests new 8532ae57f30 RISC-V: Add vwsubu.w C++ api TETS new 0fca6d1ac50 RISC-V: Add vwsubu.v C++ API test new b406b86cad2 RISC-V: Add vwsub.w C++ api TESTS new c95bc128c05 RISC-V: Add vwsub.v C++ API tests new ba839fb84bc RISC-V: Add vwmulu C++ API tests new 307241cbaa9 RISC-V: Add vwmulsu.v C++ API tests new 7d010731e8b RISC-V: Add vwmul.v C++ api TETS new 98767d253c1 RISC-V: Add vwcvt C++ api test new b840dad84da RISC-V: Add vwaddu.w c++ API TESTS new 0006e578d0a RISC-V: Add vwaddu.v C++ API tests new ccfaa507361 RISC-V: Add vwadd.w C++ API tests new 316c83b158d RISC-V: Add vwadd v C++ api test The 42 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: gcc/common/config/riscv/riscv-common.cc | 1 + gcc/config/riscv/riscv-vector-builtins-bases.cc | 102 +++++++ gcc/config/riscv/riscv-vector-builtins-bases.h | 13 + .../riscv/riscv-vector-builtins-functions.def | 30 ++ gcc/config/riscv/riscv-vector-builtins-shapes.cc | 30 +- gcc/config/riscv/riscv-vector-builtins-shapes.h | 1 + gcc/config/riscv/riscv-vector-builtins-types.def | 62 ++++ gcc/config/riscv/riscv-vector-builtins.cc | 244 +++++++++++++++ gcc/config/riscv/riscv-vector-builtins.def | 2 +- gcc/config/riscv/riscv-vector-builtins.h | 6 + gcc/config/riscv/riscv-vsetvl.cc | 40 +++ gcc/config/riscv/riscv.h | 3 - gcc/config/riscv/riscv.opt | 2 + gcc/config/riscv/vector-iterators.md | 30 ++ gcc/config/riscv/vector.md | 333 ++++++++++++++++++++- .../g++.target/riscv/rvv/base/vmulh_vv-1.C | 314 +++++++++++++++++++ .../g++.target/riscv/rvv/base/vmulh_vv-2.C | 314 +++++++++++++++++++ .../g++.target/riscv/rvv/base/vmulh_vv-3.C | 314 +++++++++++++++++++ .../g++.target/riscv/rvv/base/vmulh_vv_mu-1.C | 160 ++++++++++ .../g++.target/riscv/rvv/base/vmulh_vv_mu-2.C | 160 ++++++++++ .../g++.target/riscv/rvv/base/vmulh_vv_mu-3.C | 160 ++++++++++ .../g++.target/riscv/rvv/base/vmulh_vv_tu-1.C | 160 ++++++++++ .../g++.target/riscv/rvv/base/vmulh_vv_tu-2.C | 160 ++++++++++ .../g++.target/riscv/rvv/base/vmulh_vv_tu-3.C | 160 ++++++++++ .../g++.target/riscv/rvv/base/vmulh_vv_tum-1.C | 160 ++++++++++ .../g++.target/riscv/rvv/base/vmulh_vv_tum-2.C | 160 ++++++++++ .../g++.target/riscv/rvv/base/vmulh_vv_tum-3.C | 160 ++++++++++ .../g++.target/riscv/rvv/base/vmulh_vv_tumu-1.C | 160 ++++++++++ .../g++.target/riscv/rvv/base/vmulh_vv_tumu-2.C | 160 ++++++++++ .../g++.target/riscv/rvv/base/vmulh_vv_tumu-3.C | 160 ++++++++++ .../g++.target/riscv/rvv/base/vmulh_vx_mu_rv32-1.C | 157 ++++++++++ .../g++.target/riscv/rvv/base/vmulh_vx_mu_rv32-2.C | 157 ++++++++++ .../g++.target/riscv/rvv/base/vmulh_vx_mu_rv32-3.C | 157 ++++++++++ .../g++.target/riscv/rvv/base/vmulh_vx_mu_rv64-1.C | 160 ++++++++++ .../g++.target/riscv/rvv/base/vmulh_vx_mu_rv64-2.C | 160 ++++++++++ .../g++.target/riscv/rvv/base/vmulh_vx_mu_rv64-3.C | 160 ++++++++++ .../g++.target/riscv/rvv/base/vmulh_vx_rv32-1.C | 308 +++++++++++++++++++ .../g++.target/riscv/rvv/base/vmulh_vx_rv32-2.C | 308 +++++++++++++++++++ .../g++.target/riscv/rvv/base/vmulh_vx_rv32-3.C | 308 +++++++++++++++++++ .../g++.target/riscv/rvv/base/vmulh_vx_rv64-1.C | 314 +++++++++++++++++++ .../g++.target/riscv/rvv/base/vmulh_vx_rv64-2.C | 314 +++++++++++++++++++ .../g++.target/riscv/rvv/base/vmulh_vx_rv64-3.C | 314 +++++++++++++++++++ .../g++.target/riscv/rvv/base/vmulh_vx_tu_rv32-1.C | 157 ++++++++++ .../g++.target/riscv/rvv/base/vmulh_vx_tu_rv32-2.C | 157 ++++++++++ .../g++.target/riscv/rvv/base/vmulh_vx_tu_rv32-3.C | 157 ++++++++++ .../g++.target/riscv/rvv/base/vmulh_vx_tu_rv64-1.C | 160 ++++++++++ .../g++.target/riscv/rvv/base/vmulh_vx_tu_rv64-2.C | 160 ++++++++++ .../g++.target/riscv/rvv/base/vmulh_vx_tu_rv64-3.C | 160 ++++++++++ .../riscv/rvv/base/vmulh_vx_tum_rv32-1.C | 157 ++++++++++ .../riscv/rvv/base/vmulh_vx_tum_rv32-2.C | 157 ++++++++++ .../riscv/rvv/base/vmulh_vx_tum_rv32-3.C | 157 ++++++++++ .../riscv/rvv/base/vmulh_vx_tum_rv64-1.C | 160 ++++++++++ .../riscv/rvv/base/vmulh_vx_tum_rv64-2.C | 160 ++++++++++ .../riscv/rvv/base/vmulh_vx_tum_rv64-3.C | 160 ++++++++++ .../riscv/rvv/base/vmulh_vx_tumu_rv32-1.C | 157 ++++++++++ .../riscv/rvv/base/vmulh_vx_tumu_rv32-2.C | 157 ++++++++++ .../riscv/rvv/base/vmulh_vx_tumu_rv32-3.C | 157 ++++++++++ .../riscv/rvv/base/vmulh_vx_tumu_rv64-1.C | 160 ++++++++++ .../riscv/rvv/base/vmulh_vx_tumu_rv64-2.C | 160 ++++++++++ .../riscv/rvv/base/vmulh_vx_tumu_rv64-3.C | 160 ++++++++++ .../g++.target/riscv/rvv/base/vmulhsu_vv-1.C | 314 +++++++++++++++++++ .../g++.target/riscv/rvv/base/vmulhsu_vv-2.C | 314 +++++++++++++++++++ .../g++.target/riscv/rvv/base/vmulhsu_vv-3.C | 314 +++++++++++++++++++ .../g++.target/riscv/rvv/base/vmulhsu_vv_mu-1.C | 160 ++++++++++ .../g++.target/riscv/rvv/base/vmulhsu_vv_mu-2.C | 160 ++++++++++ .../g++.target/riscv/rvv/base/vmulhsu_vv_mu-3.C | 160 ++++++++++ .../g++.target/riscv/rvv/base/vmulhsu_vv_tu-1.C | 160 ++++++++++ .../g++.target/riscv/rvv/base/vmulhsu_vv_tu-2.C | 160 ++++++++++ .../g++.target/riscv/rvv/base/vmulhsu_vv_tu-3.C | 160 ++++++++++ .../g++.target/riscv/rvv/base/vmulhsu_vv_tum-1.C | 160 ++++++++++ .../g++.target/riscv/rvv/base/vmulhsu_vv_tum-2.C | 160 ++++++++++ .../g++.target/riscv/rvv/base/vmulhsu_vv_tum-3.C | 160 ++++++++++ .../g++.target/riscv/rvv/base/vmulhsu_vv_tumu-1.C | 160 ++++++++++ .../g++.target/riscv/rvv/base/vmulhsu_vv_tumu-2.C | 160 ++++++++++ .../g++.target/riscv/rvv/base/vmulhsu_vv_tumu-3.C | 160 ++++++++++ .../riscv/rvv/base/vmulhsu_vx_mu_rv32-1.C | 157 ++++++++++ .../riscv/rvv/base/vmulhsu_vx_mu_rv32-2.C | 157 ++++++++++ .../riscv/rvv/base/vmulhsu_vx_mu_rv32-3.C | 157 ++++++++++ .../riscv/rvv/base/vmulhsu_vx_mu_rv64-1.C | 160 ++++++++++ .../riscv/rvv/base/vmulhsu_vx_mu_rv64-2.C | 160 ++++++++++ .../riscv/rvv/base/vmulhsu_vx_mu_rv64-3.C | 160 ++++++++++ .../g++.target/riscv/rvv/base/vmulhsu_vx_rv32-1.C | 308 +++++++++++++++++++ .../g++.target/riscv/rvv/base/vmulhsu_vx_rv32-2.C | 308 +++++++++++++++++++ .../g++.target/riscv/rvv/base/vmulhsu_vx_rv32-3.C | 308 +++++++++++++++++++ .../g++.target/riscv/rvv/base/vmulhsu_vx_rv64-1.C | 314 +++++++++++++++++++ .../g++.target/riscv/rvv/base/vmulhsu_vx_rv64-2.C | 314 +++++++++++++++++++ .../g++.target/riscv/rvv/base/vmulhsu_vx_rv64-3.C | 314 +++++++++++++++++++ .../riscv/rvv/base/vmulhsu_vx_tu_rv32-1.C | 157 ++++++++++ .../riscv/rvv/base/vmulhsu_vx_tu_rv32-2.C | 157 ++++++++++ .../riscv/rvv/base/vmulhsu_vx_tu_rv32-3.C | 157 ++++++++++ .../riscv/rvv/base/vmulhsu_vx_tu_rv64-1.C | 160 ++++++++++ .../riscv/rvv/base/vmulhsu_vx_tu_rv64-2.C | 160 ++++++++++ .../riscv/rvv/base/vmulhsu_vx_tu_rv64-3.C | 160 ++++++++++ .../riscv/rvv/base/vmulhsu_vx_tum_rv32-1.C | 157 ++++++++++ .../riscv/rvv/base/vmulhsu_vx_tum_rv32-2.C | 157 ++++++++++ .../riscv/rvv/base/vmulhsu_vx_tum_rv32-3.C | 157 ++++++++++ .../riscv/rvv/base/vmulhsu_vx_tum_rv64-1.C | 160 ++++++++++ .../riscv/rvv/base/vmulhsu_vx_tum_rv64-2.C | 160 ++++++++++ .../riscv/rvv/base/vmulhsu_vx_tum_rv64-3.C | 160 ++++++++++ .../riscv/rvv/base/vmulhsu_vx_tumu_rv32-1.C | 157 ++++++++++ .../riscv/rvv/base/vmulhsu_vx_tumu_rv32-2.C | 157 ++++++++++ .../riscv/rvv/base/vmulhsu_vx_tumu_rv32-3.C | 157 ++++++++++ .../riscv/rvv/base/vmulhsu_vx_tumu_rv64-1.C | 160 ++++++++++ .../riscv/rvv/base/vmulhsu_vx_tumu_rv64-2.C | 160 ++++++++++ .../riscv/rvv/base/vmulhsu_vx_tumu_rv64-3.C | 160 ++++++++++ .../riscv/rvv/base/vmulhu_vx_mu_rv32-1.C | 157 ++++++++++ .../riscv/rvv/base/vmulhu_vx_mu_rv32-2.C | 157 ++++++++++ .../riscv/rvv/base/vmulhu_vx_mu_rv32-3.C | 157 ++++++++++ .../riscv/rvv/base/vmulhu_vx_mu_rv64-1.C | 160 ++++++++++ .../riscv/rvv/base/vmulhu_vx_mu_rv64-2.C | 160 ++++++++++ .../riscv/rvv/base/vmulhu_vx_mu_rv64-3.C | 160 ++++++++++ .../g++.target/riscv/rvv/base/vmulhu_vx_rv32-1.C | 308 +++++++++++++++++++ .../g++.target/riscv/rvv/base/vmulhu_vx_rv32-2.C | 308 +++++++++++++++++++ .../g++.target/riscv/rvv/base/vmulhu_vx_rv32-3.C | 308 +++++++++++++++++++ .../g++.target/riscv/rvv/base/vmulhu_vx_rv64-1.C | 314 +++++++++++++++++++ .../g++.target/riscv/rvv/base/vmulhu_vx_rv64-2.C | 314 +++++++++++++++++++ .../g++.target/riscv/rvv/base/vmulhu_vx_rv64-3.C | 314 +++++++++++++++++++ .../riscv/rvv/base/vmulhu_vx_tu_rv32-1.C | 157 ++++++++++ .../riscv/rvv/base/vmulhu_vx_tu_rv32-2.C | 157 ++++++++++ .../riscv/rvv/base/vmulhu_vx_tu_rv32-3.C | 157 ++++++++++ .../riscv/rvv/base/vmulhu_vx_tu_rv64-1.C | 160 ++++++++++ .../riscv/rvv/base/vmulhu_vx_tu_rv64-2.C | 160 ++++++++++ .../riscv/rvv/base/vmulhu_vx_tu_rv64-3.C | 160 ++++++++++ .../riscv/rvv/base/vmulhu_vx_tum_rv32-1.C | 157 ++++++++++ .../riscv/rvv/base/vmulhu_vx_tum_rv32-2.C | 157 ++++++++++ .../riscv/rvv/base/vmulhu_vx_tum_rv32-3.C | 157 ++++++++++ .../riscv/rvv/base/vmulhu_vx_tum_rv64-1.C | 160 ++++++++++ .../riscv/rvv/base/vmulhu_vx_tum_rv64-2.C | 160 ++++++++++ .../riscv/rvv/base/vmulhu_vx_tum_rv64-3.C | 160 ++++++++++ .../riscv/rvv/base/vmulhu_vx_tumu_rv32-1.C | 157 ++++++++++ .../riscv/rvv/base/vmulhu_vx_tumu_rv32-2.C | 157 ++++++++++ .../riscv/rvv/base/vmulhu_vx_tumu_rv32-3.C | 157 ++++++++++ .../riscv/rvv/base/vmulhu_vx_tumu_rv64-1.C | 160 ++++++++++ .../riscv/rvv/base/vmulhu_vx_tumu_rv64-2.C | 160 ++++++++++ .../riscv/rvv/base/vmulhu_vx_tumu_rv64-3.C | 160 ++++++++++ .../g++.target/riscv/rvv/base/vwadd_vv-1.C | 216 +++++++++++++ .../g++.target/riscv/rvv/base/vwadd_vv-2.C | 216 +++++++++++++ .../g++.target/riscv/rvv/base/vwadd_vv-3.C | 216 +++++++++++++ .../g++.target/riscv/rvv/base/vwadd_vv_mu-1.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwadd_vv_mu-2.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwadd_vv_mu-3.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwadd_vv_tu-1.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwadd_vv_tu-2.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwadd_vv_tu-3.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwadd_vv_tum-1.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwadd_vv_tum-2.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwadd_vv_tum-3.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwadd_vv_tumu-1.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwadd_vv_tumu-2.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwadd_vv_tumu-3.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwadd_vx-1.C | 216 +++++++++++++ .../g++.target/riscv/rvv/base/vwadd_vx-2.C | 216 +++++++++++++ .../g++.target/riscv/rvv/base/vwadd_vx-3.C | 216 +++++++++++++ .../g++.target/riscv/rvv/base/vwadd_vx_mu-1.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwadd_vx_mu-2.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwadd_vx_mu-3.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwadd_vx_tu-1.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwadd_vx_tu-2.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwadd_vx_tu-3.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwadd_vx_tum-1.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwadd_vx_tum-2.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwadd_vx_tum-3.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwadd_vx_tumu-1.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwadd_vx_tumu-2.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwadd_vx_tumu-3.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwadd_wv-1.C | 216 +++++++++++++ .../g++.target/riscv/rvv/base/vwadd_wv-2.C | 216 +++++++++++++ .../g++.target/riscv/rvv/base/vwadd_wv-3.C | 216 +++++++++++++ .../g++.target/riscv/rvv/base/vwadd_wv_mu-1.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwadd_wv_mu-2.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwadd_wv_mu-3.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwadd_wv_tu-1.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwadd_wv_tu-2.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwadd_wv_tu-3.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwadd_wv_tum-1.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwadd_wv_tum-2.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwadd_wv_tum-3.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwadd_wv_tumu-1.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwadd_wv_tumu-2.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwadd_wv_tumu-3.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwadd_wx-1.C | 216 +++++++++++++ .../g++.target/riscv/rvv/base/vwadd_wx-2.C | 216 +++++++++++++ .../g++.target/riscv/rvv/base/vwadd_wx-3.C | 216 +++++++++++++ .../g++.target/riscv/rvv/base/vwadd_wx_mu-1.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwadd_wx_mu-2.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwadd_wx_mu-3.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwadd_wx_tu-1.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwadd_wx_tu-2.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwadd_wx_tu-3.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwadd_wx_tum-1.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwadd_wx_tum-2.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwadd_wx_tum-3.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwadd_wx_tumu-1.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwadd_wx_tumu-2.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwadd_wx_tumu-3.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwaddu_vv-1.C | 216 +++++++++++++ .../g++.target/riscv/rvv/base/vwaddu_vv-2.C | 216 +++++++++++++ .../g++.target/riscv/rvv/base/vwaddu_vv-3.C | 216 +++++++++++++ .../g++.target/riscv/rvv/base/vwaddu_vv_mu-1.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwaddu_vv_mu-2.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwaddu_vv_mu-3.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwaddu_vv_tu-1.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwaddu_vv_tu-2.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwaddu_vv_tu-3.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwaddu_vv_tum-1.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwaddu_vv_tum-2.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwaddu_vv_tum-3.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwaddu_vv_tumu-1.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwaddu_vv_tumu-2.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwaddu_vv_tumu-3.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwaddu_vx-1.C | 216 +++++++++++++ .../g++.target/riscv/rvv/base/vwaddu_vx-2.C | 216 +++++++++++++ .../g++.target/riscv/rvv/base/vwaddu_vx-3.C | 216 +++++++++++++ .../g++.target/riscv/rvv/base/vwaddu_vx_mu-1.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwaddu_vx_mu-2.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwaddu_vx_mu-3.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwaddu_vx_tu-1.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwaddu_vx_tu-2.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwaddu_vx_tu-3.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwaddu_vx_tum-1.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwaddu_vx_tum-2.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwaddu_vx_tum-3.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwaddu_vx_tumu-1.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwaddu_vx_tumu-2.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwaddu_vx_tumu-3.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwaddu_wv-1.C | 216 +++++++++++++ .../g++.target/riscv/rvv/base/vwaddu_wv-2.C | 216 +++++++++++++ .../g++.target/riscv/rvv/base/vwaddu_wv-3.C | 216 +++++++++++++ .../g++.target/riscv/rvv/base/vwaddu_wv_mu-1.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwaddu_wv_mu-2.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwaddu_wv_mu-3.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwaddu_wv_tu-1.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwaddu_wv_tu-2.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwaddu_wv_tu-3.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwaddu_wv_tum-1.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwaddu_wv_tum-2.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwaddu_wv_tum-3.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwaddu_wv_tumu-1.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwaddu_wv_tumu-2.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwaddu_wv_tumu-3.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwaddu_wx-1.C | 216 +++++++++++++ .../g++.target/riscv/rvv/base/vwaddu_wx-2.C | 216 +++++++++++++ .../g++.target/riscv/rvv/base/vwaddu_wx-3.C | 216 +++++++++++++ .../g++.target/riscv/rvv/base/vwaddu_wx_mu-1.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwaddu_wx_mu-2.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwaddu_wx_mu-3.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwaddu_wx_tu-1.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwaddu_wx_tu-2.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwaddu_wx_tu-3.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwaddu_wx_tum-1.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwaddu_wx_tum-2.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwaddu_wx_tum-3.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwaddu_wx_tumu-1.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwaddu_wx_tumu-2.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwaddu_wx_tumu-3.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwcvt_x-1.C | 216 +++++++++++++ .../g++.target/riscv/rvv/base/vwcvt_x-2.C | 216 +++++++++++++ .../g++.target/riscv/rvv/base/vwcvt_x-3.C | 216 +++++++++++++ .../g++.target/riscv/rvv/base/vwcvt_x_mu-1.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwcvt_x_mu-2.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwcvt_x_mu-3.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwcvt_x_tu-1.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwcvt_x_tu-2.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwcvt_x_tu-3.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwcvt_x_tum-1.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwcvt_x_tum-2.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwcvt_x_tum-3.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwcvt_x_tumu-1.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwcvt_x_tumu-2.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwcvt_x_tumu-3.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwcvtu_x-1.C | 216 +++++++++++++ .../g++.target/riscv/rvv/base/vwcvtu_x-2.C | 216 +++++++++++++ .../g++.target/riscv/rvv/base/vwcvtu_x-3.C | 216 +++++++++++++ .../g++.target/riscv/rvv/base/vwcvtu_x_mu-1.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwcvtu_x_mu-2.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwcvtu_x_mu-3.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwcvtu_x_tu-1.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwcvtu_x_tu-2.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwcvtu_x_tu-3.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwcvtu_x_tum-1.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwcvtu_x_tum-2.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwcvtu_x_tum-3.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwcvtu_x_tumu-1.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwcvtu_x_tumu-2.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwcvtu_x_tumu-3.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwmul_vv-1.C | 216 +++++++++++++ .../g++.target/riscv/rvv/base/vwmul_vv-2.C | 216 +++++++++++++ .../g++.target/riscv/rvv/base/vwmul_vv-3.C | 216 +++++++++++++ .../g++.target/riscv/rvv/base/vwmul_vv_mu-1.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwmul_vv_mu-2.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwmul_vv_mu-3.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwmul_vv_tu-1.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwmul_vv_tu-2.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwmul_vv_tu-3.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwmul_vv_tum-1.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwmul_vv_tum-2.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwmul_vv_tum-3.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwmul_vv_tumu-1.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwmul_vv_tumu-2.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwmul_vv_tumu-3.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwmul_vx-1.C | 216 +++++++++++++ .../g++.target/riscv/rvv/base/vwmul_vx-2.C | 216 +++++++++++++ .../g++.target/riscv/rvv/base/vwmul_vx-3.C | 216 +++++++++++++ .../g++.target/riscv/rvv/base/vwmul_vx_mu-1.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwmul_vx_mu-2.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwmul_vx_mu-3.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwmul_vx_tu-1.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwmul_vx_tu-2.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwmul_vx_tu-3.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwmul_vx_tum-1.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwmul_vx_tum-2.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwmul_vx_tum-3.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwmul_vx_tumu-1.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwmul_vx_tumu-2.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwmul_vx_tumu-3.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwmulsu_vv-1.C | 216 +++++++++++++ .../g++.target/riscv/rvv/base/vwmulsu_vv-2.C | 216 +++++++++++++ .../g++.target/riscv/rvv/base/vwmulsu_vv-3.C | 216 +++++++++++++ .../g++.target/riscv/rvv/base/vwmulsu_vv_mu-1.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwmulsu_vv_mu-2.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwmulsu_vv_mu-3.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwmulsu_vv_tu-1.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwmulsu_vv_tu-2.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwmulsu_vv_tu-3.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwmulsu_vv_tum-1.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwmulsu_vv_tum-2.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwmulsu_vv_tum-3.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwmulsu_vv_tumu-1.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwmulsu_vv_tumu-2.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwmulsu_vv_tumu-3.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwmulsu_vx-1.C | 216 +++++++++++++ .../g++.target/riscv/rvv/base/vwmulsu_vx-2.C | 216 +++++++++++++ .../g++.target/riscv/rvv/base/vwmulsu_vx-3.C | 216 +++++++++++++ .../g++.target/riscv/rvv/base/vwmulsu_vx_mu-1.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwmulsu_vx_mu-2.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwmulsu_vx_mu-3.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwmulsu_vx_tu-1.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwmulsu_vx_tu-2.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwmulsu_vx_tu-3.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwmulsu_vx_tum-1.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwmulsu_vx_tum-2.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwmulsu_vx_tum-3.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwmulsu_vx_tumu-1.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwmulsu_vx_tumu-2.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwmulsu_vx_tumu-3.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwmulu_vv-1.C | 216 +++++++++++++ .../g++.target/riscv/rvv/base/vwmulu_vv-2.C | 216 +++++++++++++ .../g++.target/riscv/rvv/base/vwmulu_vv-3.C | 216 +++++++++++++ .../g++.target/riscv/rvv/base/vwmulu_vv_mu-1.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwmulu_vv_mu-2.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwmulu_vv_mu-3.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwmulu_vv_tu-1.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwmulu_vv_tu-2.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwmulu_vv_tu-3.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwmulu_vv_tum-1.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwmulu_vv_tum-2.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwmulu_vv_tum-3.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwmulu_vv_tumu-1.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwmulu_vv_tumu-2.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwmulu_vv_tumu-3.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwmulu_vx-1.C | 216 +++++++++++++ .../g++.target/riscv/rvv/base/vwmulu_vx-2.C | 216 +++++++++++++ .../g++.target/riscv/rvv/base/vwmulu_vx-3.C | 216 +++++++++++++ .../g++.target/riscv/rvv/base/vwmulu_vx_mu-1.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwmulu_vx_mu-2.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwmulu_vx_mu-3.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwmulu_vx_tu-1.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwmulu_vx_tu-2.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwmulu_vx_tu-3.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwmulu_vx_tum-1.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwmulu_vx_tum-2.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwmulu_vx_tum-3.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwmulu_vx_tumu-1.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwmulu_vx_tumu-2.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwmulu_vx_tumu-3.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwsub_vv-1.C | 216 +++++++++++++ .../g++.target/riscv/rvv/base/vwsub_vv-2.C | 216 +++++++++++++ .../g++.target/riscv/rvv/base/vwsub_vv-3.C | 216 +++++++++++++ .../g++.target/riscv/rvv/base/vwsub_vv_mu-1.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwsub_vv_mu-2.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwsub_vv_mu-3.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwsub_vv_tu-1.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwsub_vv_tu-2.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwsub_vv_tu-3.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwsub_vv_tum-1.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwsub_vv_tum-2.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwsub_vv_tum-3.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwsub_vv_tumu-1.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwsub_vv_tumu-2.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwsub_vv_tumu-3.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwsub_vx-1.C | 216 +++++++++++++ .../g++.target/riscv/rvv/base/vwsub_vx-2.C | 216 +++++++++++++ .../g++.target/riscv/rvv/base/vwsub_vx-3.C | 216 +++++++++++++ .../g++.target/riscv/rvv/base/vwsub_vx_mu-1.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwsub_vx_mu-2.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwsub_vx_mu-3.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwsub_vx_tu-1.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwsub_vx_tu-2.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwsub_vx_tu-3.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwsub_vx_tum-1.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwsub_vx_tum-2.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwsub_vx_tum-3.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwsub_vx_tumu-1.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwsub_vx_tumu-2.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwsub_vx_tumu-3.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwsub_wv-1.C | 216 +++++++++++++ .../g++.target/riscv/rvv/base/vwsub_wv-2.C | 216 +++++++++++++ .../g++.target/riscv/rvv/base/vwsub_wv-3.C | 216 +++++++++++++ .../g++.target/riscv/rvv/base/vwsub_wv_mu-1.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwsub_wv_mu-2.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwsub_wv_mu-3.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwsub_wv_tu-1.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwsub_wv_tu-2.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwsub_wv_tu-3.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwsub_wv_tum-1.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwsub_wv_tum-2.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwsub_wv_tum-3.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwsub_wv_tumu-1.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwsub_wv_tumu-2.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwsub_wv_tumu-3.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwsub_wx-1.C | 216 +++++++++++++ .../g++.target/riscv/rvv/base/vwsub_wx-2.C | 216 +++++++++++++ .../g++.target/riscv/rvv/base/vwsub_wx-3.C | 216 +++++++++++++ .../g++.target/riscv/rvv/base/vwsub_wx_mu-1.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwsub_wx_mu-2.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwsub_wx_mu-3.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwsub_wx_tu-1.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwsub_wx_tu-2.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwsub_wx_tu-3.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwsub_wx_tum-1.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwsub_wx_tum-2.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwsub_wx_tum-3.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwsub_wx_tumu-1.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwsub_wx_tumu-2.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwsub_wx_tumu-3.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwsubu_vv-1.C | 216 +++++++++++++ .../g++.target/riscv/rvv/base/vwsubu_vv-2.C | 216 +++++++++++++ .../g++.target/riscv/rvv/base/vwsubu_vv-3.C | 216 +++++++++++++ .../g++.target/riscv/rvv/base/vwsubu_vv_mu-1.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwsubu_vv_mu-2.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwsubu_vv_mu-3.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwsubu_vv_tu-1.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwsubu_vv_tu-2.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwsubu_vv_tu-3.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwsubu_vv_tum-1.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwsubu_vv_tum-2.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwsubu_vv_tum-3.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwsubu_vv_tumu-1.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwsubu_vv_tumu-2.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwsubu_vv_tumu-3.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwsubu_vx-1.C | 216 +++++++++++++ .../g++.target/riscv/rvv/base/vwsubu_vx-2.C | 216 +++++++++++++ .../g++.target/riscv/rvv/base/vwsubu_vx-3.C | 216 +++++++++++++ .../g++.target/riscv/rvv/base/vwsubu_vx_mu-1.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwsubu_vx_mu-2.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwsubu_vx_mu-3.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwsubu_vx_tu-1.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwsubu_vx_tu-2.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwsubu_vx_tu-3.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwsubu_vx_tum-1.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwsubu_vx_tum-2.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwsubu_vx_tum-3.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwsubu_vx_tumu-1.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwsubu_vx_tumu-2.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwsubu_vx_tumu-3.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwsubu_wv-1.C | 216 +++++++++++++ .../g++.target/riscv/rvv/base/vwsubu_wv-2.C | 216 +++++++++++++ .../g++.target/riscv/rvv/base/vwsubu_wv-3.C | 216 +++++++++++++ .../g++.target/riscv/rvv/base/vwsubu_wv_mu-1.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwsubu_wv_mu-2.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwsubu_wv_mu-3.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwsubu_wv_tu-1.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwsubu_wv_tu-2.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwsubu_wv_tu-3.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwsubu_wv_tum-1.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwsubu_wv_tum-2.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwsubu_wv_tum-3.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwsubu_wv_tumu-1.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwsubu_wv_tumu-2.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwsubu_wv_tumu-3.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwsubu_wx-1.C | 216 +++++++++++++ .../g++.target/riscv/rvv/base/vwsubu_wx-2.C | 216 +++++++++++++ .../g++.target/riscv/rvv/base/vwsubu_wx-3.C | 216 +++++++++++++ .../g++.target/riscv/rvv/base/vwsubu_wx_mu-1.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwsubu_wx_mu-2.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwsubu_wx_mu-3.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwsubu_wx_tu-1.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwsubu_wx_tu-2.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwsubu_wx_tu-3.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwsubu_wx_tum-1.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwsubu_wx_tum-2.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwsubu_wx_tum-3.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwsubu_wx_tumu-1.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwsubu_wx_tumu-2.C | 111 +++++++ .../g++.target/riscv/rvv/base/vwsubu_wx_tumu-3.C | 111 +++++++ .../riscv/rvv/base/binop_vx_constraint-120.c | 16 + .../gcc.target/riscv/rvv/base/vmulh_vv-1.c | 160 ++++++++++ .../gcc.target/riscv/rvv/base/vmulh_vv-2.c | 160 ++++++++++ .../gcc.target/riscv/rvv/base/vmulh_vv-3.c | 160 ++++++++++ .../gcc.target/riscv/rvv/base/vmulh_vv_m-1.c | 160 ++++++++++ .../gcc.target/riscv/rvv/base/vmulh_vv_m-2.c | 160 ++++++++++ .../gcc.target/riscv/rvv/base/vmulh_vv_m-3.c | 160 ++++++++++ .../gcc.target/riscv/rvv/base/vmulh_vv_mu-1.c | 160 ++++++++++ .../gcc.target/riscv/rvv/base/vmulh_vv_mu-2.c | 160 ++++++++++ .../gcc.target/riscv/rvv/base/vmulh_vv_mu-3.c | 160 ++++++++++ .../gcc.target/riscv/rvv/base/vmulh_vv_tu-1.c | 160 ++++++++++ .../gcc.target/riscv/rvv/base/vmulh_vv_tu-2.c | 160 ++++++++++ .../gcc.target/riscv/rvv/base/vmulh_vv_tu-3.c | 160 ++++++++++ .../gcc.target/riscv/rvv/base/vmulh_vv_tum-1.c | 160 ++++++++++ .../gcc.target/riscv/rvv/base/vmulh_vv_tum-2.c | 160 ++++++++++ .../gcc.target/riscv/rvv/base/vmulh_vv_tum-3.c | 160 ++++++++++ .../gcc.target/riscv/rvv/base/vmulh_vv_tumu-1.c | 160 ++++++++++ .../gcc.target/riscv/rvv/base/vmulh_vv_tumu-2.c | 160 ++++++++++ .../gcc.target/riscv/rvv/base/vmulh_vv_tumu-3.c | 160 ++++++++++ .../gcc.target/riscv/rvv/base/vmulh_vx_m_rv32-1.c | 157 ++++++++++ .../gcc.target/riscv/rvv/base/vmulh_vx_m_rv32-2.c | 157 ++++++++++ .../gcc.target/riscv/rvv/base/vmulh_vx_m_rv32-3.c | 157 ++++++++++ .../gcc.target/riscv/rvv/base/vmulh_vx_m_rv64-1.c | 160 ++++++++++ .../gcc.target/riscv/rvv/base/vmulh_vx_m_rv64-2.c | 160 ++++++++++ .../gcc.target/riscv/rvv/base/vmulh_vx_m_rv64-3.c | 160 ++++++++++ .../gcc.target/riscv/rvv/base/vmulh_vx_mu_rv32-1.c | 157 ++++++++++ .../gcc.target/riscv/rvv/base/vmulh_vx_mu_rv32-2.c | 157 ++++++++++ .../gcc.target/riscv/rvv/base/vmulh_vx_mu_rv32-3.c | 157 ++++++++++ .../gcc.target/riscv/rvv/base/vmulh_vx_mu_rv64-1.c | 160 ++++++++++ .../gcc.target/riscv/rvv/base/vmulh_vx_mu_rv64-2.c | 160 ++++++++++ .../gcc.target/riscv/rvv/base/vmulh_vx_mu_rv64-3.c | 160 ++++++++++ .../gcc.target/riscv/rvv/base/vmulh_vx_rv32-1.c | 157 ++++++++++ .../gcc.target/riscv/rvv/base/vmulh_vx_rv32-2.c | 157 ++++++++++ .../gcc.target/riscv/rvv/base/vmulh_vx_rv32-3.c | 157 ++++++++++ .../gcc.target/riscv/rvv/base/vmulh_vx_rv64-1.c | 160 ++++++++++ .../gcc.target/riscv/rvv/base/vmulh_vx_rv64-2.c | 160 ++++++++++ .../gcc.target/riscv/rvv/base/vmulh_vx_rv64-3.c | 160 ++++++++++ .../gcc.target/riscv/rvv/base/vmulh_vx_tu_rv32-1.c | 157 ++++++++++ .../gcc.target/riscv/rvv/base/vmulh_vx_tu_rv32-2.c | 157 ++++++++++ .../gcc.target/riscv/rvv/base/vmulh_vx_tu_rv32-3.c | 157 ++++++++++ .../gcc.target/riscv/rvv/base/vmulh_vx_tu_rv64-1.c | 160 ++++++++++ .../gcc.target/riscv/rvv/base/vmulh_vx_tu_rv64-2.c | 160 ++++++++++ .../gcc.target/riscv/rvv/base/vmulh_vx_tu_rv64-3.c | 160 ++++++++++ .../riscv/rvv/base/vmulh_vx_tum_rv32-1.c | 157 ++++++++++ .../riscv/rvv/base/vmulh_vx_tum_rv32-2.c | 157 ++++++++++ .../riscv/rvv/base/vmulh_vx_tum_rv32-3.c | 157 ++++++++++ .../riscv/rvv/base/vmulh_vx_tum_rv64-1.c | 160 ++++++++++ .../riscv/rvv/base/vmulh_vx_tum_rv64-2.c | 160 ++++++++++ .../riscv/rvv/base/vmulh_vx_tum_rv64-3.c | 160 ++++++++++ .../riscv/rvv/base/vmulh_vx_tumu_rv32-1.c | 157 ++++++++++ .../riscv/rvv/base/vmulh_vx_tumu_rv32-2.c | 157 ++++++++++ .../riscv/rvv/base/vmulh_vx_tumu_rv32-3.c | 157 ++++++++++ .../riscv/rvv/base/vmulh_vx_tumu_rv64-1.c | 160 ++++++++++ .../riscv/rvv/base/vmulh_vx_tumu_rv64-2.c | 160 ++++++++++ .../riscv/rvv/base/vmulh_vx_tumu_rv64-3.c | 160 ++++++++++ .../gcc.target/riscv/rvv/base/vmulhsu_vv-1.c | 160 ++++++++++ .../gcc.target/riscv/rvv/base/vmulhsu_vv-2.c | 160 ++++++++++ .../gcc.target/riscv/rvv/base/vmulhsu_vv-3.c | 160 ++++++++++ .../gcc.target/riscv/rvv/base/vmulhsu_vv_m-1.c | 160 ++++++++++ .../gcc.target/riscv/rvv/base/vmulhsu_vv_m-2.c | 160 ++++++++++ .../gcc.target/riscv/rvv/base/vmulhsu_vv_m-3.c | 160 ++++++++++ .../gcc.target/riscv/rvv/base/vmulhsu_vv_mu-1.c | 160 ++++++++++ .../gcc.target/riscv/rvv/base/vmulhsu_vv_mu-2.c | 160 ++++++++++ .../gcc.target/riscv/rvv/base/vmulhsu_vv_mu-3.c | 160 ++++++++++ .../gcc.target/riscv/rvv/base/vmulhsu_vv_tu-1.c | 160 ++++++++++ .../gcc.target/riscv/rvv/base/vmulhsu_vv_tu-2.c | 160 ++++++++++ .../gcc.target/riscv/rvv/base/vmulhsu_vv_tu-3.c | 160 ++++++++++ .../gcc.target/riscv/rvv/base/vmulhsu_vv_tum-1.c | 160 ++++++++++ .../gcc.target/riscv/rvv/base/vmulhsu_vv_tum-2.c | 160 ++++++++++ .../gcc.target/riscv/rvv/base/vmulhsu_vv_tum-3.c | 160 ++++++++++ .../gcc.target/riscv/rvv/base/vmulhsu_vv_tumu-1.c | 160 ++++++++++ .../gcc.target/riscv/rvv/base/vmulhsu_vv_tumu-2.c | 160 ++++++++++ .../gcc.target/riscv/rvv/base/vmulhsu_vv_tumu-3.c | 160 ++++++++++ .../riscv/rvv/base/vmulhsu_vx_m_rv32-1.c | 157 ++++++++++ .../riscv/rvv/base/vmulhsu_vx_m_rv32-2.c | 157 ++++++++++ .../riscv/rvv/base/vmulhsu_vx_m_rv32-3.c | 157 ++++++++++ .../riscv/rvv/base/vmulhsu_vx_m_rv64-1.c | 160 ++++++++++ .../riscv/rvv/base/vmulhsu_vx_m_rv64-2.c | 160 ++++++++++ .../riscv/rvv/base/vmulhsu_vx_m_rv64-3.c | 160 ++++++++++ .../riscv/rvv/base/vmulhsu_vx_mu_rv32-1.c | 157 ++++++++++ .../riscv/rvv/base/vmulhsu_vx_mu_rv32-2.c | 157 ++++++++++ .../riscv/rvv/base/vmulhsu_vx_mu_rv32-3.c | 157 ++++++++++ .../riscv/rvv/base/vmulhsu_vx_mu_rv64-1.c | 160 ++++++++++ .../riscv/rvv/base/vmulhsu_vx_mu_rv64-2.c | 160 ++++++++++ .../riscv/rvv/base/vmulhsu_vx_mu_rv64-3.c | 160 ++++++++++ .../gcc.target/riscv/rvv/base/vmulhsu_vx_rv32-1.c | 157 ++++++++++ .../gcc.target/riscv/rvv/base/vmulhsu_vx_rv32-2.c | 157 ++++++++++ .../gcc.target/riscv/rvv/base/vmulhsu_vx_rv32-3.c | 157 ++++++++++ .../gcc.target/riscv/rvv/base/vmulhsu_vx_rv64-1.c | 160 ++++++++++ .../gcc.target/riscv/rvv/base/vmulhsu_vx_rv64-2.c | 160 ++++++++++ .../gcc.target/riscv/rvv/base/vmulhsu_vx_rv64-3.c | 160 ++++++++++ .../riscv/rvv/base/vmulhsu_vx_tu_rv32-1.c | 157 ++++++++++ .../riscv/rvv/base/vmulhsu_vx_tu_rv32-2.c | 157 ++++++++++ .../riscv/rvv/base/vmulhsu_vx_tu_rv32-3.c | 157 ++++++++++ .../riscv/rvv/base/vmulhsu_vx_tu_rv64-1.c | 160 ++++++++++ .../riscv/rvv/base/vmulhsu_vx_tu_rv64-2.c | 160 ++++++++++ .../riscv/rvv/base/vmulhsu_vx_tu_rv64-3.c | 160 ++++++++++ .../riscv/rvv/base/vmulhsu_vx_tum_rv32-1.c | 157 ++++++++++ .../riscv/rvv/base/vmulhsu_vx_tum_rv32-2.c | 157 ++++++++++ .../riscv/rvv/base/vmulhsu_vx_tum_rv32-3.c | 157 ++++++++++ .../riscv/rvv/base/vmulhsu_vx_tum_rv64-1.c | 160 ++++++++++ .../riscv/rvv/base/vmulhsu_vx_tum_rv64-2.c | 160 ++++++++++ .../riscv/rvv/base/vmulhsu_vx_tum_rv64-3.c | 160 ++++++++++ .../riscv/rvv/base/vmulhsu_vx_tumu_rv32-1.c | 157 ++++++++++ .../riscv/rvv/base/vmulhsu_vx_tumu_rv32-2.c | 157 ++++++++++ .../riscv/rvv/base/vmulhsu_vx_tumu_rv32-3.c | 157 ++++++++++ .../riscv/rvv/base/vmulhsu_vx_tumu_rv64-1.c | 160 ++++++++++ .../riscv/rvv/base/vmulhsu_vx_tumu_rv64-2.c | 160 ++++++++++ .../riscv/rvv/base/vmulhsu_vx_tumu_rv64-3.c | 160 ++++++++++ .../gcc.target/riscv/rvv/base/vmulhu_vv-1.c | 160 ++++++++++ .../gcc.target/riscv/rvv/base/vmulhu_vv-2.c | 160 ++++++++++ .../gcc.target/riscv/rvv/base/vmulhu_vv-3.c | 160 ++++++++++ .../gcc.target/riscv/rvv/base/vmulhu_vv_m-1.c | 160 ++++++++++ .../gcc.target/riscv/rvv/base/vmulhu_vv_m-2.c | 160 ++++++++++ .../gcc.target/riscv/rvv/base/vmulhu_vv_m-3.c | 160 ++++++++++ .../gcc.target/riscv/rvv/base/vmulhu_vv_mu-1.c | 160 ++++++++++ .../gcc.target/riscv/rvv/base/vmulhu_vv_mu-2.c | 160 ++++++++++ .../gcc.target/riscv/rvv/base/vmulhu_vv_mu-3.c | 160 ++++++++++ .../gcc.target/riscv/rvv/base/vmulhu_vv_tu-1.c | 160 ++++++++++ .../gcc.target/riscv/rvv/base/vmulhu_vv_tu-2.c | 160 ++++++++++ .../gcc.target/riscv/rvv/base/vmulhu_vv_tu-3.c | 160 ++++++++++ .../gcc.target/riscv/rvv/base/vmulhu_vv_tum-1.c | 160 ++++++++++ .../gcc.target/riscv/rvv/base/vmulhu_vv_tum-2.c | 160 ++++++++++ .../gcc.target/riscv/rvv/base/vmulhu_vv_tum-3.c | 160 ++++++++++ .../gcc.target/riscv/rvv/base/vmulhu_vv_tumu-1.c | 160 ++++++++++ .../gcc.target/riscv/rvv/base/vmulhu_vv_tumu-2.c | 160 ++++++++++ .../gcc.target/riscv/rvv/base/vmulhu_vv_tumu-3.c | 160 ++++++++++ .../gcc.target/riscv/rvv/base/vmulhu_vx_m_rv32-1.c | 157 ++++++++++ .../gcc.target/riscv/rvv/base/vmulhu_vx_m_rv32-2.c | 157 ++++++++++ .../gcc.target/riscv/rvv/base/vmulhu_vx_m_rv32-3.c | 157 ++++++++++ .../gcc.target/riscv/rvv/base/vmulhu_vx_m_rv64-1.c | 160 ++++++++++ .../gcc.target/riscv/rvv/base/vmulhu_vx_m_rv64-2.c | 160 ++++++++++ .../gcc.target/riscv/rvv/base/vmulhu_vx_m_rv64-3.c | 160 ++++++++++ .../riscv/rvv/base/vmulhu_vx_mu_rv32-1.c | 157 ++++++++++ .../riscv/rvv/base/vmulhu_vx_mu_rv32-2.c | 157 ++++++++++ .../riscv/rvv/base/vmulhu_vx_mu_rv32-3.c | 157 ++++++++++ .../riscv/rvv/base/vmulhu_vx_mu_rv64-1.c | 160 ++++++++++ .../riscv/rvv/base/vmulhu_vx_mu_rv64-2.c | 160 ++++++++++ .../riscv/rvv/base/vmulhu_vx_mu_rv64-3.c | 160 ++++++++++ .../gcc.target/riscv/rvv/base/vmulhu_vx_rv32-1.c | 157 ++++++++++ .../gcc.target/riscv/rvv/base/vmulhu_vx_rv32-2.c | 157 ++++++++++ .../gcc.target/riscv/rvv/base/vmulhu_vx_rv32-3.c | 157 ++++++++++ .../gcc.target/riscv/rvv/base/vmulhu_vx_rv64-1.c | 160 ++++++++++ .../gcc.target/riscv/rvv/base/vmulhu_vx_rv64-2.c | 160 ++++++++++ .../gcc.target/riscv/rvv/base/vmulhu_vx_rv64-3.c | 160 ++++++++++ .../riscv/rvv/base/vmulhu_vx_tu_rv32-1.c | 157 ++++++++++ .../riscv/rvv/base/vmulhu_vx_tu_rv32-2.c | 157 ++++++++++ .../riscv/rvv/base/vmulhu_vx_tu_rv32-3.c | 157 ++++++++++ .../riscv/rvv/base/vmulhu_vx_tu_rv64-1.c | 160 ++++++++++ .../riscv/rvv/base/vmulhu_vx_tu_rv64-2.c | 160 ++++++++++ .../riscv/rvv/base/vmulhu_vx_tu_rv64-3.c | 160 ++++++++++ .../riscv/rvv/base/vmulhu_vx_tum_rv32-1.c | 157 ++++++++++ .../riscv/rvv/base/vmulhu_vx_tum_rv32-2.c | 157 ++++++++++ .../riscv/rvv/base/vmulhu_vx_tum_rv32-3.c | 157 ++++++++++ .../riscv/rvv/base/vmulhu_vx_tum_rv64-1.c | 160 ++++++++++ .../riscv/rvv/base/vmulhu_vx_tum_rv64-2.c | 160 ++++++++++ .../riscv/rvv/base/vmulhu_vx_tum_rv64-3.c | 160 ++++++++++ .../riscv/rvv/base/vmulhu_vx_tumu_rv32-1.c | 157 ++++++++++ .../riscv/rvv/base/vmulhu_vx_tumu_rv32-2.c | 157 ++++++++++ .../riscv/rvv/base/vmulhu_vx_tumu_rv32-3.c | 157 ++++++++++ .../riscv/rvv/base/vmulhu_vx_tumu_rv64-1.c | 160 ++++++++++ .../riscv/rvv/base/vmulhu_vx_tumu_rv64-2.c | 160 ++++++++++ .../riscv/rvv/base/vmulhu_vx_tumu_rv64-3.c | 160 ++++++++++ .../gcc.target/riscv/rvv/base/vwadd_vv-1.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwadd_vv-2.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwadd_vv-3.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwadd_vv_m-1.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwadd_vv_m-2.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwadd_vv_m-3.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwadd_vv_mu-1.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwadd_vv_mu-2.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwadd_vv_mu-3.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwadd_vv_tu-1.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwadd_vv_tu-2.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwadd_vv_tu-3.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwadd_vv_tum-1.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwadd_vv_tum-2.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwadd_vv_tum-3.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwadd_vv_tumu-1.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwadd_vv_tumu-2.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwadd_vv_tumu-3.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwadd_vx-1.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwadd_vx-2.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwadd_vx-3.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwadd_vx_m-1.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwadd_vx_m-2.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwadd_vx_m-3.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwadd_vx_mu-1.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwadd_vx_mu-2.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwadd_vx_mu-3.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwadd_vx_tu-1.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwadd_vx_tu-2.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwadd_vx_tu-3.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwadd_vx_tum-1.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwadd_vx_tum-2.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwadd_vx_tum-3.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwadd_vx_tumu-1.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwadd_vx_tumu-2.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwadd_vx_tumu-3.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwadd_wv-1.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwadd_wv-2.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwadd_wv-3.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwadd_wv_m-1.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwadd_wv_m-2.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwadd_wv_m-3.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwadd_wv_mu-1.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwadd_wv_mu-2.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwadd_wv_mu-3.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwadd_wv_tu-1.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwadd_wv_tu-2.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwadd_wv_tu-3.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwadd_wv_tum-1.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwadd_wv_tum-2.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwadd_wv_tum-3.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwadd_wv_tumu-1.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwadd_wv_tumu-2.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwadd_wv_tumu-3.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwadd_wx-1.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwadd_wx-2.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwadd_wx-3.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwadd_wx_m-1.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwadd_wx_m-2.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwadd_wx_m-3.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwadd_wx_mu-1.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwadd_wx_mu-2.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwadd_wx_mu-3.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwadd_wx_tu-1.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwadd_wx_tu-2.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwadd_wx_tu-3.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwadd_wx_tum-1.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwadd_wx_tum-2.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwadd_wx_tum-3.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwadd_wx_tumu-1.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwadd_wx_tumu-2.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwadd_wx_tumu-3.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwaddu_vv-1.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwaddu_vv-2.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwaddu_vv-3.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwaddu_vv_m-1.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwaddu_vv_m-2.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwaddu_vv_m-3.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwaddu_vv_mu-1.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwaddu_vv_mu-2.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwaddu_vv_mu-3.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwaddu_vv_tu-1.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwaddu_vv_tu-2.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwaddu_vv_tu-3.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwaddu_vv_tum-1.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwaddu_vv_tum-2.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwaddu_vv_tum-3.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwaddu_vv_tumu-1.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwaddu_vv_tumu-2.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwaddu_vv_tumu-3.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwaddu_vx-1.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwaddu_vx-2.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwaddu_vx-3.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwaddu_vx_m-1.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwaddu_vx_m-2.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwaddu_vx_m-3.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwaddu_vx_mu-1.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwaddu_vx_mu-2.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwaddu_vx_mu-3.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwaddu_vx_tu-1.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwaddu_vx_tu-2.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwaddu_vx_tu-3.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwaddu_vx_tum-1.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwaddu_vx_tum-2.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwaddu_vx_tum-3.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwaddu_vx_tumu-1.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwaddu_vx_tumu-2.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwaddu_vx_tumu-3.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwaddu_wv-1.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwaddu_wv-2.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwaddu_wv-3.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwaddu_wv_m-1.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwaddu_wv_m-2.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwaddu_wv_m-3.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwaddu_wv_mu-1.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwaddu_wv_mu-2.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwaddu_wv_mu-3.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwaddu_wv_tu-1.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwaddu_wv_tu-2.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwaddu_wv_tu-3.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwaddu_wv_tum-1.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwaddu_wv_tum-2.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwaddu_wv_tum-3.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwaddu_wv_tumu-1.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwaddu_wv_tumu-2.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwaddu_wv_tumu-3.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwaddu_wx-1.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwaddu_wx-2.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwaddu_wx-3.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwaddu_wx_m-1.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwaddu_wx_m-2.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwaddu_wx_m-3.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwaddu_wx_mu-1.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwaddu_wx_mu-2.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwaddu_wx_mu-3.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwaddu_wx_tu-1.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwaddu_wx_tu-2.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwaddu_wx_tu-3.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwaddu_wx_tum-1.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwaddu_wx_tum-2.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwaddu_wx_tum-3.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwaddu_wx_tumu-1.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwaddu_wx_tumu-2.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwaddu_wx_tumu-3.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwcvt_x-1.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwcvt_x-2.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwcvt_x-3.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwcvt_x_m-1.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwcvt_x_m-2.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwcvt_x_m-3.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwcvt_x_mu-1.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwcvt_x_mu-2.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwcvt_x_mu-3.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwcvt_x_tu-1.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwcvt_x_tu-2.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwcvt_x_tu-3.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwcvt_x_tum-1.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwcvt_x_tum-2.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwcvt_x_tum-3.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwcvt_x_tumu-1.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwcvt_x_tumu-2.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwcvt_x_tumu-3.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwcvtu_x-1.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwcvtu_x-2.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwcvtu_x-3.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwcvtu_x_m-1.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwcvtu_x_m-2.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwcvtu_x_m-3.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwcvtu_x_mu-1.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwcvtu_x_mu-2.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwcvtu_x_mu-3.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwcvtu_x_tu-1.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwcvtu_x_tu-2.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwcvtu_x_tu-3.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwcvtu_x_tum-1.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwcvtu_x_tum-2.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwcvtu_x_tum-3.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwcvtu_x_tumu-1.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwcvtu_x_tumu-2.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwcvtu_x_tumu-3.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwmul_vv-1.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwmul_vv-2.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwmul_vv-3.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwmul_vv_m-1.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwmul_vv_m-2.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwmul_vv_m-3.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwmul_vv_mu-1.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwmul_vv_mu-2.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwmul_vv_mu-3.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwmul_vv_tu-1.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwmul_vv_tu-2.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwmul_vv_tu-3.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwmul_vv_tum-1.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwmul_vv_tum-2.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwmul_vv_tum-3.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwmul_vv_tumu-1.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwmul_vv_tumu-2.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwmul_vv_tumu-3.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwmul_vx-1.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwmul_vx-2.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwmul_vx-3.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwmul_vx_m-1.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwmul_vx_m-2.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwmul_vx_m-3.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwmul_vx_mu-1.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwmul_vx_mu-2.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwmul_vx_mu-3.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwmul_vx_tu-1.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwmul_vx_tu-2.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwmul_vx_tu-3.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwmul_vx_tum-1.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwmul_vx_tum-2.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwmul_vx_tum-3.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwmul_vx_tumu-1.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwmul_vx_tumu-2.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwmul_vx_tumu-3.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwmulsu_vv-1.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwmulsu_vv-2.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwmulsu_vv-3.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwmulsu_vv_m-1.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwmulsu_vv_m-2.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwmulsu_vv_m-3.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwmulsu_vv_mu-1.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwmulsu_vv_mu-2.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwmulsu_vv_mu-3.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwmulsu_vv_tu-1.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwmulsu_vv_tu-2.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwmulsu_vv_tu-3.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwmulsu_vv_tum-1.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwmulsu_vv_tum-2.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwmulsu_vv_tum-3.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwmulsu_vv_tumu-1.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwmulsu_vv_tumu-2.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwmulsu_vv_tumu-3.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwmulsu_vx-1.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwmulsu_vx-2.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwmulsu_vx-3.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwmulsu_vx_m-1.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwmulsu_vx_m-2.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwmulsu_vx_m-3.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwmulsu_vx_mu-1.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwmulsu_vx_mu-2.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwmulsu_vx_mu-3.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwmulsu_vx_tu-1.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwmulsu_vx_tu-2.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwmulsu_vx_tu-3.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwmulsu_vx_tum-1.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwmulsu_vx_tum-2.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwmulsu_vx_tum-3.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwmulsu_vx_tumu-1.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwmulsu_vx_tumu-2.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwmulsu_vx_tumu-3.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwmulu_vv-1.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwmulu_vv-2.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwmulu_vv-3.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwmulu_vv_m-1.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwmulu_vv_m-2.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwmulu_vv_m-3.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwmulu_vv_mu-1.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwmulu_vv_mu-2.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwmulu_vv_mu-3.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwmulu_vv_tu-1.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwmulu_vv_tu-2.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwmulu_vv_tu-3.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwmulu_vv_tum-1.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwmulu_vv_tum-2.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwmulu_vv_tum-3.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwmulu_vv_tumu-1.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwmulu_vv_tumu-2.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwmulu_vv_tumu-3.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwmulu_vx-1.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwmulu_vx-2.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwmulu_vx-3.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwmulu_vx_m-1.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwmulu_vx_m-2.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwmulu_vx_m-3.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwmulu_vx_mu-1.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwmulu_vx_mu-2.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwmulu_vx_mu-3.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwmulu_vx_tu-1.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwmulu_vx_tu-2.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwmulu_vx_tu-3.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwmulu_vx_tum-1.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwmulu_vx_tum-2.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwmulu_vx_tum-3.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwmulu_vx_tumu-1.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwmulu_vx_tumu-2.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwmulu_vx_tumu-3.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwsub_vv-1.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwsub_vv-2.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwsub_vv-3.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwsub_vv_m-1.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwsub_vv_m-2.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwsub_vv_m-3.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwsub_vv_mu-1.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwsub_vv_mu-2.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwsub_vv_mu-3.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwsub_vv_tu-1.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwsub_vv_tu-2.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwsub_vv_tu-3.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwsub_vv_tum-1.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwsub_vv_tum-2.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwsub_vv_tum-3.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwsub_vv_tumu-1.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwsub_vv_tumu-2.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwsub_vv_tumu-3.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwsub_vx-1.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwsub_vx-2.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwsub_vx-3.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwsub_vx_m-1.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwsub_vx_m-2.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwsub_vx_m-3.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwsub_vx_mu-1.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwsub_vx_mu-2.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwsub_vx_mu-3.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwsub_vx_tu-1.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwsub_vx_tu-2.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwsub_vx_tu-3.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwsub_vx_tum-1.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwsub_vx_tum-2.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwsub_vx_tum-3.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwsub_vx_tumu-1.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwsub_vx_tumu-2.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwsub_vx_tumu-3.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwsub_wv-1.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwsub_wv-2.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwsub_wv-3.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwsub_wv_m-1.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwsub_wv_m-2.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwsub_wv_m-3.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwsub_wv_mu-1.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwsub_wv_mu-2.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwsub_wv_mu-3.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwsub_wv_tu-1.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwsub_wv_tu-2.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwsub_wv_tu-3.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwsub_wv_tum-1.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwsub_wv_tum-2.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwsub_wv_tum-3.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwsub_wv_tumu-1.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwsub_wv_tumu-2.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwsub_wv_tumu-3.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwsub_wx-1.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwsub_wx-2.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwsub_wx-3.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwsub_wx_m-1.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwsub_wx_m-2.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwsub_wx_m-3.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwsub_wx_mu-1.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwsub_wx_mu-2.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwsub_wx_mu-3.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwsub_wx_tu-1.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwsub_wx_tu-2.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwsub_wx_tu-3.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwsub_wx_tum-1.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwsub_wx_tum-2.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwsub_wx_tum-3.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwsub_wx_tumu-1.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwsub_wx_tumu-2.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwsub_wx_tumu-3.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwsubu_vv-1.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwsubu_vv-2.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwsubu_vv-3.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwsubu_vv_m-1.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwsubu_vv_m-2.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwsubu_vv_m-3.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwsubu_vv_mu-1.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwsubu_vv_mu-2.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwsubu_vv_mu-3.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwsubu_vv_tu-1.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwsubu_vv_tu-2.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwsubu_vv_tu-3.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwsubu_vv_tum-1.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwsubu_vv_tum-2.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwsubu_vv_tum-3.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwsubu_vv_tumu-1.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwsubu_vv_tumu-2.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwsubu_vv_tumu-3.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwsubu_vx-1.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwsubu_vx-2.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwsubu_vx-3.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwsubu_vx_m-1.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwsubu_vx_m-2.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwsubu_vx_m-3.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwsubu_vx_mu-1.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwsubu_vx_mu-2.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwsubu_vx_mu-3.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwsubu_vx_tu-1.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwsubu_vx_tu-2.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwsubu_vx_tu-3.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwsubu_vx_tum-1.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwsubu_vx_tum-2.c | 111 +++++++ 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.../gcc.target/riscv/rvv/base/vwsubu_wv_tum-1.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwsubu_wv_tum-2.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwsubu_wv_tum-3.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwsubu_wv_tumu-1.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwsubu_wv_tumu-2.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwsubu_wv_tumu-3.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwsubu_wx-1.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwsubu_wx-2.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwsubu_wx-3.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwsubu_wx_m-1.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwsubu_wx_m-2.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwsubu_wx_m-3.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwsubu_wx_mu-1.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwsubu_wx_mu-2.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwsubu_wx_mu-3.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwsubu_wx_tu-1.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwsubu_wx_tu-2.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwsubu_wx_tu-3.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwsubu_wx_tum-1.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwsubu_wx_tum-2.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwsubu_wx_tum-3.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwsubu_wx_tumu-1.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwsubu_wx_tumu-2.c | 111 +++++++ .../gcc.target/riscv/rvv/base/vwsubu_wx_tumu-3.c | 111 +++++++ 1090 files changed, 144866 insertions(+), 13 deletions(-) create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulh_vv-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulh_vv-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulh_vv-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulh_vv_mu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulh_vv_mu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulh_vv_mu-3.C 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1 year, 9 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_gcc_bootstrap/master-aarch64-bootstrap_ubsan updated (e7d51861cf -> 7988e918ff)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_gcc_bootstrap/master-aarch64-bootstrap_ubsan in repository toolchain/ci/base-artifacts. discards e7d51861cf 175: onsuccess: #618: 2: Success after binutils/gcc: 85 commits discards 69ce18df3c 174: onsuccess: #616: 2: Success after binutils/gcc: 37 commits discards c6d8c60fc0 173: onsuccess: #615: 2: Success after binutils/gcc: 16 commits discards 44cad673e5 172: onsuccess: #614: 2: Success after binutils/gcc: 24 commits discards b2d1a594a0 171: onsuccess: #613: 2: Success after binutils/gcc: 14 commits discards 032ca9da7b 170: onsuccess: #612: 2: Success after binutils/gcc: 29 commits discards d22e9d355c 169: onsuccess: #611: 2: Success after binutils/gcc: 58 commits discards 2ad5b137a8 168: onsuccess: #610: 2: Success after binutils/gcc: 42 commits discards 7d5474e6a7 167: onsuccess: #609: 2: Success after binutils/gcc: 107 commits discards 2d3d5fd688 166: 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That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (e7d51861cf) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_gcc_bootstrap/master-aar [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 102 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log.xz | Bin 1764 -> 1792 bytes 02-prepare_abe/console.log.xz | Bin 2756 -> 2752 bytes 04-build_abe-binutils/console.log.xz | Bin 38848 -> 38804 bytes 05-build_abe-bootstrap_ubsan/console.log.xz | Bin 346140 -> 344896 bytes 06-check_regression/console.log.xz | Bin 3056 -> 2928 bytes 07-update_baseline/console.log | 38 ++++++++++++++-------------- dashboard/dashboard-generate.sh | 2 +- git/binutils_rev | 2 +- git/gcc_rev | 2 +- mail/jira-body.txt | 2 +- mail/mail-body.txt | 2 +- mail/mail-subject.txt | 2 +- manifest.sh | 18 ++++++------- 13 files changed, 34 insertions(+), 34 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

1 year, 9 months

[binutils-gdb] branch master updated (2ecee236752 -> f0bdf68d3fb)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository binutils-gdb. from 2ecee236752 gdb: use -1 for breakpoint::task default value new f0bdf68d3fb gdb/c++: fix handling of breakpoints on @plt symbols The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: .../breakpoint-shlib-func-lib.cc} | 5 +- .../breakpoint-shlib-func.cc} | 8 ++- gdb/testsuite/gdb.cp/breakpoint-shlib-func.exp | 83 ++++++++++++++++++++++ gdb/utils.c | 31 +++++++- 4 files changed, 120 insertions(+), 7 deletions(-) copy gdb/testsuite/{gdb.debuginfod/build-id-no-debug-warning.c => gdb.cp/breakpoin [...] copy gdb/testsuite/{gdb.dwarf2/clang-cli-macro.c => gdb.cp/breakpoint-shlib-func.c [...] create mode 100644 gdb/testsuite/gdb.cp/breakpoint-shlib-func.exp -- To stop receiving notification emails like this one, please contact the administrator of this repository.

1 year, 9 months

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