Tcwg-commits February 2023

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[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_gcc_bootstrap/master-aarch64-bootstrap_lto updated (06b118ca86 -> 38aa0f5f22)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_gcc_bootstrap/master-aarch64-bootstrap_lto in repository toolchain/ci/base-artifacts. discards 06b118ca86 192: onsuccess: #602: 2: Success after binutils/gcc: 78 commits discards f87826aa12 191: onsuccess: #601: 2: Success after binutils/gcc: 56 commits discards 3cae1b2b9a 190: onsuccess: #599: 2: Success after binutils/gcc: 18 commits discards 94f040a109 189: onsuccess: #598: 2: Success after binutils/gcc: 24 commits discards 6c5c86df7f 188: onsuccess: #597: 2: Success after binutils/gcc: 7 commits discards c2a46cdc85 187: onsuccess: #596: 2: Success after binutils/gcc: 3 commits discards 82205664e1 186: onsuccess: #595: 2: Success after binutils/gcc: 27 commits discards 59384b54f5 185: onsuccess: #594: 2: Success after binutils/gcc: 53 commits discards 3bece0cb60 184: onsuccess: #593: 2: Success after binutils/gcc: 47 commits discards c2ff8747b3 183: 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onsuccess: #595: 2: Success after binutils/gcc: 27 commits new 192d3e2123 187: onsuccess: #596: 2: Success after binutils/gcc: 3 commits new 5ab86b2881 188: onsuccess: #597: 2: Success after binutils/gcc: 7 commits new c61f7f9a3b 189: onsuccess: #598: 2: Success after binutils/gcc: 24 commits new 1669ce4065 190: onsuccess: #599: 2: Success after binutils/gcc: 18 commits new 29592591aa 191: onsuccess: #601: 2: Success after binutils/gcc: 56 commits new 67a792bb09 192: onsuccess: #602: 2: Success after binutils/gcc: 78 commits new 38aa0f5f22 193: onsuccess: #603: 2: Success after binutils/gcc: 118 commits This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (06b118ca86) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_gcc_bootstrap/master-aar [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 102 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log.xz | Bin 1736 -> 1756 bytes 02-prepare_abe/console.log.xz | Bin 2752 -> 2744 bytes 04-build_abe-binutils/console.log.xz | Bin 39504 -> 39100 bytes 05-build_abe-bootstrap_lto/console.log.xz | Bin 277544 -> 276996 bytes 06-check_regression/console.log.xz | Bin 3044 -> 2952 bytes 07-update_baseline/console.log | 32 +++++++++++++++--------------- dashboard/dashboard-generate.sh | 2 +- git/binutils_rev | 2 +- git/gcc_rev | 2 +- mail/jira-body.txt | 2 +- mail/mail-body.txt | 2 +- mail/mail-subject.txt | 2 +- manifest.sh | 18 ++++++++--------- 13 files changed, 31 insertions(+), 31 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

2 years, 3 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/gnu-master-aarch64-mainline-allyesconfig updated (0a97ede8cf -> 4b77d6701a)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-master-aarch64-mainline-allyesconfig in repository toolchain/ci/base-artifacts. from 0a97ede8cf 44: onsuccess: #548: 21789: Success after binutils/gcc/linux [...] new 4b77d6701a 45: onsuccess: #549: 21789: Success after binutils/gcc/linux [...] The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log.xz | Bin 1792 -> 1840 bytes 02-prepare_abe/console.log.xz | Bin 2800 -> 2772 bytes 03-build_abe-binutils/console.log.xz | Bin 31844 -> 31396 bytes 04-build_abe-stage1/console.log.xz | Bin 74228 -> 73256 bytes 05-build_abe-qemu/console.log.xz | Bin 32092 -> 30416 bytes 06-build_linux/console.log.xz | Bin 11372 -> 11316 bytes 08-check_regression/console.log.xz | Bin 4476 -> 4256 bytes dashboard/dashboard-generate.sh | 2 +- git/binutils_rev | 2 +- git/gcc_rev | 2 +- git/linux_rev | 2 +- git/qemu_rev | 2 +- mail/jira-body.txt | 2 +- mail/mail-body.txt | 2 +- mail/mail-subject.txt | 2 +- manifest.sh | 32 ++++++++++++++++---------------- 16 files changed, 24 insertions(+), 24 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

2 years, 3 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/llvm-master-arm-stable-allnoconfig updated (3e157b74d0 -> 1f692adec8)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-arm-stable-allnoconfig in repository toolchain/ci/base-artifacts. from 3e157b74d0 42: onsuccess: #429: all: Success after binutils/llvm/linux/ [...] new 1f692adec8 43: onsuccess: #430: all: Success after binutils/llvm/linux/ [...] The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log.xz | Bin 1764 -> 1760 bytes 02-prepare_abe/console.log.xz | Bin 2772 -> 2764 bytes 03-build_abe-binutils/console.log.xz | Bin 30996 -> 31284 bytes 04-build_kernel_llvm/console.log.xz | Bin 65520 -> 63428 bytes 05-build_abe-qemu/console.log.xz | Bin 31812 -> 31328 bytes 06-build_linux/console.log.xz | Bin 3468 -> 3444 bytes 07-boot_linux/console.log.xz | Bin 496 -> 496 bytes 08-check_regression/console.log.xz | Bin 4348 -> 4460 bytes dashboard/dashboard-generate.sh | 2 +- git/binutils_rev | 2 +- git/linux_rev | 2 +- git/llvm_rev | 2 +- git/qemu_rev | 2 +- mail/jira-body.txt | 2 +- mail/mail-body.txt | 2 +- mail/mail-subject.txt | 2 +- manifest.sh | 32 ++++++++++++++++---------------- 17 files changed, 24 insertions(+), 24 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

2 years, 3 months

[gcc] branch master updated (4fd0cfd87b1 -> 2cd7cbaf51f)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository gcc. from 4fd0cfd87b1 libstdc++: Change www.unix.org to unix.org new e09418f21dd RISC-V: Add fixed-point support new 71a1c2c67aa RISC-V: Add vssrl.vx C API tests new 13907f4bd2e RISC-V: Add vssrl.vv C API tests new 4e00937ec3e RISC-V: Add vssra.vx C API tests new 5ca5ca30b6a RISC-V: Add vssra.vv C API tests new bbb168daecf RISC-V: Add vsmul.vx C API tests new c156e8d7bcf RISC-V: Add vsmul.vv C API tests new 367a01e6a06 RISC-V: Add vnclip C API tests new 1580eda6c3d RISC-V: Add vasubu.vx C API tests new 193a125c3fe RISC-V: Add vasubu.vv C API tests new 48e24473fe1 RISC-V: Add vasub.vx C API tests new 4432ef4eca4 RISC-V: Add vasub.vv C API tests new 6ad0002f1e3 RISC-V: Add vaaddu.vx C API tests new 119e5d9aff3 RISC-V: Add vaaddu.vv C api tests new 5898e1f333b RISC-V: Add vaadd.vx C api tests new e85cb86e338 RISC-V: Add vaadd.vv C api tests new b7795fb143c RISC-V: Add vssrl.vx C++ API tests new 02b0325269b RISC-V: Add vssrl.vv C++ API tests new 7326a694da9 RISC-V: Add vssra.vx C++ API tests new 49e53882081 RISC-V: Add vssra.vv C++ API tests new 73dea8e6426 RISC-V: Add vsmul.vx C++ API tests new 7302972bcd5 RISC-V: Add vsmul.vv C++ API tests new 0906435e2b6 RISC-V: Add vnclip C++ API tests new 90ea2d28d47 RISC-V: Add vasubu.vx C++ API tests new 1a8c69e7ea6 RISC-V: Add vasubu.vv C++ API tests new 3d65ea07b47 RISC-V: Add vasub.vx C++ API tests new ff4d996600b RISC-V: Add vasub.vv C++ api tests new 2ec75330230 RISC-V: Add vaaddu.vx C++ Api tests new 0b1f45786f4 RISC-V: Add vaaddu.vv C++ api tests new e8a0c9e9d41 RISC-V: Add vaadd.vx C++ API tests new 2cd7cbaf51f RISC-V: Add vaadd.vv C++ API tests The 31 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: gcc/config/riscv/riscv-vector-builtins-bases.cc | 59 ++++ gcc/config/riscv/riscv-vector-builtins-bases.h | 12 +- .../riscv/riscv-vector-builtins-functions.def | 18 ++ gcc/config/riscv/vector-iterators.md | 32 ++- gcc/config/riscv/vector.md | 238 +++++++++++++++- .../g++.target/riscv/rvv/base/vaadd_vv-1.C | 314 +++++++++++++++++++++ .../g++.target/riscv/rvv/base/vaadd_vv-2.C | 314 +++++++++++++++++++++ .../g++.target/riscv/rvv/base/vaadd_vv-3.C | 314 +++++++++++++++++++++ .../g++.target/riscv/rvv/base/vaadd_vv_mu-1.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vaadd_vv_mu-2.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vaadd_vv_mu-3.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vaadd_vv_tu-1.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vaadd_vv_tu-2.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vaadd_vv_tu-3.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vaadd_vv_tum-1.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vaadd_vv_tum-2.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vaadd_vv_tum-3.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vaadd_vv_tumu-1.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vaadd_vv_tumu-2.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vaadd_vv_tumu-3.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vaadd_vx_mu_rv32-1.C | 157 +++++++++++ .../g++.target/riscv/rvv/base/vaadd_vx_mu_rv32-2.C | 157 +++++++++++ .../g++.target/riscv/rvv/base/vaadd_vx_mu_rv32-3.C | 157 +++++++++++ .../g++.target/riscv/rvv/base/vaadd_vx_mu_rv64-1.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vaadd_vx_mu_rv64-2.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vaadd_vx_mu_rv64-3.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vaadd_vx_rv32-1.C | 308 ++++++++++++++++++++ .../g++.target/riscv/rvv/base/vaadd_vx_rv32-2.C | 308 ++++++++++++++++++++ .../g++.target/riscv/rvv/base/vaadd_vx_rv32-3.C | 308 ++++++++++++++++++++ .../g++.target/riscv/rvv/base/vaadd_vx_rv64-1.C | 314 +++++++++++++++++++++ .../g++.target/riscv/rvv/base/vaadd_vx_rv64-2.C | 314 +++++++++++++++++++++ .../g++.target/riscv/rvv/base/vaadd_vx_rv64-3.C | 314 +++++++++++++++++++++ .../g++.target/riscv/rvv/base/vaadd_vx_tu_rv32-1.C | 157 +++++++++++ .../g++.target/riscv/rvv/base/vaadd_vx_tu_rv32-2.C | 157 +++++++++++ .../g++.target/riscv/rvv/base/vaadd_vx_tu_rv32-3.C | 157 +++++++++++ .../g++.target/riscv/rvv/base/vaadd_vx_tu_rv64-1.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vaadd_vx_tu_rv64-2.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vaadd_vx_tu_rv64-3.C | 160 +++++++++++ .../riscv/rvv/base/vaadd_vx_tum_rv32-1.C | 157 +++++++++++ .../riscv/rvv/base/vaadd_vx_tum_rv32-2.C | 157 +++++++++++ .../riscv/rvv/base/vaadd_vx_tum_rv32-3.C | 157 +++++++++++ .../riscv/rvv/base/vaadd_vx_tum_rv64-1.C | 160 +++++++++++ .../riscv/rvv/base/vaadd_vx_tum_rv64-2.C | 160 +++++++++++ .../riscv/rvv/base/vaadd_vx_tum_rv64-3.C | 160 +++++++++++ .../riscv/rvv/base/vaadd_vx_tumu_rv32-1.C | 157 +++++++++++ .../riscv/rvv/base/vaadd_vx_tumu_rv32-2.C | 157 +++++++++++ .../riscv/rvv/base/vaadd_vx_tumu_rv32-3.C | 157 +++++++++++ .../riscv/rvv/base/vaadd_vx_tumu_rv64-1.C | 160 +++++++++++ .../riscv/rvv/base/vaadd_vx_tumu_rv64-2.C | 160 +++++++++++ .../riscv/rvv/base/vaadd_vx_tumu_rv64-3.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vaaddu_vv-1.C | 314 +++++++++++++++++++++ .../g++.target/riscv/rvv/base/vaaddu_vv-2.C | 314 +++++++++++++++++++++ .../g++.target/riscv/rvv/base/vaaddu_vv-3.C | 314 +++++++++++++++++++++ .../g++.target/riscv/rvv/base/vaaddu_vv_mu-1.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vaaddu_vv_mu-2.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vaaddu_vv_mu-3.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vaaddu_vv_tu-1.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vaaddu_vv_tu-2.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vaaddu_vv_tu-3.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vaaddu_vv_tum-1.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vaaddu_vv_tum-2.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vaaddu_vv_tum-3.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vaaddu_vv_tumu-1.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vaaddu_vv_tumu-2.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vaaddu_vv_tumu-3.C | 160 +++++++++++ .../riscv/rvv/base/vaaddu_vx_mu_rv32-1.C | 157 +++++++++++ .../riscv/rvv/base/vaaddu_vx_mu_rv32-2.C | 157 +++++++++++ .../riscv/rvv/base/vaaddu_vx_mu_rv32-3.C | 157 +++++++++++ .../riscv/rvv/base/vaaddu_vx_mu_rv64-1.C | 160 +++++++++++ .../riscv/rvv/base/vaaddu_vx_mu_rv64-2.C | 160 +++++++++++ .../riscv/rvv/base/vaaddu_vx_mu_rv64-3.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vaaddu_vx_rv32-1.C | 308 ++++++++++++++++++++ .../g++.target/riscv/rvv/base/vaaddu_vx_rv32-2.C | 308 ++++++++++++++++++++ .../g++.target/riscv/rvv/base/vaaddu_vx_rv32-3.C | 308 ++++++++++++++++++++ .../g++.target/riscv/rvv/base/vaaddu_vx_rv64-1.C | 314 +++++++++++++++++++++ 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.../riscv/rvv/base/vaaddu_vx_tumu_rv32-3.C | 157 +++++++++++ .../riscv/rvv/base/vaaddu_vx_tumu_rv64-1.C | 160 +++++++++++ .../riscv/rvv/base/vaaddu_vx_tumu_rv64-2.C | 160 +++++++++++ .../riscv/rvv/base/vaaddu_vx_tumu_rv64-3.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vasub_vv-1.C | 314 +++++++++++++++++++++ .../g++.target/riscv/rvv/base/vasub_vv-2.C | 314 +++++++++++++++++++++ .../g++.target/riscv/rvv/base/vasub_vv-3.C | 314 +++++++++++++++++++++ .../g++.target/riscv/rvv/base/vasub_vv_mu-1.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vasub_vv_mu-2.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vasub_vv_mu-3.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vasub_vv_tu-1.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vasub_vv_tu-2.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vasub_vv_tu-3.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vasub_vv_tum-1.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vasub_vv_tum-2.C | 160 +++++++++++ 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.../g++.target/riscv/rvv/base/vasub_vx_rv64-2.C | 314 +++++++++++++++++++++ .../g++.target/riscv/rvv/base/vasub_vx_rv64-3.C | 314 +++++++++++++++++++++ .../g++.target/riscv/rvv/base/vasub_vx_tu_rv32-1.C | 157 +++++++++++ .../g++.target/riscv/rvv/base/vasub_vx_tu_rv32-2.C | 157 +++++++++++ .../g++.target/riscv/rvv/base/vasub_vx_tu_rv32-3.C | 157 +++++++++++ .../g++.target/riscv/rvv/base/vasub_vx_tu_rv64-1.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vasub_vx_tu_rv64-2.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vasub_vx_tu_rv64-3.C | 160 +++++++++++ .../riscv/rvv/base/vasub_vx_tum_rv32-1.C | 157 +++++++++++ .../riscv/rvv/base/vasub_vx_tum_rv32-2.C | 157 +++++++++++ .../riscv/rvv/base/vasub_vx_tum_rv32-3.C | 157 +++++++++++ .../riscv/rvv/base/vasub_vx_tum_rv64-1.C | 160 +++++++++++ .../riscv/rvv/base/vasub_vx_tum_rv64-2.C | 160 +++++++++++ .../riscv/rvv/base/vasub_vx_tum_rv64-3.C | 160 +++++++++++ .../riscv/rvv/base/vasub_vx_tumu_rv32-1.C | 157 +++++++++++ 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.../g++.target/riscv/rvv/base/vnclip_vv_tumu-1.C | 111 ++++++++ .../g++.target/riscv/rvv/base/vnclip_vv_tumu-2.C | 111 ++++++++ .../g++.target/riscv/rvv/base/vnclip_vv_tumu-3.C | 111 ++++++++ .../g++.target/riscv/rvv/base/vnclip_vx-1.C | 216 ++++++++++++++ .../g++.target/riscv/rvv/base/vnclip_vx-2.C | 216 ++++++++++++++ .../g++.target/riscv/rvv/base/vnclip_vx-3.C | 216 ++++++++++++++ .../g++.target/riscv/rvv/base/vnclip_vx_mu-1.C | 111 ++++++++ .../g++.target/riscv/rvv/base/vnclip_vx_mu-2.C | 111 ++++++++ .../g++.target/riscv/rvv/base/vnclip_vx_mu-3.C | 111 ++++++++ .../g++.target/riscv/rvv/base/vnclip_vx_tu-1.C | 111 ++++++++ .../g++.target/riscv/rvv/base/vnclip_vx_tu-2.C | 111 ++++++++ .../g++.target/riscv/rvv/base/vnclip_vx_tu-3.C | 111 ++++++++ .../g++.target/riscv/rvv/base/vnclip_vx_tum-1.C | 111 ++++++++ .../g++.target/riscv/rvv/base/vnclip_vx_tum-2.C | 111 ++++++++ .../g++.target/riscv/rvv/base/vnclip_vx_tum-3.C | 111 ++++++++ .../g++.target/riscv/rvv/base/vnclip_vx_tumu-1.C | 111 ++++++++ .../g++.target/riscv/rvv/base/vnclip_vx_tumu-2.C | 111 ++++++++ .../g++.target/riscv/rvv/base/vnclip_vx_tumu-3.C | 111 ++++++++ .../g++.target/riscv/rvv/base/vnclipu_vv-1.C | 216 ++++++++++++++ .../g++.target/riscv/rvv/base/vnclipu_vv-2.C | 216 ++++++++++++++ .../g++.target/riscv/rvv/base/vnclipu_vv-3.C | 216 ++++++++++++++ .../g++.target/riscv/rvv/base/vnclipu_vv_mu-1.C | 111 ++++++++ .../g++.target/riscv/rvv/base/vnclipu_vv_mu-2.C | 111 ++++++++ .../g++.target/riscv/rvv/base/vnclipu_vv_mu-3.C | 111 ++++++++ .../g++.target/riscv/rvv/base/vnclipu_vv_tu-1.C | 111 ++++++++ .../g++.target/riscv/rvv/base/vnclipu_vv_tu-2.C | 111 ++++++++ .../g++.target/riscv/rvv/base/vnclipu_vv_tu-3.C | 111 ++++++++ .../g++.target/riscv/rvv/base/vnclipu_vv_tum-1.C | 111 ++++++++ .../g++.target/riscv/rvv/base/vnclipu_vv_tum-2.C | 111 ++++++++ .../g++.target/riscv/rvv/base/vnclipu_vv_tum-3.C | 111 ++++++++ .../g++.target/riscv/rvv/base/vnclipu_vv_tumu-1.C | 111 ++++++++ .../g++.target/riscv/rvv/base/vnclipu_vv_tumu-2.C | 111 ++++++++ .../g++.target/riscv/rvv/base/vnclipu_vv_tumu-3.C | 111 ++++++++ .../g++.target/riscv/rvv/base/vnclipu_vx-1.C | 216 ++++++++++++++ .../g++.target/riscv/rvv/base/vnclipu_vx-2.C | 216 ++++++++++++++ .../g++.target/riscv/rvv/base/vnclipu_vx-3.C | 216 ++++++++++++++ .../g++.target/riscv/rvv/base/vnclipu_vx_mu-1.C | 111 ++++++++ .../g++.target/riscv/rvv/base/vnclipu_vx_mu-2.C | 111 ++++++++ .../g++.target/riscv/rvv/base/vnclipu_vx_mu-3.C | 111 ++++++++ .../g++.target/riscv/rvv/base/vnclipu_vx_tu-1.C | 111 ++++++++ .../g++.target/riscv/rvv/base/vnclipu_vx_tu-2.C | 111 ++++++++ .../g++.target/riscv/rvv/base/vnclipu_vx_tu-3.C | 111 ++++++++ .../g++.target/riscv/rvv/base/vnclipu_vx_tum-1.C | 111 ++++++++ .../g++.target/riscv/rvv/base/vnclipu_vx_tum-2.C | 111 ++++++++ .../g++.target/riscv/rvv/base/vnclipu_vx_tum-3.C | 111 ++++++++ .../g++.target/riscv/rvv/base/vnclipu_vx_tumu-1.C | 111 ++++++++ .../g++.target/riscv/rvv/base/vnclipu_vx_tumu-2.C | 111 ++++++++ .../g++.target/riscv/rvv/base/vnclipu_vx_tumu-3.C | 111 ++++++++ .../g++.target/riscv/rvv/base/vsmul_vv-1.C | 314 +++++++++++++++++++++ .../g++.target/riscv/rvv/base/vsmul_vv-2.C | 314 +++++++++++++++++++++ .../g++.target/riscv/rvv/base/vsmul_vv-3.C | 314 +++++++++++++++++++++ .../g++.target/riscv/rvv/base/vsmul_vv_mu-1.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vsmul_vv_mu-2.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vsmul_vv_mu-3.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vsmul_vv_tu-1.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vsmul_vv_tu-2.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vsmul_vv_tu-3.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vsmul_vv_tum-1.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vsmul_vv_tum-2.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vsmul_vv_tum-3.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vsmul_vv_tumu-1.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vsmul_vv_tumu-2.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vsmul_vv_tumu-3.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vsmul_vx_mu_rv32-1.C | 157 +++++++++++ .../g++.target/riscv/rvv/base/vsmul_vx_mu_rv32-2.C | 157 +++++++++++ .../g++.target/riscv/rvv/base/vsmul_vx_mu_rv32-3.C | 157 +++++++++++ .../g++.target/riscv/rvv/base/vsmul_vx_mu_rv64-1.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vsmul_vx_mu_rv64-2.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vsmul_vx_mu_rv64-3.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vsmul_vx_rv32-1.C | 308 ++++++++++++++++++++ .../g++.target/riscv/rvv/base/vsmul_vx_rv32-2.C | 308 ++++++++++++++++++++ .../g++.target/riscv/rvv/base/vsmul_vx_rv32-3.C | 308 ++++++++++++++++++++ .../g++.target/riscv/rvv/base/vsmul_vx_rv64-1.C | 314 +++++++++++++++++++++ .../g++.target/riscv/rvv/base/vsmul_vx_rv64-2.C | 314 +++++++++++++++++++++ .../g++.target/riscv/rvv/base/vsmul_vx_rv64-3.C | 314 +++++++++++++++++++++ .../g++.target/riscv/rvv/base/vsmul_vx_tu_rv32-1.C | 157 +++++++++++ .../g++.target/riscv/rvv/base/vsmul_vx_tu_rv32-2.C | 157 +++++++++++ .../g++.target/riscv/rvv/base/vsmul_vx_tu_rv32-3.C | 157 +++++++++++ .../g++.target/riscv/rvv/base/vsmul_vx_tu_rv64-1.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vsmul_vx_tu_rv64-2.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vsmul_vx_tu_rv64-3.C | 160 +++++++++++ .../riscv/rvv/base/vsmul_vx_tum_rv32-1.C | 157 +++++++++++ .../riscv/rvv/base/vsmul_vx_tum_rv32-2.C | 157 +++++++++++ .../riscv/rvv/base/vsmul_vx_tum_rv32-3.C | 157 +++++++++++ .../riscv/rvv/base/vsmul_vx_tum_rv64-1.C | 160 +++++++++++ .../riscv/rvv/base/vsmul_vx_tum_rv64-2.C | 160 +++++++++++ .../riscv/rvv/base/vsmul_vx_tum_rv64-3.C | 160 +++++++++++ .../riscv/rvv/base/vsmul_vx_tumu_rv32-1.C | 157 +++++++++++ .../riscv/rvv/base/vsmul_vx_tumu_rv32-2.C | 157 +++++++++++ .../riscv/rvv/base/vsmul_vx_tumu_rv32-3.C | 157 +++++++++++ .../riscv/rvv/base/vsmul_vx_tumu_rv64-1.C | 160 +++++++++++ .../riscv/rvv/base/vsmul_vx_tumu_rv64-2.C | 160 +++++++++++ .../riscv/rvv/base/vsmul_vx_tumu_rv64-3.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vssra_vv-1.C | 314 +++++++++++++++++++++ .../g++.target/riscv/rvv/base/vssra_vv-2.C | 314 +++++++++++++++++++++ .../g++.target/riscv/rvv/base/vssra_vv-3.C | 314 +++++++++++++++++++++ .../g++.target/riscv/rvv/base/vssra_vv_mu-1.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vssra_vv_mu-2.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vssra_vv_mu-3.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vssra_vv_tu-1.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vssra_vv_tu-2.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vssra_vv_tu-3.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vssra_vv_tum-1.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vssra_vv_tum-2.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vssra_vv_tum-3.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vssra_vv_tumu-1.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vssra_vv_tumu-2.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vssra_vv_tumu-3.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vssra_vx-1.C | 314 +++++++++++++++++++++ .../g++.target/riscv/rvv/base/vssra_vx-2.C | 314 +++++++++++++++++++++ .../g++.target/riscv/rvv/base/vssra_vx-3.C | 314 +++++++++++++++++++++ .../g++.target/riscv/rvv/base/vssra_vx_mu-1.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vssra_vx_mu-2.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vssra_vx_mu-3.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vssra_vx_tu-1.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vssra_vx_tu-2.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vssra_vx_tu-3.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vssra_vx_tum-1.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vssra_vx_tum-2.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vssra_vx_tum-3.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vssra_vx_tumu-1.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vssra_vx_tumu-2.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vssra_vx_tumu-3.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vssrl_vv-1.C | 314 +++++++++++++++++++++ .../g++.target/riscv/rvv/base/vssrl_vv-2.C | 314 +++++++++++++++++++++ .../g++.target/riscv/rvv/base/vssrl_vv-3.C | 314 +++++++++++++++++++++ .../g++.target/riscv/rvv/base/vssrl_vv_mu-1.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vssrl_vv_mu-2.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vssrl_vv_mu-3.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vssrl_vv_tu-1.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vssrl_vv_tu-2.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vssrl_vv_tu-3.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vssrl_vv_tum-1.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vssrl_vv_tum-2.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vssrl_vv_tum-3.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vssrl_vv_tumu-1.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vssrl_vv_tumu-2.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vssrl_vv_tumu-3.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vssrl_vx-1.C | 314 +++++++++++++++++++++ .../g++.target/riscv/rvv/base/vssrl_vx-2.C | 314 +++++++++++++++++++++ .../g++.target/riscv/rvv/base/vssrl_vx-3.C | 314 +++++++++++++++++++++ .../g++.target/riscv/rvv/base/vssrl_vx_mu-1.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vssrl_vx_mu-2.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vssrl_vx_mu-3.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vssrl_vx_tu-1.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vssrl_vx_tu-2.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vssrl_vx_tu-3.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vssrl_vx_tum-1.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vssrl_vx_tum-2.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vssrl_vx_tum-3.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vssrl_vx_tumu-1.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vssrl_vx_tumu-2.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vssrl_vx_tumu-3.C | 160 +++++++++++ .../riscv/rvv/base/binop_vx_constraint-122.c | 21 ++ .../gcc.target/riscv/rvv/base/vaadd_vv-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vaadd_vv-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vaadd_vv-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vaadd_vv_m-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vaadd_vv_m-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vaadd_vv_m-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vaadd_vv_mu-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vaadd_vv_mu-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vaadd_vv_mu-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vaadd_vv_tu-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vaadd_vv_tu-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vaadd_vv_tu-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vaadd_vv_tum-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vaadd_vv_tum-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vaadd_vv_tum-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vaadd_vv_tumu-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vaadd_vv_tumu-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vaadd_vv_tumu-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vaadd_vx_m_rv32-1.c | 157 +++++++++++ .../gcc.target/riscv/rvv/base/vaadd_vx_m_rv32-2.c | 157 +++++++++++ .../gcc.target/riscv/rvv/base/vaadd_vx_m_rv32-3.c | 157 +++++++++++ .../gcc.target/riscv/rvv/base/vaadd_vx_m_rv64-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vaadd_vx_m_rv64-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vaadd_vx_m_rv64-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vaadd_vx_mu_rv32-1.c | 157 +++++++++++ .../gcc.target/riscv/rvv/base/vaadd_vx_mu_rv32-2.c | 157 +++++++++++ .../gcc.target/riscv/rvv/base/vaadd_vx_mu_rv32-3.c | 157 +++++++++++ .../gcc.target/riscv/rvv/base/vaadd_vx_mu_rv64-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vaadd_vx_mu_rv64-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vaadd_vx_mu_rv64-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vaadd_vx_rv32-1.c | 157 +++++++++++ .../gcc.target/riscv/rvv/base/vaadd_vx_rv32-2.c | 157 +++++++++++ .../gcc.target/riscv/rvv/base/vaadd_vx_rv32-3.c | 157 +++++++++++ .../gcc.target/riscv/rvv/base/vaadd_vx_rv64-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vaadd_vx_rv64-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vaadd_vx_rv64-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vaadd_vx_tu_rv32-1.c | 157 +++++++++++ .../gcc.target/riscv/rvv/base/vaadd_vx_tu_rv32-2.c | 157 +++++++++++ .../gcc.target/riscv/rvv/base/vaadd_vx_tu_rv32-3.c | 157 +++++++++++ .../gcc.target/riscv/rvv/base/vaadd_vx_tu_rv64-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vaadd_vx_tu_rv64-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vaadd_vx_tu_rv64-3.c | 160 +++++++++++ .../riscv/rvv/base/vaadd_vx_tum_rv32-1.c | 157 +++++++++++ .../riscv/rvv/base/vaadd_vx_tum_rv32-2.c | 157 +++++++++++ .../riscv/rvv/base/vaadd_vx_tum_rv32-3.c | 157 +++++++++++ .../riscv/rvv/base/vaadd_vx_tum_rv64-1.c | 160 +++++++++++ .../riscv/rvv/base/vaadd_vx_tum_rv64-2.c | 160 +++++++++++ .../riscv/rvv/base/vaadd_vx_tum_rv64-3.c | 160 +++++++++++ .../riscv/rvv/base/vaadd_vx_tumu_rv32-1.c | 157 +++++++++++ .../riscv/rvv/base/vaadd_vx_tumu_rv32-2.c | 157 +++++++++++ .../riscv/rvv/base/vaadd_vx_tumu_rv32-3.c | 157 +++++++++++ .../riscv/rvv/base/vaadd_vx_tumu_rv64-1.c | 160 +++++++++++ .../riscv/rvv/base/vaadd_vx_tumu_rv64-2.c | 160 +++++++++++ .../riscv/rvv/base/vaadd_vx_tumu_rv64-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vaaddu_vv-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vaaddu_vv-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vaaddu_vv-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vaaddu_vv_m-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vaaddu_vv_m-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vaaddu_vv_m-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vaaddu_vv_mu-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vaaddu_vv_mu-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vaaddu_vv_mu-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vaaddu_vv_tu-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vaaddu_vv_tu-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vaaddu_vv_tu-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vaaddu_vv_tum-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vaaddu_vv_tum-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vaaddu_vv_tum-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vaaddu_vv_tumu-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vaaddu_vv_tumu-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vaaddu_vv_tumu-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vaaddu_vx_m_rv32-1.c | 157 +++++++++++ .../gcc.target/riscv/rvv/base/vaaddu_vx_m_rv32-2.c | 157 +++++++++++ .../gcc.target/riscv/rvv/base/vaaddu_vx_m_rv32-3.c | 157 +++++++++++ .../gcc.target/riscv/rvv/base/vaaddu_vx_m_rv64-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vaaddu_vx_m_rv64-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vaaddu_vx_m_rv64-3.c | 160 +++++++++++ .../riscv/rvv/base/vaaddu_vx_mu_rv32-1.c | 157 +++++++++++ .../riscv/rvv/base/vaaddu_vx_mu_rv32-2.c | 157 +++++++++++ .../riscv/rvv/base/vaaddu_vx_mu_rv32-3.c | 157 +++++++++++ .../riscv/rvv/base/vaaddu_vx_mu_rv64-1.c | 160 +++++++++++ .../riscv/rvv/base/vaaddu_vx_mu_rv64-2.c | 160 +++++++++++ .../riscv/rvv/base/vaaddu_vx_mu_rv64-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vaaddu_vx_rv32-1.c | 157 +++++++++++ .../gcc.target/riscv/rvv/base/vaaddu_vx_rv32-2.c | 157 +++++++++++ .../gcc.target/riscv/rvv/base/vaaddu_vx_rv32-3.c | 157 +++++++++++ .../gcc.target/riscv/rvv/base/vaaddu_vx_rv64-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vaaddu_vx_rv64-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vaaddu_vx_rv64-3.c | 160 +++++++++++ .../riscv/rvv/base/vaaddu_vx_tu_rv32-1.c | 157 +++++++++++ .../riscv/rvv/base/vaaddu_vx_tu_rv32-2.c | 157 +++++++++++ .../riscv/rvv/base/vaaddu_vx_tu_rv32-3.c | 157 +++++++++++ .../riscv/rvv/base/vaaddu_vx_tu_rv64-1.c | 160 +++++++++++ .../riscv/rvv/base/vaaddu_vx_tu_rv64-2.c | 160 +++++++++++ .../riscv/rvv/base/vaaddu_vx_tu_rv64-3.c | 160 +++++++++++ .../riscv/rvv/base/vaaddu_vx_tum_rv32-1.c | 157 +++++++++++ .../riscv/rvv/base/vaaddu_vx_tum_rv32-2.c | 157 +++++++++++ .../riscv/rvv/base/vaaddu_vx_tum_rv32-3.c | 157 +++++++++++ .../riscv/rvv/base/vaaddu_vx_tum_rv64-1.c | 160 +++++++++++ .../riscv/rvv/base/vaaddu_vx_tum_rv64-2.c | 160 +++++++++++ .../riscv/rvv/base/vaaddu_vx_tum_rv64-3.c | 160 +++++++++++ .../riscv/rvv/base/vaaddu_vx_tumu_rv32-1.c | 157 +++++++++++ .../riscv/rvv/base/vaaddu_vx_tumu_rv32-2.c | 157 +++++++++++ .../riscv/rvv/base/vaaddu_vx_tumu_rv32-3.c | 157 +++++++++++ .../riscv/rvv/base/vaaddu_vx_tumu_rv64-1.c | 160 +++++++++++ .../riscv/rvv/base/vaaddu_vx_tumu_rv64-2.c | 160 +++++++++++ .../riscv/rvv/base/vaaddu_vx_tumu_rv64-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vasub_vv-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vasub_vv-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vasub_vv-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vasub_vv_m-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vasub_vv_m-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vasub_vv_m-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vasub_vv_mu-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vasub_vv_mu-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vasub_vv_mu-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vasub_vv_tu-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vasub_vv_tu-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vasub_vv_tu-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vasub_vv_tum-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vasub_vv_tum-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vasub_vv_tum-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vasub_vv_tumu-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vasub_vv_tumu-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vasub_vv_tumu-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vasub_vx_m_rv32-1.c | 157 +++++++++++ .../gcc.target/riscv/rvv/base/vasub_vx_m_rv32-2.c | 157 +++++++++++ .../gcc.target/riscv/rvv/base/vasub_vx_m_rv32-3.c | 157 +++++++++++ .../gcc.target/riscv/rvv/base/vasub_vx_m_rv64-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vasub_vx_m_rv64-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vasub_vx_m_rv64-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vasub_vx_mu_rv32-1.c | 157 +++++++++++ .../gcc.target/riscv/rvv/base/vasub_vx_mu_rv32-2.c | 157 +++++++++++ .../gcc.target/riscv/rvv/base/vasub_vx_mu_rv32-3.c | 157 +++++++++++ .../gcc.target/riscv/rvv/base/vasub_vx_mu_rv64-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vasub_vx_mu_rv64-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vasub_vx_mu_rv64-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vasub_vx_rv32-1.c | 157 +++++++++++ .../gcc.target/riscv/rvv/base/vasub_vx_rv32-2.c | 157 +++++++++++ .../gcc.target/riscv/rvv/base/vasub_vx_rv32-3.c | 157 +++++++++++ .../gcc.target/riscv/rvv/base/vasub_vx_rv64-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vasub_vx_rv64-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vasub_vx_rv64-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vasub_vx_tu_rv32-1.c | 157 +++++++++++ .../gcc.target/riscv/rvv/base/vasub_vx_tu_rv32-2.c | 157 +++++++++++ .../gcc.target/riscv/rvv/base/vasub_vx_tu_rv32-3.c | 157 +++++++++++ .../gcc.target/riscv/rvv/base/vasub_vx_tu_rv64-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vasub_vx_tu_rv64-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vasub_vx_tu_rv64-3.c | 160 +++++++++++ .../riscv/rvv/base/vasub_vx_tum_rv32-1.c | 157 +++++++++++ .../riscv/rvv/base/vasub_vx_tum_rv32-2.c | 157 +++++++++++ .../riscv/rvv/base/vasub_vx_tum_rv32-3.c | 157 +++++++++++ .../riscv/rvv/base/vasub_vx_tum_rv64-1.c | 160 +++++++++++ .../riscv/rvv/base/vasub_vx_tum_rv64-2.c | 160 +++++++++++ .../riscv/rvv/base/vasub_vx_tum_rv64-3.c | 160 +++++++++++ .../riscv/rvv/base/vasub_vx_tumu_rv32-1.c | 157 +++++++++++ .../riscv/rvv/base/vasub_vx_tumu_rv32-2.c | 157 +++++++++++ .../riscv/rvv/base/vasub_vx_tumu_rv32-3.c | 157 +++++++++++ .../riscv/rvv/base/vasub_vx_tumu_rv64-1.c | 160 +++++++++++ .../riscv/rvv/base/vasub_vx_tumu_rv64-2.c | 160 +++++++++++ .../riscv/rvv/base/vasub_vx_tumu_rv64-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vasubu_vv-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vasubu_vv-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vasubu_vv-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vasubu_vv_m-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vasubu_vv_m-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vasubu_vv_m-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vasubu_vv_mu-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vasubu_vv_mu-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vasubu_vv_mu-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vasubu_vv_tu-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vasubu_vv_tu-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vasubu_vv_tu-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vasubu_vv_tum-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vasubu_vv_tum-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vasubu_vv_tum-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vasubu_vv_tumu-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vasubu_vv_tumu-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vasubu_vv_tumu-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vasubu_vx_m_rv32-1.c | 157 +++++++++++ .../gcc.target/riscv/rvv/base/vasubu_vx_m_rv32-2.c | 157 +++++++++++ .../gcc.target/riscv/rvv/base/vasubu_vx_m_rv32-3.c | 157 +++++++++++ .../gcc.target/riscv/rvv/base/vasubu_vx_m_rv64-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vasubu_vx_m_rv64-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vasubu_vx_m_rv64-3.c | 160 +++++++++++ .../riscv/rvv/base/vasubu_vx_mu_rv32-1.c | 157 +++++++++++ .../riscv/rvv/base/vasubu_vx_mu_rv32-2.c | 157 +++++++++++ .../riscv/rvv/base/vasubu_vx_mu_rv32-3.c | 157 +++++++++++ .../riscv/rvv/base/vasubu_vx_mu_rv64-1.c | 160 +++++++++++ .../riscv/rvv/base/vasubu_vx_mu_rv64-2.c | 160 +++++++++++ .../riscv/rvv/base/vasubu_vx_mu_rv64-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vasubu_vx_rv32-1.c | 157 +++++++++++ .../gcc.target/riscv/rvv/base/vasubu_vx_rv32-2.c | 157 +++++++++++ .../gcc.target/riscv/rvv/base/vasubu_vx_rv32-3.c | 157 +++++++++++ .../gcc.target/riscv/rvv/base/vasubu_vx_rv64-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vasubu_vx_rv64-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vasubu_vx_rv64-3.c | 160 +++++++++++ .../riscv/rvv/base/vasubu_vx_tu_rv32-1.c | 157 +++++++++++ .../riscv/rvv/base/vasubu_vx_tu_rv32-2.c | 157 +++++++++++ .../riscv/rvv/base/vasubu_vx_tu_rv32-3.c | 157 +++++++++++ .../riscv/rvv/base/vasubu_vx_tu_rv64-1.c | 160 +++++++++++ .../riscv/rvv/base/vasubu_vx_tu_rv64-2.c | 160 +++++++++++ .../riscv/rvv/base/vasubu_vx_tu_rv64-3.c | 160 +++++++++++ .../riscv/rvv/base/vasubu_vx_tum_rv32-1.c | 157 +++++++++++ .../riscv/rvv/base/vasubu_vx_tum_rv32-2.c | 157 +++++++++++ .../riscv/rvv/base/vasubu_vx_tum_rv32-3.c | 157 +++++++++++ .../riscv/rvv/base/vasubu_vx_tum_rv64-1.c | 160 +++++++++++ .../riscv/rvv/base/vasubu_vx_tum_rv64-2.c | 160 +++++++++++ .../riscv/rvv/base/vasubu_vx_tum_rv64-3.c | 160 +++++++++++ .../riscv/rvv/base/vasubu_vx_tumu_rv32-1.c | 157 +++++++++++ .../riscv/rvv/base/vasubu_vx_tumu_rv32-2.c | 157 +++++++++++ .../riscv/rvv/base/vasubu_vx_tumu_rv32-3.c | 157 +++++++++++ .../riscv/rvv/base/vasubu_vx_tumu_rv64-1.c | 160 +++++++++++ .../riscv/rvv/base/vasubu_vx_tumu_rv64-2.c | 160 +++++++++++ .../riscv/rvv/base/vasubu_vx_tumu_rv64-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vnclip_wv-1.c | 111 ++++++++ .../gcc.target/riscv/rvv/base/vnclip_wv-2.c | 111 ++++++++ .../gcc.target/riscv/rvv/base/vnclip_wv-3.c | 111 ++++++++ .../gcc.target/riscv/rvv/base/vnclip_wv_m-1.c | 111 ++++++++ .../gcc.target/riscv/rvv/base/vnclip_wv_m-2.c | 111 ++++++++ .../gcc.target/riscv/rvv/base/vnclip_wv_m-3.c | 111 ++++++++ .../gcc.target/riscv/rvv/base/vnclip_wv_mu-1.c | 111 ++++++++ .../gcc.target/riscv/rvv/base/vnclip_wv_mu-2.c | 111 ++++++++ .../gcc.target/riscv/rvv/base/vnclip_wv_mu-3.c | 111 ++++++++ .../gcc.target/riscv/rvv/base/vnclip_wv_tu-1.c | 111 ++++++++ .../gcc.target/riscv/rvv/base/vnclip_wv_tu-2.c | 111 ++++++++ .../gcc.target/riscv/rvv/base/vnclip_wv_tu-3.c | 111 ++++++++ .../gcc.target/riscv/rvv/base/vnclip_wv_tum-1.c | 111 ++++++++ .../gcc.target/riscv/rvv/base/vnclip_wv_tum-2.c | 111 ++++++++ .../gcc.target/riscv/rvv/base/vnclip_wv_tum-3.c | 111 ++++++++ .../gcc.target/riscv/rvv/base/vnclip_wv_tumu-1.c | 111 ++++++++ .../gcc.target/riscv/rvv/base/vnclip_wv_tumu-2.c | 111 ++++++++ .../gcc.target/riscv/rvv/base/vnclip_wv_tumu-3.c | 111 ++++++++ .../gcc.target/riscv/rvv/base/vnclip_wx-1.c | 111 ++++++++ .../gcc.target/riscv/rvv/base/vnclip_wx-2.c | 111 ++++++++ .../gcc.target/riscv/rvv/base/vnclip_wx-3.c | 111 ++++++++ .../gcc.target/riscv/rvv/base/vnclip_wx_m-1.c | 111 ++++++++ .../gcc.target/riscv/rvv/base/vnclip_wx_m-2.c | 111 ++++++++ .../gcc.target/riscv/rvv/base/vnclip_wx_m-3.c | 111 ++++++++ .../gcc.target/riscv/rvv/base/vnclip_wx_mu-1.c | 111 ++++++++ .../gcc.target/riscv/rvv/base/vnclip_wx_mu-2.c | 111 ++++++++ .../gcc.target/riscv/rvv/base/vnclip_wx_mu-3.c | 111 ++++++++ .../gcc.target/riscv/rvv/base/vnclip_wx_tu-1.c | 111 ++++++++ .../gcc.target/riscv/rvv/base/vnclip_wx_tu-2.c | 111 ++++++++ .../gcc.target/riscv/rvv/base/vnclip_wx_tu-3.c | 111 ++++++++ .../gcc.target/riscv/rvv/base/vnclip_wx_tum-1.c | 111 ++++++++ .../gcc.target/riscv/rvv/base/vnclip_wx_tum-2.c | 111 ++++++++ .../gcc.target/riscv/rvv/base/vnclip_wx_tum-3.c | 111 ++++++++ .../gcc.target/riscv/rvv/base/vnclip_wx_tumu-1.c | 111 ++++++++ .../gcc.target/riscv/rvv/base/vnclip_wx_tumu-2.c | 111 ++++++++ .../gcc.target/riscv/rvv/base/vnclip_wx_tumu-3.c | 111 ++++++++ .../gcc.target/riscv/rvv/base/vnclipu_wv-1.c | 111 ++++++++ .../gcc.target/riscv/rvv/base/vnclipu_wv-2.c | 111 ++++++++ .../gcc.target/riscv/rvv/base/vnclipu_wv-3.c | 111 ++++++++ .../gcc.target/riscv/rvv/base/vnclipu_wv_m-1.c | 111 ++++++++ .../gcc.target/riscv/rvv/base/vnclipu_wv_m-2.c | 111 ++++++++ .../gcc.target/riscv/rvv/base/vnclipu_wv_m-3.c | 111 ++++++++ .../gcc.target/riscv/rvv/base/vnclipu_wv_mu-1.c | 111 ++++++++ .../gcc.target/riscv/rvv/base/vnclipu_wv_mu-2.c | 111 ++++++++ .../gcc.target/riscv/rvv/base/vnclipu_wv_mu-3.c | 111 ++++++++ .../gcc.target/riscv/rvv/base/vnclipu_wv_tu-1.c | 111 ++++++++ .../gcc.target/riscv/rvv/base/vnclipu_wv_tu-2.c | 111 ++++++++ .../gcc.target/riscv/rvv/base/vnclipu_wv_tu-3.c | 111 ++++++++ .../gcc.target/riscv/rvv/base/vnclipu_wv_tum-1.c | 111 ++++++++ .../gcc.target/riscv/rvv/base/vnclipu_wv_tum-2.c | 111 ++++++++ .../gcc.target/riscv/rvv/base/vnclipu_wv_tum-3.c | 111 ++++++++ .../gcc.target/riscv/rvv/base/vnclipu_wv_tumu-1.c | 111 ++++++++ .../gcc.target/riscv/rvv/base/vnclipu_wv_tumu-2.c | 111 ++++++++ .../gcc.target/riscv/rvv/base/vnclipu_wv_tumu-3.c | 111 ++++++++ .../gcc.target/riscv/rvv/base/vnclipu_wx-1.c | 111 ++++++++ .../gcc.target/riscv/rvv/base/vnclipu_wx-2.c | 111 ++++++++ .../gcc.target/riscv/rvv/base/vnclipu_wx-3.c | 111 ++++++++ .../gcc.target/riscv/rvv/base/vnclipu_wx_m-1.c | 111 ++++++++ .../gcc.target/riscv/rvv/base/vnclipu_wx_m-2.c | 111 ++++++++ .../gcc.target/riscv/rvv/base/vnclipu_wx_m-3.c | 111 ++++++++ .../gcc.target/riscv/rvv/base/vnclipu_wx_mu-1.c | 111 ++++++++ .../gcc.target/riscv/rvv/base/vnclipu_wx_mu-2.c | 111 ++++++++ .../gcc.target/riscv/rvv/base/vnclipu_wx_mu-3.c | 111 ++++++++ .../gcc.target/riscv/rvv/base/vnclipu_wx_tu-1.c | 111 ++++++++ .../gcc.target/riscv/rvv/base/vnclipu_wx_tu-2.c | 111 ++++++++ .../gcc.target/riscv/rvv/base/vnclipu_wx_tu-3.c | 111 ++++++++ .../gcc.target/riscv/rvv/base/vnclipu_wx_tum-1.c | 111 ++++++++ .../gcc.target/riscv/rvv/base/vnclipu_wx_tum-2.c | 111 ++++++++ .../gcc.target/riscv/rvv/base/vnclipu_wx_tum-3.c | 111 ++++++++ .../gcc.target/riscv/rvv/base/vnclipu_wx_tumu-1.c | 111 ++++++++ .../gcc.target/riscv/rvv/base/vnclipu_wx_tumu-2.c | 111 ++++++++ .../gcc.target/riscv/rvv/base/vnclipu_wx_tumu-3.c | 111 ++++++++ .../gcc.target/riscv/rvv/base/vsmul_vv-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vsmul_vv-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vsmul_vv-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vsmul_vv_m-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vsmul_vv_m-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vsmul_vv_m-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vsmul_vv_mu-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vsmul_vv_mu-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vsmul_vv_mu-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vsmul_vv_tu-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vsmul_vv_tu-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vsmul_vv_tu-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vsmul_vv_tum-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vsmul_vv_tum-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vsmul_vv_tum-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vsmul_vv_tumu-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vsmul_vv_tumu-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vsmul_vv_tumu-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vsmul_vx_m_rv32-1.c | 157 +++++++++++ .../gcc.target/riscv/rvv/base/vsmul_vx_m_rv32-2.c | 157 +++++++++++ .../gcc.target/riscv/rvv/base/vsmul_vx_m_rv32-3.c | 157 +++++++++++ .../gcc.target/riscv/rvv/base/vsmul_vx_m_rv64-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vsmul_vx_m_rv64-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vsmul_vx_m_rv64-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vsmul_vx_mu_rv32-1.c | 157 +++++++++++ .../gcc.target/riscv/rvv/base/vsmul_vx_mu_rv32-2.c | 157 +++++++++++ .../gcc.target/riscv/rvv/base/vsmul_vx_mu_rv32-3.c | 157 +++++++++++ .../gcc.target/riscv/rvv/base/vsmul_vx_mu_rv64-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vsmul_vx_mu_rv64-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vsmul_vx_mu_rv64-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vsmul_vx_rv32-1.c | 157 +++++++++++ .../gcc.target/riscv/rvv/base/vsmul_vx_rv32-2.c | 157 +++++++++++ .../gcc.target/riscv/rvv/base/vsmul_vx_rv32-3.c | 157 +++++++++++ .../gcc.target/riscv/rvv/base/vsmul_vx_rv64-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vsmul_vx_rv64-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vsmul_vx_rv64-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vsmul_vx_tu_rv32-1.c | 157 +++++++++++ .../gcc.target/riscv/rvv/base/vsmul_vx_tu_rv32-2.c | 157 +++++++++++ .../gcc.target/riscv/rvv/base/vsmul_vx_tu_rv32-3.c | 157 +++++++++++ .../gcc.target/riscv/rvv/base/vsmul_vx_tu_rv64-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vsmul_vx_tu_rv64-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vsmul_vx_tu_rv64-3.c | 160 +++++++++++ .../riscv/rvv/base/vsmul_vx_tum_rv32-1.c | 157 +++++++++++ .../riscv/rvv/base/vsmul_vx_tum_rv32-2.c | 157 +++++++++++ .../riscv/rvv/base/vsmul_vx_tum_rv32-3.c | 157 +++++++++++ .../riscv/rvv/base/vsmul_vx_tum_rv64-1.c | 160 +++++++++++ .../riscv/rvv/base/vsmul_vx_tum_rv64-2.c | 160 +++++++++++ .../riscv/rvv/base/vsmul_vx_tum_rv64-3.c | 160 +++++++++++ .../riscv/rvv/base/vsmul_vx_tumu_rv32-1.c | 157 +++++++++++ .../riscv/rvv/base/vsmul_vx_tumu_rv32-2.c | 157 +++++++++++ .../riscv/rvv/base/vsmul_vx_tumu_rv32-3.c | 157 +++++++++++ .../riscv/rvv/base/vsmul_vx_tumu_rv64-1.c | 160 +++++++++++ .../riscv/rvv/base/vsmul_vx_tumu_rv64-2.c | 160 +++++++++++ .../riscv/rvv/base/vsmul_vx_tumu_rv64-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssra_vv-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssra_vv-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssra_vv-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssra_vv_m-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssra_vv_m-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssra_vv_m-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssra_vv_mu-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssra_vv_mu-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssra_vv_mu-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssra_vv_tu-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssra_vv_tu-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssra_vv_tu-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssra_vv_tum-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssra_vv_tum-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssra_vv_tum-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssra_vv_tumu-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssra_vv_tumu-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssra_vv_tumu-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssra_vx-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssra_vx-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssra_vx-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssra_vx_m-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssra_vx_m-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssra_vx_m-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssra_vx_mu-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssra_vx_mu-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssra_vx_mu-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssra_vx_tu-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssra_vx_tu-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssra_vx_tu-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssra_vx_tum-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssra_vx_tum-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssra_vx_tum-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssra_vx_tumu-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssra_vx_tumu-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssra_vx_tumu-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssrl_vv-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssrl_vv-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssrl_vv-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssrl_vv_m-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssrl_vv_m-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssrl_vv_m-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssrl_vv_mu-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssrl_vv_mu-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssrl_vv_mu-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssrl_vv_tu-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssrl_vv_tu-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssrl_vv_tu-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssrl_vv_tum-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssrl_vv_tum-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssrl_vv_tum-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssrl_vv_tumu-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssrl_vv_tumu-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssrl_vv_tumu-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssrl_vx-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssrl_vx-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssrl_vx-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssrl_vx_m-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssrl_vx_m-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssrl_vx_m-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssrl_vx_mu-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssrl_vx_mu-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssrl_vx_mu-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssrl_vx_tu-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssrl_vx_tu-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssrl_vx_tu-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssrl_vx_tum-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssrl_vx_tum-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssrl_vx_tum-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssrl_vx_tumu-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssrl_vx_tumu-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssrl_vx_tumu-3.c | 160 +++++++++++ 765 files changed, 124837 insertions(+), 13 deletions(-) create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vv-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vv-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vv-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vv_mu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vv_mu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vv_mu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vv_tu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vv_tu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vv_tu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vv_tum-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vv_tum-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vv_tum-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vv_tumu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vv_tumu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vv_tumu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_mu_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_mu_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_mu_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_mu_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_mu_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_mu_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_tu_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_tu_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_tu_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_tu_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_tu_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_tu_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_tum_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_tum_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_tum_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_tum_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_tum_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_tum_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_tumu_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_tumu_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_tumu_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_tumu_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_tumu_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_tumu_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaaddu_vv-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaaddu_vv-2.C create mode 100644 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gcc/testsuite/g++.target/riscv/rvv/base/vaaddu_vx_mu_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaaddu_vx_mu_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaaddu_vx_mu_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaaddu_vx_mu_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaaddu_vx_mu_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaaddu_vx_mu_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaaddu_vx_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaaddu_vx_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaaddu_vx_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaaddu_vx_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaaddu_vx_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaaddu_vx_rv64-3.C create mode 100644 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gcc/testsuite/gcc.target/riscv/rvv/base/vssrl_vx_mu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssrl_vx_tu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssrl_vx_tu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssrl_vx_tu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssrl_vx_tum-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssrl_vx_tum-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssrl_vx_tum-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssrl_vx_tumu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssrl_vx_tumu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssrl_vx_tumu-3.c -- To stop receiving notification emails like this one, please contact the administrator of this repository.

2 years, 3 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/gnu-master-arm-next-defconfig updated (c620c4575b -> 2cfd01833f)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-master-arm-next-defconfig in repository toolchain/ci/base-artifacts. from c620c4575b 45: onsuccess: #470: boot: Success after binutils/gcc/linux/ [...] new 2cfd01833f 46: onsuccess: #471: boot: Success after binutils/gcc/linux/ [...] The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log.xz | Bin 1772 -> 1772 bytes 02-prepare_abe/console.log.xz | Bin 2768 -> 2776 bytes 03-build_abe-binutils/console.log.xz | Bin 31072 -> 31240 bytes 04-build_abe-stage1/console.log.xz | Bin 92156 -> 91428 bytes 05-build_abe-qemu/console.log.xz | Bin 31736 -> 31332 bytes 06-build_linux/console.log.xz | Bin 5504 -> 5508 bytes 07-boot_linux/console.log.xz | Bin 5676 -> 5688 bytes 08-check_regression/console.log.xz | Bin 4408 -> 4280 bytes 08-check_regression/mail-body.txt | 4 ++-- dashboard/dashboard-generate.sh | 2 +- git/binutils_rev | 2 +- git/gcc_rev | 2 +- git/linux_rev | 2 +- git/qemu_rev | 2 +- mail/jira-body.txt | 2 +- mail/mail-body.txt | 6 +++--- mail/mail-subject.txt | 2 +- manifest.sh | 32 ++++++++++++++++---------------- results | 2 +- 19 files changed, 29 insertions(+), 29 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

2 years, 3 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_gnu_native_check_gcc/master-aarch64 updated (00d7d26a8b -> 98c835e13f)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_gnu_native_check_gcc/master-aarch64 in repository toolchain/ci/base-artifacts. discards 00d7d26a8b 184: onsuccess: #936: 1: Success after binutils/gcc/linux/gl [...] discards 9683728ce2 183: onsuccess: #935: 1: Success after binutils/gcc/linux/gl [...] discards 7c5bf03068 182: onsuccess: #933: 1: Success after binutils/gcc/linux/gl [...] discards 9e1eb0ba20 181: onsuccess: #932: 1: Success after binutils/gcc/linux/gl [...] discards 1c6e3018c6 180: onsuccess: #931: 1: Success after binutils/gcc/linux/gl [...] discards 7b5d9fec79 179: onsuccess: #930: 1: Success after binutils/gcc/linux/gl [...] discards 1d9c0392b2 178: onsuccess: #929: 1: Success after binutils/gcc/linux/gl [...] discards e5e2560252 177: onsuccess: #928: 1: Success after binutils/gcc/linux/gl [...] discards 21f8e1c84a 176: onsuccess: #927: 1: Success after binutils/gcc/linux/gl [...] discards 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binutils/gcc/linux/gl [...] new 3d336a4b84 184: onsuccess: #936: 1: Success after binutils/gcc/linux/gl [...] new 98c835e13f 185: onsuccess: #937: 1: Success after binutils/gcc/linux/gd [...] This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (00d7d26a8b) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_gnu_native_check_gcc/mas [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 102 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log.xz | Bin 1768 -> 1772 bytes 02-prepare_abe/console.log.xz | Bin 2756 -> 2756 bytes 03-build_abe-binutils/console.log.xz | Bin 39080 -> 39160 bytes 04-build_abe-gcc/console.log.xz | Bin 213524 -> 214260 bytes 05-clean_sysroot/console.log.xz | Bin 312 -> 312 bytes 06-build_abe-linux/console.log.xz | Bin 8640 -> 8604 bytes 07-build_abe-glibc/console.log.xz | Bin 244412 -> 244796 bytes 08-build_abe-gdb/console.log.xz | Bin 38624 -> 38676 bytes 09-build_abe-dejagnu/console.log.xz | Bin 3832 -> 3836 bytes 10-build_abe-check_gcc/console.log.xz | Bin 2564 -> 2684 bytes 11-check_regression/console.log.xz | Bin 7092 -> 6104 bytes 11-check_regression/results.compare | 30 +- 11-check_regression/results.compare2 | 129 +- 12-update_baseline/console.log | 34 +- dashboard/dashboard-generate.sh | 2 +- git/binutils_rev | 2 +- git/gcc_rev | 2 +- git/gdb_rev | 2 +- git/linux_rev | 2 +- mail/jira-body.txt | 2 +- mail/mail-body.txt | 2 +- mail/mail-subject.txt | 2 +- manifest.sh | 32 +- sumfiles/g++.log.xz | Bin 3710168 -> 3747324 bytes sumfiles/g++.sum | 132 +- sumfiles/gcc.log.xz | Bin 3258232 -> 3230580 bytes sumfiles/gcc.sum | 5107 +++++++++++++++++---------------- sumfiles/gfortran.log.xz | Bin 1075400 -> 1083340 bytes sumfiles/gfortran.sum | 42 +- sumfiles/libatomic.log.xz | Bin 2280 -> 2272 bytes sumfiles/libatomic.sum | 4 +- sumfiles/libgomp.log.xz | Bin 235388 -> 235244 bytes sumfiles/libgomp.sum | 16 +- sumfiles/libitm.log.xz | Bin 2676 -> 2664 bytes sumfiles/libitm.sum | 6 +- sumfiles/libstdc++.log.xz | Bin 456128 -> 457904 bytes sumfiles/libstdc++.sum | 10 +- 37 files changed, 2735 insertions(+), 2823 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

2 years, 3 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_bmk-code_speed-spec2k6/gnu-aarch64-master-O2 updated (f3554652e3 -> bdf5805493)

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This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_bmk-code_speed-spec2k6/gnu-aarch64-master-O2 in repository toolchain/ci/base-artifacts. from f3554652e3 47: onsuccess: #21: 1: [TCWG CI] No change after binutils/gc [...] new bdf5805493 48: onsuccess: #25: 1: [TCWG CI] No change after glibc: 7 commits The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log.xz | Bin 2004 -> 1836 bytes 02-prepare_abe/console.log.xz | Bin 2772 -> 2768 bytes 03-build_abe-binutils/console.log.xz | Bin 31888 -> 32020 bytes 04-build_abe-stage1/console.log.xz | Bin 73988 -> 75060 bytes 06-build_abe-linux/console.log.xz | Bin 8668 -> 8796 bytes 07-build_abe-glibc/console.log.xz | Bin 247676 -> 246840 bytes 08-build_abe-stage2/console.log.xz | Bin 187760 -> 184536 bytes 09-benchmark/benchmark-build.log | 124 +- 09-benchmark/benchmark.log | 122 +- 09-benchmark/console.log.xz | Bin 3864 -> 3856 bytes 10-check_regression/console.log.xz | Bin 17852 -> 16764 bytes .../csv-results-vs-first-0/md5sum.csv | 2864 +- .../csv-results-vs-first-0/results.csv | 264044 ++++----- .../csv-results-vs-first-0/size.csv | 488244 ++++++++-------- 10-check_regression/csv-results-vs-first-0/sve.csv | 29008 +- .../csv-results-vs-first-0/vect.csv | 460 +- .../csv-results-vs-first-1/md5sum.csv | 2603 +- .../csv-results-vs-first-1/perf.csv | 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dashboard/squad-vs-first/Mean/results-metrics.json | 2 +- dashboard/squad-vs-first/dashboard-push-squad.sh | 122 +- git/glibc_rev | 2 +- mail/jira-body.txt | 32 +- mail/mail-body.txt | 32 +- mail/mail-subject.txt | 2 +- manifest.sh | 27 +- results_id | 2 +- save-temps/400.perlbench.tar.xz | Bin 2549756 -> 1281720 bytes save-temps/401.bzip2.tar.xz | Bin 234492 -> 94476 bytes save-temps/403.gcc.tar.xz | Bin 6843768 -> 3567072 bytes save-temps/410.bwaves.tar.xz | Bin 47844 -> 15100 bytes save-temps/416.gamess.tar.xz | Bin 13817220 -> 4210492 bytes save-temps/429.mcf.tar.xz | Bin 69628 -> 36580 bytes save-temps/433.milc.tar.xz | Bin 333244 -> 167760 bytes save-temps/434.zeusmp.tar.xz | Bin 428176 -> 126512 bytes save-temps/435.gromacs.tar.xz | Bin 2111148 -> 979240 bytes save-temps/436.cactusADM.tar.xz | Bin 1524620 -> 725464 bytes save-temps/437.leslie3d.tar.xz | Bin 151400 -> 46336 bytes save-temps/444.namd.tar.xz | Bin 486200 -> 168352 bytes save-temps/445.gobmk.tar.xz | Bin 2490084 -> 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insertions(+), 1972181 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

2 years, 3 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_gnu_native_fast_check_gdb/master-arm updated (7a0df0ad08 -> ff29af20eb)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_gnu_native_fast_check_gdb/master-arm in repository toolchain/ci/base-artifacts. from 7a0df0ad08 94: onsuccess: #104: 1: Success after binutils/gcc/linux/gli [...] new ff29af20eb 95: onsuccess: #105: 1: Success after binutils/gcc/linux/gdb [...] The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log.xz | Bin 1736 -> 1752 bytes 02-prepare_abe/console.log.xz | Bin 2740 -> 2748 bytes 03-build_abe-binutils/console.log.xz | Bin 52136 -> 51840 bytes 04-build_abe-gcc/console.log.xz | Bin 237516 -> 236696 bytes 05-clean_sysroot/console.log.xz | Bin 316 -> 316 bytes 06-build_abe-linux/console.log.xz | Bin 8632 -> 8612 bytes 07-build_abe-glibc/console.log.xz | Bin 235824 -> 236104 bytes 08-build_abe-gdb/console.log.xz | Bin 50548 -> 50348 bytes 09-build_abe-dejagnu/console.log.xz | Bin 3820 -> 3820 bytes 10-build_abe-check_gdb/console.log.xz | Bin 3144 -> 2712 bytes 11-check_regression/console.log.xz | Bin 6052 -> 5664 bytes 11-check_regression/results.compare | 4 ++-- 11-check_regression/results.compare2 | 6 +++--- dashboard/dashboard-generate.sh | 2 +- git/binutils_rev | 2 +- git/gcc_rev | 2 +- git/gdb_rev | 2 +- git/linux_rev | 2 +- mail/jira-body.txt | 2 +- mail/mail-body.txt | 2 +- mail/mail-subject.txt | 2 +- manifest.sh | 32 ++++++++++++++++---------------- sumfiles/gdb.log.xz | Bin 11932 -> 11924 bytes sumfiles/gdb.sum | 30 +++++++++++++++--------------- 24 files changed, 44 insertions(+), 44 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

2 years, 3 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_gnu_native_fast_check_gdb/master-aarch64 updated (1156b94dc1 -> d5b843335c)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_gnu_native_fast_check_gdb/master-aarch64 in repository toolchain/ci/base-artifacts. from 1156b94dc1 95: onsuccess: #109: 1: Success after binutils/gcc/linux/gli [...] new d5b843335c 96: onsuccess: #110: 1: Success after binutils/gcc/linux/gdb [...] The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log.xz | Bin 1784 -> 1776 bytes 02-prepare_abe/console.log.xz | Bin 2748 -> 2760 bytes 03-build_abe-binutils/console.log.xz | Bin 39080 -> 39560 bytes 04-build_abe-gcc/console.log.xz | Bin 213076 -> 216252 bytes 05-clean_sysroot/console.log.xz | Bin 312 -> 312 bytes 06-build_abe-linux/console.log.xz | Bin 8632 -> 8680 bytes 07-build_abe-glibc/console.log.xz | Bin 244948 -> 246808 bytes 08-build_abe-gdb/console.log.xz | Bin 38748 -> 39040 bytes 09-build_abe-dejagnu/console.log.xz | Bin 3856 -> 3852 bytes 10-build_abe-check_gdb/console.log.xz | Bin 2872 -> 2716 bytes 11-check_regression/console.log.xz | Bin 5944 -> 5672 bytes 11-check_regression/results.compare | 4 ++-- 11-check_regression/results.compare2 | 6 +++--- dashboard/dashboard-generate.sh | 2 +- git/binutils_rev | 2 +- git/gcc_rev | 2 +- git/gdb_rev | 2 +- git/linux_rev | 2 +- mail/jira-body.txt | 2 +- mail/mail-body.txt | 2 +- mail/mail-subject.txt | 2 +- manifest.sh | 32 ++++++++++++++++---------------- sumfiles/gdb.log.xz | Bin 11912 -> 11904 bytes sumfiles/gdb.sum | 30 +++++++++++++++--------------- 24 files changed, 44 insertions(+), 44 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

2 years, 3 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_gnu_native_check_gdb/master-arm updated (f9be660d12 -> f5306123f1)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_gnu_native_check_gdb/master-arm in repository toolchain/ci/base-artifacts. discards f9be660d12 186: onsuccess: #680: 1: Success after binutils/gcc/linux/gl [...] discards 5c23bb135c 185: onsuccess: #679: 1: Success after binutils/gcc/linux/gl [...] discards 0cf1965f3d 184: onsuccess: #678: 1: Success after binutils/gcc/glibc/gd [...] discards 93c26e8618 183: onsuccess: #677: 1: Success after binutils/gcc/linux/gl [...] discards 94355080db 182: onsuccess: #676: 1: Success after binutils/gcc/linux/gl [...] discards bb55f5b378 181: onsuccess: #675: 1: Success after binutils/gcc/linux/gl [...] discards 6a48e2de0f 180: onsuccess: #674: 1: Success after binutils/gcc/linux/gd [...] discards 9e522e1d30 179: onsuccess: #673: 1: Success after binutils/gcc/linux/gl [...] discards 35bc50a0ad 178: onsuccess: #672: 1: Success after binutils/gcc/linux/gl [...] discards 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That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (f9be660d12) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_gnu_native_check_gdb/mas [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 102 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log.xz | Bin 1752 -> 1748 bytes 02-prepare_abe/console.log.xz | Bin 2756 -> 2740 bytes 03-build_abe-binutils/console.log.xz | Bin 52280 -> 52064 bytes 04-build_abe-gcc/console.log.xz | Bin 238164 -> 238704 bytes 05-clean_sysroot/console.log.xz | Bin 316 -> 316 bytes 06-build_abe-linux/console.log.xz | Bin 8652 -> 8580 bytes 07-build_abe-glibc/console.log.xz | Bin 236592 -> 236480 bytes 08-build_abe-gdb/console.log.xz | Bin 51408 -> 51272 bytes 09-build_abe-dejagnu/console.log.xz | Bin 3872 -> 3836 bytes 10-build_abe-check_gdb/console.log.xz | Bin 2500 -> 2436 bytes 11-check_regression/console.log.xz | Bin 14160 -> 17384 bytes 11-check_regression/extra-bisect-params | 2 +- 11-check_regression/fails.sum | 47 +- 11-check_regression/mail-body.txt | 199 +- 11-check_regression/results.compare | 81 +- 11-check_regression/results.compare2 | 5543 +++++++++++------- 11-check_regression/results.regressions | 81 +- 12-update_baseline/console.log | 66 +- dashboard/dashboard-generate.sh | 2 +- git/binutils_rev | 2 +- git/gcc_rev | 2 +- git/gdb_rev | 2 +- git/linux_rev | 2 +- mail/jira-body.txt | 2 +- mail/mail-body.txt | 201 +- mail/mail-subject.txt | 2 +- manifest.sh | 32 +- results | 81 +- sumfiles/gdb.log.xz | Bin 2842152 -> 2838140 bytes sumfiles/gdb.sum | 9468 ++++++++++++++++++------------- 30 files changed, 9445 insertions(+), 6370 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

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Tcwg-commits February 2023