Tcwg-commits February 2023

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[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_gcc_check_bootstrap/master-aarch64-check_bootstrap updated (fedc81df9f -> 2d47774d22)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_gcc_check_bootstrap/master-aarch64-check_bootstrap in repository toolchain/ci/base-artifacts. discards fedc81df9f 170: onsuccess: #717: 1: Success after binutils/gcc: 121 commits discards 9e47885181 169: onsuccess: #715: 1: Success after binutils/gcc: 18 commits discards 1d59d2ea66 168: onsuccess: #714: 1: Success after binutils/gcc: 23 commits discards b364e13118 167: onsuccess: #713: 1: Success after binutils/gcc: 13 commits discards a30d6e4359 166: onsuccess: #712: 1: Success after binutils/gcc: 87 commits discards 186d25af40 165: onsuccess: #711: 1: Success after binutils/gcc: 47 commits discards 3e25679509 164: onsuccess: #710: 1: Success after binutils/gcc: 146 commits discards a48d9e71ce 163: onsuccess: #709: 1: Success after binutils/gcc: 22 commits discards 06ffd25463 162: onsuccess: #708: 1: Success after binutils/gcc: 67 commits discards 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That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (fedc81df9f) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_gcc_check_bootstrap/mast [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 102 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log.xz | Bin 1768 -> 1764 bytes 02-prepare_abe/console.log.xz | Bin 2756 -> 2756 bytes 03-build_abe-binutils/console.log.xz | Bin 39692 -> 38620 bytes 04-build_abe-bootstrap/console.log.xz | Bin 272916 -> 272244 bytes 05-build_abe-dejagnu/console.log.xz | Bin 3840 -> 3840 bytes 06-build_abe-check_bootstrap/console.log.xz | Bin 2772 -> 2484 bytes 07-check_regression/console.log.xz | Bin 8288 -> 5308 bytes 07-check_regression/results.compare | 19 - 07-check_regression/results.compare2 | 699 +--- 08-update_baseline/console.log | 36 +- dashboard/dashboard-generate.sh | 2 +- git/binutils_rev | 2 +- git/gcc_rev | 2 +- mail/jira-body.txt | 2 +- mail/mail-body.txt | 2 +- mail/mail-subject.txt | 2 +- manifest.sh | 18 +- sumfiles/g++.log.xz | Bin 3641176 -> 3686344 bytes sumfiles/g++.sum | 46 +- sumfiles/gcc.log.xz | Bin 3232656 -> 3217604 bytes sumfiles/gcc.sum | 4561 ++++++++++++++------------- sumfiles/gfortran.log.xz | Bin 1089868 -> 1095096 bytes sumfiles/gfortran.sum | 4 +- sumfiles/libatomic.log.xz | Bin 2352 -> 2352 bytes sumfiles/libatomic.sum | 2 +- sumfiles/libgomp.log.xz | Bin 228444 -> 228744 bytes sumfiles/libgomp.sum | 2 +- sumfiles/libitm.log.xz | Bin 2732 -> 2724 bytes sumfiles/libitm.sum | 2 +- sumfiles/libstdc++.log.xz | Bin 477012 -> 473152 bytes sumfiles/libstdc++.sum | 2 +- 31 files changed, 2378 insertions(+), 3025 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

1 year, 9 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_gcc_bootstrap/master-arm-bootstrap updated (a6ee411dc9 -> 870410bd4e)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_gcc_bootstrap/master-arm-bootstrap in repository toolchain/ci/base-artifacts. discards a6ee411dc9 544: onsuccess: #1977: 2: Success after binutils/gcc: 17 commits discards 575a65d958 543: onsuccess: #1976: 2: Success after binutils/gcc: 61 commits discards 81b18b70a8 542: onsuccess: #1975: 2: Success after binutils/gcc: 9 commits discards 6e9030081f 541: onsuccess: #1974: 2: Success after binutils/gcc: 11 commits discards e06ec81e45 540: onsuccess: #1973: 2: Success after binutils/gcc: 39 commits discards 9940ed8902 539: onsuccess: #1972: 2: Success after binutils/gcc: 16 commits discards 40e45edc5a 538: onsuccess: #1971: 2: Success after binutils/gcc: 23 commits discards 2d5204db70 537: onsuccess: #1970: 2: Success after binutils/gcc: 7 commits discards cdfecfa3ff 536: onsuccess: #1969: 2: Success after binutils/gcc: 8 commits discards bc3e714167 535: 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Summary of changes: 01-reset_artifacts/console.log.xz | Bin 1732 -> 1732 bytes 02-prepare_abe/console.log.xz | Bin 2756 -> 2756 bytes 04-build_abe-binutils/console.log.xz | Bin 52512 -> 52288 bytes 05-build_abe-bootstrap/console.log.xz | Bin 472352 -> 472548 bytes 06-check_regression/console.log.xz | Bin 2920 -> 2976 bytes 07-update_baseline/console.log | 38 +++++++++++++++++----------------- dashboard/dashboard-generate.sh | 2 +- git/binutils_rev | 2 +- git/gcc_rev | 2 +- mail/jira-body.txt | 2 +- mail/mail-body.txt | 2 +- mail/mail-subject.txt | 2 +- manifest.sh | 18 ++++++++-------- 13 files changed, 34 insertions(+), 34 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

1 year, 9 months

[gcc] branch master updated (064a2d53a38 -> 74595dd5181)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository gcc. from 064a2d53a38 RISC-V: Add vsadd.vx C++ overloaded API tests new 99fa5d94c41 RISC-V: Add vsext/vzext C/C++ intrinsic support new a2da134248b RISC-V: Add vzext.vf8 C API tests new 1d66166b0f7 RISC-V: Add vzext.vf4 C API tests new 91d0120e389 RISC-V: Add vzext.vf2 C API tests new decfa1d5bc5 RISC-V: Add vsext.vf8 C API tests new 42666defc0d RISC-V: Add vsext.vf4 C API tests new 7d2c4a6f07e RISC-V: Add vsext.vf2 C API tests new 00c93929571 RISC-V: Add vsext constraint tests new 221f26c9624 RISC-V: Add vzext.vf8 C++ API tests new 522d385831b RISC-V: Add vzext.vf4 C++ API tests new 921f11c8cc2 RISC-V: Add vzext.vf2 C++ API tests new 74595dd5181 RISC-V: Add vsext C++ API tests The 12 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: gcc/config/riscv/iterators.md | 4 +- gcc/config/riscv/riscv-vector-builtins-bases.cc | 25 +++ gcc/config/riscv/riscv-vector-builtins-bases.h | 2 + .../riscv/riscv-vector-builtins-functions.def | 6 + gcc/config/riscv/riscv-vector-builtins-shapes.cc | 21 +- gcc/config/riscv/riscv-vector-builtins-types.def | 104 ++++++++++ gcc/config/riscv/riscv-vector-builtins.cc | 131 ++++++++++++- gcc/config/riscv/riscv-vector-builtins.h | 3 + gcc/config/riscv/vector-iterators.md | 39 ++++ gcc/config/riscv/vector.md | 80 +++++++- .../g++.target/riscv/rvv/base/vsext_vf2-1.C | 216 +++++++++++++++++++++ .../g++.target/riscv/rvv/base/vsext_vf2-2.C | 216 +++++++++++++++++++++ .../g++.target/riscv/rvv/base/vsext_vf2-3.C | 216 +++++++++++++++++++++ .../g++.target/riscv/rvv/base/vsext_vf2_mu-1.C | 111 +++++++++++ .../g++.target/riscv/rvv/base/vsext_vf2_mu-2.C | 111 +++++++++++ .../g++.target/riscv/rvv/base/vsext_vf2_mu-3.C | 111 +++++++++++ .../g++.target/riscv/rvv/base/vsext_vf2_tu-1.C | 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69 +++++++ .../g++.target/riscv/rvv/base/vzext_vf4_tum-2.C | 69 +++++++ .../g++.target/riscv/rvv/base/vzext_vf4_tum-3.C | 69 +++++++ .../g++.target/riscv/rvv/base/vzext_vf4_tumu-1.C | 69 +++++++ .../g++.target/riscv/rvv/base/vzext_vf4_tumu-2.C | 69 +++++++ .../g++.target/riscv/rvv/base/vzext_vf4_tumu-3.C | 69 +++++++ .../g++.target/riscv/rvv/base/vzext_vf8-1.C | 62 ++++++ .../g++.target/riscv/rvv/base/vzext_vf8-2.C | 62 ++++++ .../g++.target/riscv/rvv/base/vzext_vf8-3.C | 62 ++++++ .../g++.target/riscv/rvv/base/vzext_vf8_mu-1.C | 34 ++++ .../g++.target/riscv/rvv/base/vzext_vf8_mu-2.C | 34 ++++ .../g++.target/riscv/rvv/base/vzext_vf8_mu-3.C | 34 ++++ .../g++.target/riscv/rvv/base/vzext_vf8_tu-1.C | 34 ++++ .../g++.target/riscv/rvv/base/vzext_vf8_tu-2.C | 34 ++++ .../g++.target/riscv/rvv/base/vzext_vf8_tu-3.C | 34 ++++ .../g++.target/riscv/rvv/base/vzext_vf8_tum-1.C | 34 ++++ .../g++.target/riscv/rvv/base/vzext_vf8_tum-2.C | 34 ++++ .../g++.target/riscv/rvv/base/vzext_vf8_tum-3.C | 34 ++++ .../g++.target/riscv/rvv/base/vzext_vf8_tumu-1.C | 34 ++++ .../g++.target/riscv/rvv/base/vzext_vf8_tumu-2.C | 34 ++++ .../g++.target/riscv/rvv/base/vzext_vf8_tumu-3.C | 34 ++++ .../riscv/rvv/base/unop_v_constraint-2.c | 132 +++++++++++++ .../gcc.target/riscv/rvv/base/vsext_vf2-1.c | 111 +++++++++++ .../gcc.target/riscv/rvv/base/vsext_vf2-2.c | 111 +++++++++++ .../gcc.target/riscv/rvv/base/vsext_vf2-3.c | 111 +++++++++++ .../gcc.target/riscv/rvv/base/vsext_vf2_m-1.c | 111 +++++++++++ .../gcc.target/riscv/rvv/base/vsext_vf2_m-2.c | 111 +++++++++++ .../gcc.target/riscv/rvv/base/vsext_vf2_m-3.c | 111 +++++++++++ .../gcc.target/riscv/rvv/base/vsext_vf2_mu-1.c | 111 +++++++++++ .../gcc.target/riscv/rvv/base/vsext_vf2_mu-2.c | 111 +++++++++++ .../gcc.target/riscv/rvv/base/vsext_vf2_mu-3.c | 111 +++++++++++ .../gcc.target/riscv/rvv/base/vsext_vf2_tu-1.c | 111 +++++++++++ .../gcc.target/riscv/rvv/base/vsext_vf2_tu-2.c | 111 +++++++++++ .../gcc.target/riscv/rvv/base/vsext_vf2_tu-3.c | 111 +++++++++++ .../gcc.target/riscv/rvv/base/vsext_vf2_tum-1.c | 111 +++++++++++ .../gcc.target/riscv/rvv/base/vsext_vf2_tum-2.c | 111 +++++++++++ .../gcc.target/riscv/rvv/base/vsext_vf2_tum-3.c | 111 +++++++++++ .../gcc.target/riscv/rvv/base/vsext_vf2_tumu-1.c | 111 +++++++++++ .../gcc.target/riscv/rvv/base/vsext_vf2_tumu-2.c | 111 +++++++++++ .../gcc.target/riscv/rvv/base/vsext_vf2_tumu-3.c | 111 +++++++++++ .../gcc.target/riscv/rvv/base/vsext_vf4-1.c | 69 +++++++ .../gcc.target/riscv/rvv/base/vsext_vf4-2.c | 69 +++++++ .../gcc.target/riscv/rvv/base/vsext_vf4-3.c | 69 +++++++ .../gcc.target/riscv/rvv/base/vsext_vf4_m-1.c | 69 +++++++ .../gcc.target/riscv/rvv/base/vsext_vf4_m-2.c | 69 +++++++ .../gcc.target/riscv/rvv/base/vsext_vf4_m-3.c | 69 +++++++ .../gcc.target/riscv/rvv/base/vsext_vf4_mu-1.c | 69 +++++++ .../gcc.target/riscv/rvv/base/vsext_vf4_mu-2.c | 69 +++++++ .../gcc.target/riscv/rvv/base/vsext_vf4_mu-3.c | 69 +++++++ .../gcc.target/riscv/rvv/base/vsext_vf4_tu-1.c | 69 +++++++ .../gcc.target/riscv/rvv/base/vsext_vf4_tu-2.c | 69 +++++++ .../gcc.target/riscv/rvv/base/vsext_vf4_tu-3.c | 69 +++++++ .../gcc.target/riscv/rvv/base/vsext_vf4_tum-1.c | 69 +++++++ .../gcc.target/riscv/rvv/base/vsext_vf4_tum-2.c | 69 +++++++ .../gcc.target/riscv/rvv/base/vsext_vf4_tum-3.c | 69 +++++++ .../gcc.target/riscv/rvv/base/vsext_vf4_tumu-1.c | 69 +++++++ .../gcc.target/riscv/rvv/base/vsext_vf4_tumu-2.c | 69 +++++++ .../gcc.target/riscv/rvv/base/vsext_vf4_tumu-3.c | 69 +++++++ .../gcc.target/riscv/rvv/base/vsext_vf8-1.c | 34 ++++ .../gcc.target/riscv/rvv/base/vsext_vf8-2.c | 34 ++++ .../gcc.target/riscv/rvv/base/vsext_vf8-3.c | 34 ++++ .../gcc.target/riscv/rvv/base/vsext_vf8_m-1.c | 34 ++++ .../gcc.target/riscv/rvv/base/vsext_vf8_m-2.c | 34 ++++ .../gcc.target/riscv/rvv/base/vsext_vf8_m-3.c | 34 ++++ .../gcc.target/riscv/rvv/base/vsext_vf8_mu-1.c | 34 ++++ .../gcc.target/riscv/rvv/base/vsext_vf8_mu-2.c | 34 ++++ .../gcc.target/riscv/rvv/base/vsext_vf8_mu-3.c | 34 ++++ .../gcc.target/riscv/rvv/base/vsext_vf8_tu-1.c | 34 ++++ .../gcc.target/riscv/rvv/base/vsext_vf8_tu-2.c | 34 ++++ .../gcc.target/riscv/rvv/base/vsext_vf8_tu-3.c | 34 ++++ .../gcc.target/riscv/rvv/base/vsext_vf8_tum-1.c | 34 ++++ .../gcc.target/riscv/rvv/base/vsext_vf8_tum-2.c | 34 ++++ .../gcc.target/riscv/rvv/base/vsext_vf8_tum-3.c | 34 ++++ .../gcc.target/riscv/rvv/base/vsext_vf8_tumu-1.c | 34 ++++ .../gcc.target/riscv/rvv/base/vsext_vf8_tumu-2.c | 34 ++++ .../gcc.target/riscv/rvv/base/vsext_vf8_tumu-3.c | 34 ++++ .../gcc.target/riscv/rvv/base/vzext_vf2-1.c | 111 +++++++++++ .../gcc.target/riscv/rvv/base/vzext_vf2-2.c | 111 +++++++++++ .../gcc.target/riscv/rvv/base/vzext_vf2-3.c | 111 +++++++++++ .../gcc.target/riscv/rvv/base/vzext_vf2_m-1.c | 111 +++++++++++ .../gcc.target/riscv/rvv/base/vzext_vf2_m-2.c | 111 +++++++++++ .../gcc.target/riscv/rvv/base/vzext_vf2_m-3.c | 111 +++++++++++ .../gcc.target/riscv/rvv/base/vzext_vf2_mu-1.c | 111 +++++++++++ .../gcc.target/riscv/rvv/base/vzext_vf2_mu-2.c | 111 +++++++++++ .../gcc.target/riscv/rvv/base/vzext_vf2_mu-3.c | 111 +++++++++++ .../gcc.target/riscv/rvv/base/vzext_vf2_tu-1.c | 111 +++++++++++ .../gcc.target/riscv/rvv/base/vzext_vf2_tu-2.c | 111 +++++++++++ .../gcc.target/riscv/rvv/base/vzext_vf2_tu-3.c | 111 +++++++++++ .../gcc.target/riscv/rvv/base/vzext_vf2_tum-1.c | 111 +++++++++++ .../gcc.target/riscv/rvv/base/vzext_vf2_tum-2.c | 111 +++++++++++ .../gcc.target/riscv/rvv/base/vzext_vf2_tum-3.c | 111 +++++++++++ .../gcc.target/riscv/rvv/base/vzext_vf2_tumu-1.c | 111 +++++++++++ .../gcc.target/riscv/rvv/base/vzext_vf2_tumu-2.c | 111 +++++++++++ .../gcc.target/riscv/rvv/base/vzext_vf2_tumu-3.c | 111 +++++++++++ .../gcc.target/riscv/rvv/base/vzext_vf4-1.c | 69 +++++++ .../gcc.target/riscv/rvv/base/vzext_vf4-2.c | 69 +++++++ .../gcc.target/riscv/rvv/base/vzext_vf4-3.c | 69 +++++++ .../gcc.target/riscv/rvv/base/vzext_vf4_m-1.c | 69 +++++++ .../gcc.target/riscv/rvv/base/vzext_vf4_m-2.c | 69 +++++++ .../gcc.target/riscv/rvv/base/vzext_vf4_m-3.c | 69 +++++++ .../gcc.target/riscv/rvv/base/vzext_vf4_mu-1.c | 69 +++++++ .../gcc.target/riscv/rvv/base/vzext_vf4_mu-2.c | 69 +++++++ .../gcc.target/riscv/rvv/base/vzext_vf4_mu-3.c | 69 +++++++ .../gcc.target/riscv/rvv/base/vzext_vf4_tu-1.c | 69 +++++++ .../gcc.target/riscv/rvv/base/vzext_vf4_tu-2.c | 69 +++++++ .../gcc.target/riscv/rvv/base/vzext_vf4_tu-3.c | 69 +++++++ .../gcc.target/riscv/rvv/base/vzext_vf4_tum-1.c | 69 +++++++ .../gcc.target/riscv/rvv/base/vzext_vf4_tum-2.c | 69 +++++++ .../gcc.target/riscv/rvv/base/vzext_vf4_tum-3.c | 69 +++++++ .../gcc.target/riscv/rvv/base/vzext_vf4_tumu-1.c | 69 +++++++ .../gcc.target/riscv/rvv/base/vzext_vf4_tumu-2.c | 69 +++++++ .../gcc.target/riscv/rvv/base/vzext_vf4_tumu-3.c | 69 +++++++ .../gcc.target/riscv/rvv/base/vzext_vf8-1.c | 34 ++++ .../gcc.target/riscv/rvv/base/vzext_vf8-2.c | 34 ++++ .../gcc.target/riscv/rvv/base/vzext_vf8-3.c | 34 ++++ .../gcc.target/riscv/rvv/base/vzext_vf8_m-1.c | 34 ++++ .../gcc.target/riscv/rvv/base/vzext_vf8_m-2.c | 34 ++++ .../gcc.target/riscv/rvv/base/vzext_vf8_m-3.c | 34 ++++ .../gcc.target/riscv/rvv/base/vzext_vf8_mu-1.c | 34 ++++ .../gcc.target/riscv/rvv/base/vzext_vf8_mu-2.c | 34 ++++ .../gcc.target/riscv/rvv/base/vzext_vf8_mu-3.c | 34 ++++ .../gcc.target/riscv/rvv/base/vzext_vf8_tu-1.c | 34 ++++ .../gcc.target/riscv/rvv/base/vzext_vf8_tu-2.c | 34 ++++ .../gcc.target/riscv/rvv/base/vzext_vf8_tu-3.c | 34 ++++ .../gcc.target/riscv/rvv/base/vzext_vf8_tum-1.c | 34 ++++ .../gcc.target/riscv/rvv/base/vzext_vf8_tum-2.c | 34 ++++ .../gcc.target/riscv/rvv/base/vzext_vf8_tum-3.c | 34 ++++ .../gcc.target/riscv/rvv/base/vzext_vf8_tumu-1.c | 34 ++++ .../gcc.target/riscv/rvv/base/vzext_vf8_tumu-2.c | 34 ++++ .../gcc.target/riscv/rvv/base/vzext_vf8_tumu-3.c | 34 ++++ 209 files changed, 15833 insertions(+), 14 deletions(-) create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf2-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf2-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf2-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf2_mu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf2_mu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf2_mu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf2_tu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf2_tu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf2_tu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf2_tum-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf2_tum-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf2_tum-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf2_tumu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf2_tumu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf2_tumu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf4-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf4-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf4-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf4_mu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf4_mu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf4_mu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf4_tu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf4_tu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf4_tu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf4_tum-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf4_tum-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf4_tum-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf4_tumu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf4_tumu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf4_tumu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf8-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf8-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf8-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf8_mu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf8_mu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf8_mu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf8_tu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf8_tu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf8_tu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf8_tum-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf8_tum-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf8_tum-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf8_tumu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf8_tumu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf8_tumu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf2-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf2-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf2-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf2_mu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf2_mu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf2_mu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf2_tu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf2_tu-2.C create mode 100644 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1 year, 9 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_gcc_bootstrap/master-aarch64-bootstrap updated (ba8857a8af -> 597b9943a3)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_gcc_bootstrap/master-aarch64-bootstrap in repository toolchain/ci/base-artifacts. discards ba8857a8af 552: onsuccess: #1996: 2: Success after binutils/gcc: 17 commits discards bd7000490c 551: onsuccess: #1995: 2: Success after binutils/gcc: 62 commits discards c74aeec283 550: onsuccess: #1994: 2: Success after binutils/gcc: 21 commits discards b1eb368406 549: onsuccess: #1992: 2: Success after binutils/gcc: 41 commits discards ce82e5a722 548: onsuccess: #1991: 2: Success after binutils/gcc: 14 commits discards 4a4ff45c82 547: onsuccess: #1990: 2: Success after binutils/gcc: 22 commits discards 0ba0750069 546: onsuccess: #1989: 2: Success after binutils/gcc: 6 commits discards a351987d03 545: onsuccess: #1988: 2: Success after binutils/gcc: 8 commits discards 37e76d3c04 544: onsuccess: #1987: 2: Success after binutils/gcc: 45 commits discards fee239e2d8 543: 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That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (ba8857a8af) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_gcc_bootstrap/master-aar [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 102 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log.xz | Bin 1756 -> 1740 bytes 02-prepare_abe/console.log.xz | Bin 2748 -> 2760 bytes 04-build_abe-binutils/console.log.xz | Bin 39264 -> 38756 bytes 05-build_abe-bootstrap/console.log.xz | Bin 271776 -> 274416 bytes 06-check_regression/console.log.xz | Bin 2924 -> 3008 bytes 07-update_baseline/console.log | 38 +++++++++++++++++----------------- dashboard/dashboard-generate.sh | 2 +- git/binutils_rev | 2 +- git/gcc_rev | 2 +- mail/jira-body.txt | 2 +- mail/mail-body.txt | 2 +- mail/mail-subject.txt | 2 +- manifest.sh | 18 ++++++++-------- 13 files changed, 34 insertions(+), 34 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

1 year, 9 months

[gcc] branch master updated (ee117887838 -> 064a2d53a38)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository gcc. from ee117887838 Daily bump. new c129d22de6b RISC-V: Fix VSETVL PASS bug in exception handling new d7f8c79a57e RISC-V: Add unary C/C++ API support new 2855e295484 RISC-V: Add vnot.v C API tests new 340a770d9dc RISC-V: Add vneg.v C/C++ API tests new 779e441103e RISC-V: Add unary constraint tests. new 4170a0f021f RISC-V: Add vnot.v C++ API tests new eeb50b70354 RISC-V: Add vneg.v C++ API tests new 7ad729a0df0 RISC-V: Add saturating Addition && Subtraction C/C++ Support new b2691c96efd RISC-V: Add saturating Add && Sub vx constraint tests new 098e7fc10e4 RISC-V: Add vsadd.vv C++ API tests new 77c9ee5e22e RISC-V: Add vsaddu.vv C++ API tests. new cc01b5c0659 RISC-V: Add vsub.vv C++ API tests new ae9b600f2d5 RISC-V: Add vssubu.vv C++ API tests new cd92bd48c55 RISC-V: Add vssubu.vv C API tests new bd182ae41bc RISC-V: Add vssub.vv C API tests new e5600572a17 RISC-V: Add vsaddu.vv C API tests new 6a04629d5a0 RISC-V: Add vsadd.vv C API tests new d6c18465cbb RISC-V: Add vssubu.vx C API tests new 1b7f3e20a2f RISC-V: Add vssub.vx C API tests new ed0c99027d4 RISC-V: Add vsaddu.vx C++ API tests new 933dce55100 RISC-V: Add vsadd.vx C++ API tests new e5dd529dcdb RISC-V: Add vssubu.vx C++ API tests new 3762ff2450c RISC-V: Add vssub.vx C++ API tests new a1ca758fd5e RISC-V: Add vsaddu.vx overloaded API tests new 064a2d53a38 RISC-V: Add vsadd.vx C++ overloaded API tests The 25 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: gcc/config/riscv/iterators.md | 16 +- gcc/config/riscv/riscv-v.cc | 5 +- gcc/config/riscv/riscv-vector-builtins-bases.cc | 23 ++ gcc/config/riscv/riscv-vector-builtins-bases.h | 6 + .../riscv/riscv-vector-builtins-functions.def | 81 +++--- gcc/config/riscv/riscv-vector-builtins-shapes.cc | 6 +- gcc/config/riscv/riscv-vector-builtins-shapes.h | 2 +- gcc/config/riscv/riscv-vector-builtins.cc | 12 + gcc/config/riscv/riscv-vsetvl.cc | 10 +- gcc/config/riscv/vector-iterators.md | 54 +++- gcc/config/riscv/vector.md | 280 +++++++++++++++++- .../g++.target/riscv/rvv/base/exception-1.C | 27 ++ gcc/testsuite/g++.target/riscv/rvv/base/vneg_v-1.C | 314 +++++++++++++++++++++ gcc/testsuite/g++.target/riscv/rvv/base/vneg_v-2.C | 314 +++++++++++++++++++++ gcc/testsuite/g++.target/riscv/rvv/base/vneg_v-3.C | 314 +++++++++++++++++++++ .../g++.target/riscv/rvv/base/vneg_v_mu-1.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vneg_v_mu-2.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vneg_v_mu-3.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vneg_v_tu-1.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vneg_v_tu-2.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vneg_v_tu-3.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vneg_v_tum-1.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vneg_v_tum-2.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vneg_v_tum-3.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vneg_v_tumu-1.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vneg_v_tumu-2.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vneg_v_tumu-3.C | 160 +++++++++++ gcc/testsuite/g++.target/riscv/rvv/base/vnot_v-1.C | 314 +++++++++++++++++++++ gcc/testsuite/g++.target/riscv/rvv/base/vnot_v-2.C | 314 +++++++++++++++++++++ gcc/testsuite/g++.target/riscv/rvv/base/vnot_v-3.C | 314 +++++++++++++++++++++ .../g++.target/riscv/rvv/base/vnot_v_mu-1.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vnot_v_mu-2.C | 160 +++++++++++ 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.../riscv/rvv/base/vsadd_vx_tum_rv32-2.C | 157 +++++++++++ .../riscv/rvv/base/vsadd_vx_tum_rv32-3.C | 157 +++++++++++ .../riscv/rvv/base/vsadd_vx_tum_rv64-1.C | 160 +++++++++++ .../riscv/rvv/base/vsadd_vx_tum_rv64-2.C | 160 +++++++++++ .../riscv/rvv/base/vsadd_vx_tum_rv64-3.C | 160 +++++++++++ .../riscv/rvv/base/vsadd_vx_tumu_rv32-1.C | 157 +++++++++++ .../riscv/rvv/base/vsadd_vx_tumu_rv32-2.C | 157 +++++++++++ .../riscv/rvv/base/vsadd_vx_tumu_rv32-3.C | 157 +++++++++++ .../riscv/rvv/base/vsadd_vx_tumu_rv64-1.C | 160 +++++++++++ .../riscv/rvv/base/vsadd_vx_tumu_rv64-2.C | 160 +++++++++++ .../riscv/rvv/base/vsadd_vx_tumu_rv64-3.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vsaddu_vv-1.C | 314 +++++++++++++++++++++ .../g++.target/riscv/rvv/base/vsaddu_vv-2.C | 314 +++++++++++++++++++++ .../g++.target/riscv/rvv/base/vsaddu_vv-3.C | 314 +++++++++++++++++++++ .../g++.target/riscv/rvv/base/vsaddu_vv_mu-1.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vsaddu_vv_mu-2.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vsaddu_vv_mu-3.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vsaddu_vv_tu-1.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vsaddu_vv_tu-2.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vsaddu_vv_tu-3.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vsaddu_vv_tum-1.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vsaddu_vv_tum-2.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vsaddu_vv_tum-3.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vsaddu_vv_tumu-1.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vsaddu_vv_tumu-2.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vsaddu_vv_tumu-3.C | 160 +++++++++++ .../riscv/rvv/base/vsaddu_vx_mu_rv32-1.C | 157 +++++++++++ .../riscv/rvv/base/vsaddu_vx_mu_rv32-2.C | 157 +++++++++++ .../riscv/rvv/base/vsaddu_vx_mu_rv32-3.C | 157 +++++++++++ .../riscv/rvv/base/vsaddu_vx_mu_rv64-1.C | 160 +++++++++++ .../riscv/rvv/base/vsaddu_vx_mu_rv64-2.C | 160 +++++++++++ .../riscv/rvv/base/vsaddu_vx_mu_rv64-3.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vsaddu_vx_rv32-1.C | 308 ++++++++++++++++++++ .../g++.target/riscv/rvv/base/vsaddu_vx_rv32-2.C | 308 ++++++++++++++++++++ .../g++.target/riscv/rvv/base/vsaddu_vx_rv32-3.C | 308 ++++++++++++++++++++ .../g++.target/riscv/rvv/base/vsaddu_vx_rv64-1.C | 314 +++++++++++++++++++++ .../g++.target/riscv/rvv/base/vsaddu_vx_rv64-2.C | 314 +++++++++++++++++++++ .../g++.target/riscv/rvv/base/vsaddu_vx_rv64-3.C | 314 +++++++++++++++++++++ .../riscv/rvv/base/vsaddu_vx_tu_rv32-1.C | 157 +++++++++++ .../riscv/rvv/base/vsaddu_vx_tu_rv32-2.C | 157 +++++++++++ .../riscv/rvv/base/vsaddu_vx_tu_rv32-3.C | 157 +++++++++++ .../riscv/rvv/base/vsaddu_vx_tu_rv64-1.C | 160 +++++++++++ .../riscv/rvv/base/vsaddu_vx_tu_rv64-2.C | 160 +++++++++++ .../riscv/rvv/base/vsaddu_vx_tu_rv64-3.C | 160 +++++++++++ .../riscv/rvv/base/vsaddu_vx_tum_rv32-1.C | 157 +++++++++++ .../riscv/rvv/base/vsaddu_vx_tum_rv32-2.C | 157 +++++++++++ .../riscv/rvv/base/vsaddu_vx_tum_rv32-3.C | 157 +++++++++++ .../riscv/rvv/base/vsaddu_vx_tum_rv64-1.C | 160 +++++++++++ .../riscv/rvv/base/vsaddu_vx_tum_rv64-2.C | 160 +++++++++++ .../riscv/rvv/base/vsaddu_vx_tum_rv64-3.C | 160 +++++++++++ .../riscv/rvv/base/vsaddu_vx_tumu_rv32-1.C | 157 +++++++++++ .../riscv/rvv/base/vsaddu_vx_tumu_rv32-2.C | 157 +++++++++++ .../riscv/rvv/base/vsaddu_vx_tumu_rv32-3.C | 157 +++++++++++ .../riscv/rvv/base/vsaddu_vx_tumu_rv64-1.C | 160 +++++++++++ .../riscv/rvv/base/vsaddu_vx_tumu_rv64-2.C | 160 +++++++++++ .../riscv/rvv/base/vsaddu_vx_tumu_rv64-3.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vssub_vv-1.C | 314 +++++++++++++++++++++ .../g++.target/riscv/rvv/base/vssub_vv-2.C | 314 +++++++++++++++++++++ .../g++.target/riscv/rvv/base/vssub_vv-3.C | 314 +++++++++++++++++++++ .../g++.target/riscv/rvv/base/vssub_vv_mu-1.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vssub_vv_mu-2.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vssub_vv_mu-3.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vssub_vv_tu-1.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vssub_vv_tu-2.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vssub_vv_tu-3.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vssub_vv_tum-1.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vssub_vv_tum-2.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vssub_vv_tum-3.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vssub_vv_tumu-1.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vssub_vv_tumu-2.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vssub_vv_tumu-3.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vssub_vx_mu_rv32-1.C | 157 +++++++++++ .../g++.target/riscv/rvv/base/vssub_vx_mu_rv32-2.C | 157 +++++++++++ .../g++.target/riscv/rvv/base/vssub_vx_mu_rv32-3.C | 157 +++++++++++ .../g++.target/riscv/rvv/base/vssub_vx_mu_rv64-1.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vssub_vx_mu_rv64-2.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vssub_vx_mu_rv64-3.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vssub_vx_rv32-1.C | 308 ++++++++++++++++++++ .../g++.target/riscv/rvv/base/vssub_vx_rv32-2.C | 308 ++++++++++++++++++++ .../g++.target/riscv/rvv/base/vssub_vx_rv32-3.C | 308 ++++++++++++++++++++ .../g++.target/riscv/rvv/base/vssub_vx_rv64-1.C | 314 +++++++++++++++++++++ .../g++.target/riscv/rvv/base/vssub_vx_rv64-2.C | 314 +++++++++++++++++++++ .../g++.target/riscv/rvv/base/vssub_vx_rv64-3.C | 314 +++++++++++++++++++++ .../g++.target/riscv/rvv/base/vssub_vx_tu_rv32-1.C | 157 +++++++++++ .../g++.target/riscv/rvv/base/vssub_vx_tu_rv32-2.C | 157 +++++++++++ .../g++.target/riscv/rvv/base/vssub_vx_tu_rv32-3.C | 157 +++++++++++ .../g++.target/riscv/rvv/base/vssub_vx_tu_rv64-1.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vssub_vx_tu_rv64-2.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vssub_vx_tu_rv64-3.C | 160 +++++++++++ .../riscv/rvv/base/vssub_vx_tum_rv32-1.C | 157 +++++++++++ .../riscv/rvv/base/vssub_vx_tum_rv32-2.C | 157 +++++++++++ .../riscv/rvv/base/vssub_vx_tum_rv32-3.C | 157 +++++++++++ .../riscv/rvv/base/vssub_vx_tum_rv64-1.C | 160 +++++++++++ .../riscv/rvv/base/vssub_vx_tum_rv64-2.C | 160 +++++++++++ .../riscv/rvv/base/vssub_vx_tum_rv64-3.C | 160 +++++++++++ .../riscv/rvv/base/vssub_vx_tumu_rv32-1.C | 157 +++++++++++ .../riscv/rvv/base/vssub_vx_tumu_rv32-2.C | 157 +++++++++++ .../riscv/rvv/base/vssub_vx_tumu_rv32-3.C | 157 +++++++++++ .../riscv/rvv/base/vssub_vx_tumu_rv64-1.C | 160 +++++++++++ .../riscv/rvv/base/vssub_vx_tumu_rv64-2.C | 160 +++++++++++ .../riscv/rvv/base/vssub_vx_tumu_rv64-3.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vssubu_vv-1.C | 314 +++++++++++++++++++++ .../g++.target/riscv/rvv/base/vssubu_vv-2.C | 314 +++++++++++++++++++++ .../g++.target/riscv/rvv/base/vssubu_vv-3.C | 314 +++++++++++++++++++++ .../g++.target/riscv/rvv/base/vssubu_vv_mu-1.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vssubu_vv_mu-2.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vssubu_vv_mu-3.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vssubu_vv_tu-1.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vssubu_vv_tu-2.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vssubu_vv_tu-3.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vssubu_vv_tum-1.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vssubu_vv_tum-2.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vssubu_vv_tum-3.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vssubu_vv_tumu-1.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vssubu_vv_tumu-2.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vssubu_vv_tumu-3.C | 160 +++++++++++ .../riscv/rvv/base/vssubu_vx_mu_rv32-1.C | 157 +++++++++++ .../riscv/rvv/base/vssubu_vx_mu_rv32-2.C | 157 +++++++++++ .../riscv/rvv/base/vssubu_vx_mu_rv32-3.C | 157 +++++++++++ .../riscv/rvv/base/vssubu_vx_mu_rv64-1.C | 160 +++++++++++ .../riscv/rvv/base/vssubu_vx_mu_rv64-2.C | 160 +++++++++++ .../riscv/rvv/base/vssubu_vx_mu_rv64-3.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vssubu_vx_rv32-1.C | 308 ++++++++++++++++++++ .../g++.target/riscv/rvv/base/vssubu_vx_rv32-2.C | 308 ++++++++++++++++++++ .../g++.target/riscv/rvv/base/vssubu_vx_rv32-3.C | 308 ++++++++++++++++++++ .../g++.target/riscv/rvv/base/vssubu_vx_rv64-1.C | 314 +++++++++++++++++++++ .../g++.target/riscv/rvv/base/vssubu_vx_rv64-2.C | 314 +++++++++++++++++++++ .../g++.target/riscv/rvv/base/vssubu_vx_rv64-3.C | 314 +++++++++++++++++++++ .../riscv/rvv/base/vssubu_vx_tu_rv32-1.C | 157 +++++++++++ .../riscv/rvv/base/vssubu_vx_tu_rv32-2.C | 157 +++++++++++ .../riscv/rvv/base/vssubu_vx_tu_rv32-3.C | 157 +++++++++++ .../riscv/rvv/base/vssubu_vx_tu_rv64-1.C | 160 +++++++++++ .../riscv/rvv/base/vssubu_vx_tu_rv64-2.C | 160 +++++++++++ .../riscv/rvv/base/vssubu_vx_tu_rv64-3.C | 160 +++++++++++ .../riscv/rvv/base/vssubu_vx_tum_rv32-1.C | 157 +++++++++++ .../riscv/rvv/base/vssubu_vx_tum_rv32-2.C | 157 +++++++++++ .../riscv/rvv/base/vssubu_vx_tum_rv32-3.C | 157 +++++++++++ .../riscv/rvv/base/vssubu_vx_tum_rv64-1.C | 160 +++++++++++ .../riscv/rvv/base/vssubu_vx_tum_rv64-2.C | 160 +++++++++++ .../riscv/rvv/base/vssubu_vx_tum_rv64-3.C | 160 +++++++++++ .../riscv/rvv/base/vssubu_vx_tumu_rv32-1.C | 157 +++++++++++ .../riscv/rvv/base/vssubu_vx_tumu_rv32-2.C | 157 +++++++++++ .../riscv/rvv/base/vssubu_vx_tumu_rv32-3.C | 157 +++++++++++ .../riscv/rvv/base/vssubu_vx_tumu_rv64-1.C | 160 +++++++++++ .../riscv/rvv/base/vssubu_vx_tumu_rv64-2.C | 160 +++++++++++ .../riscv/rvv/base/vssubu_vx_tumu_rv64-3.C | 160 +++++++++++ ...x_constraint-94.c => binop_vx_constraint-100.c} | 6 +- ...x_constraint-49.c => binop_vx_constraint-101.c} | 6 +- ...x_constraint-90.c => binop_vx_constraint-102.c} | 6 +- .../riscv/rvv/base/binop_vx_constraint-103.c | 123 ++++++++ .../riscv/rvv/base/binop_vx_constraint-104.c | 72 +++++ ...x_constraint-81.c => binop_vx_constraint-105.c} | 8 +- ...x_constraint-81.c => binop_vx_constraint-106.c} | 8 +- ...x_constraint-83.c => binop_vx_constraint-107.c} | 8 +- ...x_constraint-84.c => binop_vx_constraint-108.c} | 8 +- ...x_constraint-91.c => binop_vx_constraint-109.c} | 56 ++-- ...x_constraint-64.c => binop_vx_constraint-110.c} | 32 +-- ...x_constraint-93.c => binop_vx_constraint-111.c} | 6 +- ...x_constraint-94.c => binop_vx_constraint-112.c} | 6 +- ...x_constraint-49.c => binop_vx_constraint-113.c} | 6 +- ...x_constraint-90.c => binop_vx_constraint-114.c} | 6 +- ...x_constraint-80.c => binop_vx_constraint-115.c} | 32 +-- ...x_constraint-81.c => binop_vx_constraint-116.c} | 6 +- ...x_constraint-81.c => binop_vx_constraint-117.c} | 6 +- ...x_constraint-83.c => binop_vx_constraint-118.c} | 6 +- ...x_constraint-84.c => binop_vx_constraint-119.c} | 6 +- ...vx_constraint-91.c => binop_vx_constraint-97.c} | 56 ++-- ...vx_constraint-64.c => binop_vx_constraint-98.c} | 32 +-- ...vx_constraint-47.c => binop_vx_constraint-99.c} | 0 ...nop_vv_constraint-1.c => unop_v_constraint-1.c} | 48 ++-- gcc/testsuite/gcc.target/riscv/rvv/base/vneg_v-1.c | 160 +++++++++++ gcc/testsuite/gcc.target/riscv/rvv/base/vneg_v-2.c | 160 +++++++++++ gcc/testsuite/gcc.target/riscv/rvv/base/vneg_v-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vneg_v_m-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vneg_v_m-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vneg_v_m-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vneg_v_mu-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vneg_v_mu-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vneg_v_mu-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vneg_v_tu-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vneg_v_tu-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vneg_v_tu-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vneg_v_tum-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vneg_v_tum-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vneg_v_tum-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vneg_v_tumu-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vneg_v_tumu-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vneg_v_tumu-3.c | 160 +++++++++++ gcc/testsuite/gcc.target/riscv/rvv/base/vnot_v-1.c | 160 +++++++++++ gcc/testsuite/gcc.target/riscv/rvv/base/vnot_v-2.c | 160 +++++++++++ gcc/testsuite/gcc.target/riscv/rvv/base/vnot_v-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vnot_v_m-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vnot_v_m-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vnot_v_m-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vnot_v_mu-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vnot_v_mu-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vnot_v_mu-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vnot_v_tu-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vnot_v_tu-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vnot_v_tu-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vnot_v_tum-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vnot_v_tum-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vnot_v_tum-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vnot_v_tumu-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vnot_v_tumu-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vnot_v_tumu-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vsadd_vv-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vsadd_vv-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vsadd_vv-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vsadd_vv_m-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vsadd_vv_m-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vsadd_vv_m-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vsadd_vv_mu-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vsadd_vv_mu-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vsadd_vv_mu-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vsadd_vv_tu-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vsadd_vv_tu-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vsadd_vv_tu-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vsadd_vv_tum-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vsadd_vv_tum-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vsadd_vv_tum-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vsadd_vv_tumu-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vsadd_vv_tumu-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vsadd_vv_tumu-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vsadd_vx_m_rv32-1.c | 157 +++++++++++ .../gcc.target/riscv/rvv/base/vsadd_vx_m_rv32-2.c | 157 +++++++++++ .../gcc.target/riscv/rvv/base/vsadd_vx_m_rv32-3.c | 157 +++++++++++ .../gcc.target/riscv/rvv/base/vsadd_vx_m_rv64-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vsadd_vx_m_rv64-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vsadd_vx_m_rv64-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vsadd_vx_mu_rv32-1.c | 157 +++++++++++ .../gcc.target/riscv/rvv/base/vsadd_vx_mu_rv32-2.c | 157 +++++++++++ .../gcc.target/riscv/rvv/base/vsadd_vx_mu_rv32-3.c | 157 +++++++++++ .../gcc.target/riscv/rvv/base/vsadd_vx_mu_rv64-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vsadd_vx_mu_rv64-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vsadd_vx_mu_rv64-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vsadd_vx_rv32-1.c | 157 +++++++++++ .../gcc.target/riscv/rvv/base/vsadd_vx_rv32-2.c | 157 +++++++++++ .../gcc.target/riscv/rvv/base/vsadd_vx_rv32-3.c | 157 +++++++++++ .../gcc.target/riscv/rvv/base/vsadd_vx_rv64-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vsadd_vx_rv64-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vsadd_vx_rv64-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vsadd_vx_tu_rv32-1.c | 157 +++++++++++ .../gcc.target/riscv/rvv/base/vsadd_vx_tu_rv32-2.c | 157 +++++++++++ .../gcc.target/riscv/rvv/base/vsadd_vx_tu_rv32-3.c | 157 +++++++++++ .../gcc.target/riscv/rvv/base/vsadd_vx_tu_rv64-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vsadd_vx_tu_rv64-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vsadd_vx_tu_rv64-3.c | 160 +++++++++++ .../riscv/rvv/base/vsadd_vx_tum_rv32-1.c | 157 +++++++++++ .../riscv/rvv/base/vsadd_vx_tum_rv32-2.c | 157 +++++++++++ .../riscv/rvv/base/vsadd_vx_tum_rv32-3.c | 157 +++++++++++ .../riscv/rvv/base/vsadd_vx_tum_rv64-1.c | 160 +++++++++++ .../riscv/rvv/base/vsadd_vx_tum_rv64-2.c | 160 +++++++++++ .../riscv/rvv/base/vsadd_vx_tum_rv64-3.c | 160 +++++++++++ .../riscv/rvv/base/vsadd_vx_tumu_rv32-1.c | 157 +++++++++++ .../riscv/rvv/base/vsadd_vx_tumu_rv32-2.c | 157 +++++++++++ .../riscv/rvv/base/vsadd_vx_tumu_rv32-3.c | 157 +++++++++++ .../riscv/rvv/base/vsadd_vx_tumu_rv64-1.c | 160 +++++++++++ .../riscv/rvv/base/vsadd_vx_tumu_rv64-2.c | 160 +++++++++++ .../riscv/rvv/base/vsadd_vx_tumu_rv64-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vsaddu_vv-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vsaddu_vv-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vsaddu_vv-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vsaddu_vv_m-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vsaddu_vv_m-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vsaddu_vv_m-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vsaddu_vv_mu-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vsaddu_vv_mu-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vsaddu_vv_mu-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vsaddu_vv_tu-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vsaddu_vv_tu-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vsaddu_vv_tu-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vsaddu_vv_tum-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vsaddu_vv_tum-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vsaddu_vv_tum-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vsaddu_vv_tumu-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vsaddu_vv_tumu-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vsaddu_vv_tumu-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vsaddu_vx_m_rv32-1.c | 157 +++++++++++ .../gcc.target/riscv/rvv/base/vsaddu_vx_m_rv32-2.c | 157 +++++++++++ .../gcc.target/riscv/rvv/base/vsaddu_vx_m_rv32-3.c | 157 +++++++++++ .../gcc.target/riscv/rvv/base/vsaddu_vx_m_rv64-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vsaddu_vx_m_rv64-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vsaddu_vx_m_rv64-3.c | 160 +++++++++++ .../riscv/rvv/base/vsaddu_vx_mu_rv32-1.c | 157 +++++++++++ .../riscv/rvv/base/vsaddu_vx_mu_rv32-2.c | 157 +++++++++++ .../riscv/rvv/base/vsaddu_vx_mu_rv32-3.c | 157 +++++++++++ .../riscv/rvv/base/vsaddu_vx_mu_rv64-1.c | 160 +++++++++++ .../riscv/rvv/base/vsaddu_vx_mu_rv64-2.c | 160 +++++++++++ .../riscv/rvv/base/vsaddu_vx_mu_rv64-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vsaddu_vx_rv32-1.c | 157 +++++++++++ .../gcc.target/riscv/rvv/base/vsaddu_vx_rv32-2.c | 157 +++++++++++ .../gcc.target/riscv/rvv/base/vsaddu_vx_rv32-3.c | 157 +++++++++++ .../gcc.target/riscv/rvv/base/vsaddu_vx_rv64-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vsaddu_vx_rv64-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vsaddu_vx_rv64-3.c | 160 +++++++++++ .../riscv/rvv/base/vsaddu_vx_tu_rv32-1.c | 157 +++++++++++ .../riscv/rvv/base/vsaddu_vx_tu_rv32-2.c | 157 +++++++++++ .../riscv/rvv/base/vsaddu_vx_tu_rv32-3.c | 157 +++++++++++ .../riscv/rvv/base/vsaddu_vx_tu_rv64-1.c | 160 +++++++++++ .../riscv/rvv/base/vsaddu_vx_tu_rv64-2.c | 160 +++++++++++ .../riscv/rvv/base/vsaddu_vx_tu_rv64-3.c | 160 +++++++++++ .../riscv/rvv/base/vsaddu_vx_tum_rv32-1.c | 157 +++++++++++ .../riscv/rvv/base/vsaddu_vx_tum_rv32-2.c | 157 +++++++++++ .../riscv/rvv/base/vsaddu_vx_tum_rv32-3.c | 157 +++++++++++ .../riscv/rvv/base/vsaddu_vx_tum_rv64-1.c | 160 +++++++++++ .../riscv/rvv/base/vsaddu_vx_tum_rv64-2.c | 160 +++++++++++ .../riscv/rvv/base/vsaddu_vx_tum_rv64-3.c | 160 +++++++++++ .../riscv/rvv/base/vsaddu_vx_tumu_rv32-1.c | 157 +++++++++++ .../riscv/rvv/base/vsaddu_vx_tumu_rv32-2.c | 157 +++++++++++ .../riscv/rvv/base/vsaddu_vx_tumu_rv32-3.c | 157 +++++++++++ .../riscv/rvv/base/vsaddu_vx_tumu_rv64-1.c | 160 +++++++++++ .../riscv/rvv/base/vsaddu_vx_tumu_rv64-2.c | 160 +++++++++++ .../riscv/rvv/base/vsaddu_vx_tumu_rv64-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssub_vv-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssub_vv-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssub_vv-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssub_vv_m-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssub_vv_m-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssub_vv_m-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssub_vv_mu-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssub_vv_mu-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssub_vv_mu-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssub_vv_tu-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssub_vv_tu-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssub_vv_tu-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssub_vv_tum-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssub_vv_tum-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssub_vv_tum-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssub_vv_tumu-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssub_vv_tumu-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssub_vv_tumu-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssub_vx_m_rv32-1.c | 157 +++++++++++ .../gcc.target/riscv/rvv/base/vssub_vx_m_rv32-2.c | 157 +++++++++++ .../gcc.target/riscv/rvv/base/vssub_vx_m_rv32-3.c | 157 +++++++++++ .../gcc.target/riscv/rvv/base/vssub_vx_m_rv64-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssub_vx_m_rv64-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssub_vx_m_rv64-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssub_vx_mu_rv32-1.c | 157 +++++++++++ .../gcc.target/riscv/rvv/base/vssub_vx_mu_rv32-2.c | 157 +++++++++++ .../gcc.target/riscv/rvv/base/vssub_vx_mu_rv32-3.c | 157 +++++++++++ .../gcc.target/riscv/rvv/base/vssub_vx_mu_rv64-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssub_vx_mu_rv64-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssub_vx_mu_rv64-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssub_vx_rv32-1.c | 157 +++++++++++ .../gcc.target/riscv/rvv/base/vssub_vx_rv32-2.c | 157 +++++++++++ .../gcc.target/riscv/rvv/base/vssub_vx_rv32-3.c | 157 +++++++++++ .../gcc.target/riscv/rvv/base/vssub_vx_rv64-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssub_vx_rv64-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssub_vx_rv64-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssub_vx_tu_rv32-1.c | 157 +++++++++++ .../gcc.target/riscv/rvv/base/vssub_vx_tu_rv32-2.c | 157 +++++++++++ .../gcc.target/riscv/rvv/base/vssub_vx_tu_rv32-3.c | 157 +++++++++++ .../gcc.target/riscv/rvv/base/vssub_vx_tu_rv64-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssub_vx_tu_rv64-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssub_vx_tu_rv64-3.c | 160 +++++++++++ .../riscv/rvv/base/vssub_vx_tum_rv32-1.c | 157 +++++++++++ .../riscv/rvv/base/vssub_vx_tum_rv32-2.c | 157 +++++++++++ .../riscv/rvv/base/vssub_vx_tum_rv32-3.c | 157 +++++++++++ .../riscv/rvv/base/vssub_vx_tum_rv64-1.c | 160 +++++++++++ .../riscv/rvv/base/vssub_vx_tum_rv64-2.c | 160 +++++++++++ .../riscv/rvv/base/vssub_vx_tum_rv64-3.c | 160 +++++++++++ .../riscv/rvv/base/vssub_vx_tumu_rv32-1.c | 157 +++++++++++ .../riscv/rvv/base/vssub_vx_tumu_rv32-2.c | 157 +++++++++++ .../riscv/rvv/base/vssub_vx_tumu_rv32-3.c | 157 +++++++++++ .../riscv/rvv/base/vssub_vx_tumu_rv64-1.c | 160 +++++++++++ .../riscv/rvv/base/vssub_vx_tumu_rv64-2.c | 160 +++++++++++ .../riscv/rvv/base/vssub_vx_tumu_rv64-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssubu_vv-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssubu_vv-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssubu_vv-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssubu_vv_m-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssubu_vv_m-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssubu_vv_m-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssubu_vv_mu-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssubu_vv_mu-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssubu_vv_mu-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssubu_vv_tu-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssubu_vv_tu-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssubu_vv_tu-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssubu_vv_tum-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssubu_vv_tum-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssubu_vv_tum-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssubu_vv_tumu-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssubu_vv_tumu-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssubu_vv_tumu-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssubu_vx_m_rv32-1.c | 157 +++++++++++ .../gcc.target/riscv/rvv/base/vssubu_vx_m_rv32-2.c | 157 +++++++++++ .../gcc.target/riscv/rvv/base/vssubu_vx_m_rv32-3.c | 157 +++++++++++ .../gcc.target/riscv/rvv/base/vssubu_vx_m_rv64-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssubu_vx_m_rv64-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssubu_vx_m_rv64-3.c | 160 +++++++++++ .../riscv/rvv/base/vssubu_vx_mu_rv32-1.c | 157 +++++++++++ .../riscv/rvv/base/vssubu_vx_mu_rv32-2.c | 157 +++++++++++ .../riscv/rvv/base/vssubu_vx_mu_rv32-3.c | 157 +++++++++++ .../riscv/rvv/base/vssubu_vx_mu_rv64-1.c | 160 +++++++++++ .../riscv/rvv/base/vssubu_vx_mu_rv64-2.c | 160 +++++++++++ .../riscv/rvv/base/vssubu_vx_mu_rv64-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssubu_vx_rv32-1.c | 157 +++++++++++ .../gcc.target/riscv/rvv/base/vssubu_vx_rv32-2.c | 157 +++++++++++ .../gcc.target/riscv/rvv/base/vssubu_vx_rv32-3.c | 157 +++++++++++ .../gcc.target/riscv/rvv/base/vssubu_vx_rv64-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssubu_vx_rv64-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssubu_vx_rv64-3.c | 160 +++++++++++ .../riscv/rvv/base/vssubu_vx_tu_rv32-1.c | 157 +++++++++++ .../riscv/rvv/base/vssubu_vx_tu_rv32-2.c | 157 +++++++++++ .../riscv/rvv/base/vssubu_vx_tu_rv32-3.c | 157 +++++++++++ .../riscv/rvv/base/vssubu_vx_tu_rv64-1.c | 160 +++++++++++ .../riscv/rvv/base/vssubu_vx_tu_rv64-2.c | 160 +++++++++++ .../riscv/rvv/base/vssubu_vx_tu_rv64-3.c | 160 +++++++++++ .../riscv/rvv/base/vssubu_vx_tum_rv32-1.c | 157 +++++++++++ .../riscv/rvv/base/vssubu_vx_tum_rv32-2.c | 157 +++++++++++ .../riscv/rvv/base/vssubu_vx_tum_rv32-3.c | 157 +++++++++++ .../riscv/rvv/base/vssubu_vx_tum_rv64-1.c | 160 +++++++++++ .../riscv/rvv/base/vssubu_vx_tum_rv64-2.c | 160 +++++++++++ .../riscv/rvv/base/vssubu_vx_tum_rv64-3.c | 160 +++++++++++ .../riscv/rvv/base/vssubu_vx_tumu_rv32-1.c | 157 +++++++++++ .../riscv/rvv/base/vssubu_vx_tumu_rv32-2.c | 157 +++++++++++ .../riscv/rvv/base/vssubu_vx_tumu_rv32-3.c | 157 +++++++++++ .../riscv/rvv/base/vssubu_vx_tumu_rv64-1.c | 160 +++++++++++ .../riscv/rvv/base/vssubu_vx_tumu_rv64-2.c | 160 +++++++++++ .../riscv/rvv/base/vssubu_vx_tumu_rv64-3.c | 160 +++++++++++ 498 files changed, 80788 insertions(+), 239 deletions(-) create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/exception-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vneg_v-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vneg_v-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vneg_v-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vneg_v_mu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vneg_v_mu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vneg_v_mu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vneg_v_tu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vneg_v_tu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vneg_v_tu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vneg_v_tum-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vneg_v_tum-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vneg_v_tum-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vneg_v_tumu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vneg_v_tumu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vneg_v_tumu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnot_v-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnot_v-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnot_v-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnot_v_mu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnot_v_mu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnot_v_mu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnot_v_tu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnot_v_tu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnot_v_tu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnot_v_tum-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnot_v_tum-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnot_v_tum-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnot_v_tumu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnot_v_tumu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnot_v_tumu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsadd_vv-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsadd_vv-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsadd_vv-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsadd_vv_mu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsadd_vv_mu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsadd_vv_mu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsadd_vv_tu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsadd_vv_tu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsadd_vv_tu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsadd_vv_tum-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsadd_vv_tum-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsadd_vv_tum-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsadd_vv_tumu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsadd_vv_tumu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsadd_vv_tumu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsadd_vx_mu_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsadd_vx_mu_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsadd_vx_mu_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsadd_vx_mu_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsadd_vx_mu_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsadd_vx_mu_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsadd_vx_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsadd_vx_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsadd_vx_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsadd_vx_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsadd_vx_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsadd_vx_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsadd_vx_tu_rv32-1.C create mode 100644 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gcc/testsuite/g++.target/riscv/rvv/base/vsadd_vx_tumu_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsadd_vx_tumu_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsadd_vx_tumu_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsadd_vx_tumu_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsadd_vx_tumu_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsaddu_vv-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsaddu_vv-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsaddu_vv-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsaddu_vv_mu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsaddu_vv_mu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsaddu_vv_mu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsaddu_vv_tu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsaddu_vv_tu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsaddu_vv_tu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsaddu_vv_tum-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsaddu_vv_tum-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsaddu_vv_tum-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsaddu_vv_tumu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsaddu_vv_tumu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsaddu_vv_tumu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsaddu_vx_mu_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsaddu_vx_mu_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsaddu_vx_mu_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsaddu_vx_mu_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsaddu_vx_mu_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsaddu_vx_mu_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsaddu_vx_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsaddu_vx_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsaddu_vx_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsaddu_vx_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsaddu_vx_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsaddu_vx_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsaddu_vx_tu_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsaddu_vx_tu_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsaddu_vx_tu_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsaddu_vx_tu_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsaddu_vx_tu_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsaddu_vx_tu_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsaddu_vx_tum_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsaddu_vx_tum_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsaddu_vx_tum_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsaddu_vx_tum_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsaddu_vx_tum_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsaddu_vx_tum_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsaddu_vx_tumu_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsaddu_vx_tumu_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsaddu_vx_tumu_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsaddu_vx_tumu_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsaddu_vx_tumu_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsaddu_vx_tumu_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssub_vv-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssub_vv-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssub_vv-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssub_vv_mu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssub_vv_mu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssub_vv_mu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssub_vv_tu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssub_vv_tu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssub_vv_tu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssub_vv_tum-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssub_vv_tum-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssub_vv_tum-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssub_vv_tumu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssub_vv_tumu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssub_vv_tumu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssub_vx_mu_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssub_vx_mu_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssub_vx_mu_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssub_vx_mu_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssub_vx_mu_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssub_vx_mu_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssub_vx_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssub_vx_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssub_vx_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssub_vx_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssub_vx_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssub_vx_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssub_vx_tu_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssub_vx_tu_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssub_vx_tu_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssub_vx_tu_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssub_vx_tu_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssub_vx_tu_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssub_vx_tum_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssub_vx_tum_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssub_vx_tum_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssub_vx_tum_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssub_vx_tum_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssub_vx_tum_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssub_vx_tumu_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssub_vx_tumu_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssub_vx_tumu_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssub_vx_tumu_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssub_vx_tumu_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssub_vx_tumu_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vv-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vv-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vv-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vv_mu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vv_mu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vv_mu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vv_tu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vv_tu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vv_tu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vv_tum-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vv_tum-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vv_tum-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vv_tumu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vv_tumu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vv_tumu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_mu_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_mu_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_mu_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_mu_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_mu_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_mu_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_tu_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_tu_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_tu_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_tu_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_tu_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_tu_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_tum_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_tum_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_tum_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_tum_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_tum_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_tum_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_tumu_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_tumu_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_tumu_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_tumu_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_tumu_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_tumu_rv64-3.C copy gcc/testsuite/gcc.target/riscv/rvv/base/{binop_vx_constraint-94.c => binop_vx [...] copy gcc/testsuite/gcc.target/riscv/rvv/base/{binop_vx_constraint-49.c => binop_vx [...] copy gcc/testsuite/gcc.target/riscv/rvv/base/{binop_vx_constraint-90.c => binop_vx [...] create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-103.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-104.c copy gcc/testsuite/gcc.target/riscv/rvv/base/{binop_vx_constraint-81.c => binop_vx [...] copy gcc/testsuite/gcc.target/riscv/rvv/base/{binop_vx_constraint-81.c => binop_vx [...] copy gcc/testsuite/gcc.target/riscv/rvv/base/{binop_vx_constraint-83.c => binop_vx [...] copy gcc/testsuite/gcc.target/riscv/rvv/base/{binop_vx_constraint-84.c => binop_vx [...] copy gcc/testsuite/gcc.target/riscv/rvv/base/{binop_vx_constraint-91.c => binop_vx [...] copy gcc/testsuite/gcc.target/riscv/rvv/base/{binop_vx_constraint-64.c => binop_vx [...] copy gcc/testsuite/gcc.target/riscv/rvv/base/{binop_vx_constraint-93.c => binop_vx [...] copy gcc/testsuite/gcc.target/riscv/rvv/base/{binop_vx_constraint-94.c => binop_vx [...] copy gcc/testsuite/gcc.target/riscv/rvv/base/{binop_vx_constraint-49.c => binop_vx [...] copy gcc/testsuite/gcc.target/riscv/rvv/base/{binop_vx_constraint-90.c => binop_vx [...] copy gcc/testsuite/gcc.target/riscv/rvv/base/{binop_vx_constraint-80.c => binop_vx [...] copy gcc/testsuite/gcc.target/riscv/rvv/base/{binop_vx_constraint-81.c => binop_vx [...] copy gcc/testsuite/gcc.target/riscv/rvv/base/{binop_vx_constraint-81.c => binop_vx [...] copy gcc/testsuite/gcc.target/riscv/rvv/base/{binop_vx_constraint-83.c => binop_vx [...] copy gcc/testsuite/gcc.target/riscv/rvv/base/{binop_vx_constraint-84.c => binop_vx [...] copy gcc/testsuite/gcc.target/riscv/rvv/base/{binop_vx_constraint-91.c => binop_vx [...] copy gcc/testsuite/gcc.target/riscv/rvv/base/{binop_vx_constraint-64.c => binop_vx [...] copy gcc/testsuite/gcc.target/riscv/rvv/base/{binop_vx_constraint-47.c => binop_vx [...] copy gcc/testsuite/gcc.target/riscv/rvv/base/{binop_vv_constraint-1.c => unop_v_co [...] create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vneg_v-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vneg_v-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vneg_v-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vneg_v_m-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vneg_v_m-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vneg_v_m-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vneg_v_mu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vneg_v_mu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vneg_v_mu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vneg_v_tu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vneg_v_tu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vneg_v_tu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vneg_v_tum-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vneg_v_tum-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vneg_v_tum-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vneg_v_tumu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vneg_v_tumu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vneg_v_tumu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnot_v-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnot_v-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnot_v-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnot_v_m-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnot_v_m-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnot_v_m-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnot_v_mu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnot_v_mu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnot_v_mu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnot_v_tu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnot_v_tu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnot_v_tu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnot_v_tum-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnot_v_tum-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnot_v_tum-3.c create mode 100644 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gcc/testsuite/gcc.target/riscv/rvv/base/vsadd_vx_tum_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsadd_vx_tumu_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsadd_vx_tumu_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsadd_vx_tumu_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsadd_vx_tumu_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsadd_vx_tumu_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsadd_vx_tumu_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsaddu_vv-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsaddu_vv-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsaddu_vv-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsaddu_vv_m-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsaddu_vv_m-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsaddu_vv_m-3.c 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create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsaddu_vx_m_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsaddu_vx_m_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsaddu_vx_m_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsaddu_vx_m_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsaddu_vx_m_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsaddu_vx_mu_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsaddu_vx_mu_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsaddu_vx_mu_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsaddu_vx_mu_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsaddu_vx_mu_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsaddu_vx_mu_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsaddu_vx_rv32-1.c create mode 100644 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gcc/testsuite/gcc.target/riscv/rvv/base/vssubu_vx_tum_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssubu_vx_tum_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssubu_vx_tumu_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssubu_vx_tumu_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssubu_vx_tumu_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssubu_vx_tumu_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssubu_vx_tumu_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssubu_vx_tumu_rv64-3.c -- To stop receiving notification emails like this one, please contact the administrator of this repository.

1 year, 9 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/llvm-master-arm-mainline-defconfig updated (cff4781ea4 -> 0ad8d9462e)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-arm-mainline-defconfig in repository toolchain/ci/base-artifacts. from cff4781ea4 40: onsuccess: #462: boot: Success after binutils/llvm/linux [...] new 0ad8d9462e 41: onsuccess: #463: boot: Success after binutils/llvm/linux [...] The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log.xz | Bin 1756 -> 1784 bytes 02-prepare_abe/console.log.xz | Bin 2768 -> 2768 bytes 03-build_abe-binutils/console.log.xz | Bin 31056 -> 30836 bytes 04-build_kernel_llvm/console.log.xz | Bin 64284 -> 63084 bytes 05-build_abe-qemu/console.log.xz | Bin 32500 -> 31496 bytes 06-build_linux/console.log.xz | Bin 3136 -> 3120 bytes 07-boot_linux/console.log.xz | Bin 5664 -> 5652 bytes 08-check_regression/console.log.xz | Bin 4356 -> 4308 bytes 09-update_baseline/console.log | 8 ++++---- dashboard/dashboard-generate.sh | 2 +- git/binutils_rev | 2 +- git/linux_rev | 2 +- git/llvm_rev | 2 +- git/qemu_rev | 2 +- mail/jira-body.txt | 2 +- mail/mail-body.txt | 2 +- mail/mail-subject.txt | 2 +- manifest.sh | 32 ++++++++++++++++---------------- 18 files changed, 28 insertions(+), 28 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

1 year, 9 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_gcc_bootstrap/master-arm-bootstrap_profiled_lto_lean updated (0f8fc2c3c8 -> 96bd1365f1)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_gcc_bootstrap/master-arm-bootstrap_profiled_lto_lean in repository toolchain/ci/base-artifacts. discards 0f8fc2c3c8 161: onsuccess: #570: 2: Success after binutils/gcc: 57 commits discards 5b984998d2 160: onsuccess: #568: 2: Success after binutils/gcc: 20 commits discards f0aa5954dc 159: onsuccess: #567: 2: Success after binutils/gcc: 28 commits discards ff79b955fc 158: onsuccess: #566: 2: Success after binutils/gcc: 7 commits discards 8f543cdef0 157: onsuccess: #565: 2: Success after binutils/gcc: 79 commits discards 0641e54d1e 156: onsuccess: #562: 2: Success after binutils/gcc: 47 commits discards e2386ab713 155: onsuccess: #561: 2: Success after binutils/gcc: 108 commits discards 2705d14196 154: onsuccess: #560: 2: Success after binutils/gcc: 59 commits discards 3b1905d403 153: onsuccess: #558: 2: Success after binutils/gcc: 28 commits discards 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commits new fb2825f092 155: onsuccess: #561: 2: Success after binutils/gcc: 108 commits new 0b90d1edd0 156: onsuccess: #562: 2: Success after binutils/gcc: 47 commits new dc1f25fb17 157: onsuccess: #565: 2: Success after binutils/gcc: 79 commits new a16e2118fa 158: onsuccess: #566: 2: Success after binutils/gcc: 7 commits new 97d76b2699 159: onsuccess: #567: 2: Success after binutils/gcc: 28 commits new b790d56e67 160: onsuccess: #568: 2: Success after binutils/gcc: 20 commits new 06553d13d4 161: onsuccess: #570: 2: Success after binutils/gcc: 57 commits new 96bd1365f1 162: onsuccess: #571: 2: Success after binutils/gcc: 75 commits This update added new revisions after undoing existing revisions. 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Summary of changes: 01-reset_artifacts/console.log.xz | Bin 1784 -> 1808 bytes 02-prepare_abe/console.log.xz | Bin 2752 -> 2748 bytes 04-build_abe-binutils/console.log.xz | Bin 51844 -> 52556 bytes .../console.log.xz | Bin 957244 -> 956908 bytes 06-check_regression/console.log.xz | Bin 3104 -> 3020 bytes 07-update_baseline/console.log | 38 ++++++++++----------- dashboard/dashboard-generate.sh | 2 +- git/binutils_rev | 2 +- git/gcc_rev | 2 +- mail/jira-body.txt | 2 +- mail/mail-body.txt | 2 +- mail/mail-subject.txt | 2 +- manifest.sh | 18 +++++----- 13 files changed, 34 insertions(+), 34 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

1 year, 9 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_gcc_bootstrap/master-aarch64-bootstrap_debug updated (96fceee23c -> 6a34a53f16)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_gcc_bootstrap/master-aarch64-bootstrap_debug in repository toolchain/ci/base-artifacts. discards 96fceee23c 174: onsuccess: #576: 2: Success after binutils/gcc: 121 commits discards e1c3303c5d 173: onsuccess: #574: 2: Success after binutils/gcc: 18 commits discards 8122f96836 172: onsuccess: #573: 2: Success after binutils/gcc: 28 commits discards 68ea13579e 171: onsuccess: #572: 2: Success after binutils/gcc: 52 commits discards bd985f87a6 170: onsuccess: #571: 2: Success after binutils/gcc: 44 commits discards ead1413017 169: onsuccess: #570: 2: Success after binutils/gcc: 47 commits discards d95a7098e8 168: onsuccess: #569: 2: Success after binutils/gcc: 145 commits discards d449fd4ca6 167: onsuccess: #568: 2: Success after binutils/gcc: 22 commits discards 4d071442b5 166: onsuccess: #567: 2: Success after binutils/gcc: 228 commits discards 33174f1e69 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That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (96fceee23c) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_gcc_bootstrap/master-aar [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 102 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log.xz | Bin 1760 -> 1748 bytes 02-prepare_abe/console.log.xz | Bin 2752 -> 2740 bytes 04-build_abe-binutils/console.log.xz | Bin 39808 -> 38752 bytes 05-build_abe-bootstrap_debug/console.log.xz | Bin 273640 -> 271092 bytes 06-check_regression/console.log.xz | Bin 3052 -> 3000 bytes 07-update_baseline/console.log | 56 ++++++++++++++-------------- dashboard/dashboard-generate.sh | 2 +- git/binutils_rev | 2 +- git/gcc_rev | 2 +- mail/jira-body.txt | 2 +- mail/mail-body.txt | 2 +- mail/mail-subject.txt | 2 +- manifest.sh | 18 ++++----- 13 files changed, 43 insertions(+), 43 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

1 year, 9 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_bmk-code_speed-spec2k6/gnu-arm-master-O3 updated (f874ce5376 -> 2ebe141a43)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_bmk-code_speed-spec2k6/gnu-arm-master-O3 in repository toolchain/ci/base-artifacts. from f874ce5376 65: onsuccess: #37: 1: [TCWG CI] No change after binutils/gc [...] new 2ebe141a43 66: onsuccess: #38: 1: [TCWG CI] No change after binutils/gc [...] The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log.xz | Bin 1788 -> 1844 bytes 02-prepare_abe/console.log.xz | Bin 2780 -> 2772 bytes 03-build_abe-binutils/console.log.xz | Bin 31676 -> 31476 bytes 04-build_abe-stage1/console.log.xz | Bin 94436 -> 94636 bytes 05-clean_sysroot/console.log.xz | Bin 336 -> 336 bytes 06-build_abe-linux/console.log.xz | Bin 8664 -> 8704 bytes 07-build_abe-glibc/console.log.xz | Bin 238672 -> 238016 bytes 08-build_abe-stage2/console.log.xz | Bin 223844 -> 220124 bytes 09-benchmark/benchmark-build.log | 132 +- 09-benchmark/benchmark.log | 130 +- 09-benchmark/console.log.xz | Bin 3912 -> 3872 bytes 10-check_regression/console.log.xz | Bin 17788 -> 17660 bytes .../csv-results-vs-first-0/md5sum.csv | 2722 +- .../csv-results-vs-first-0/results.csv | 607488 +++++++++--------- .../csv-results-vs-first-0/size.csv | 605246 ++++++++--------- 10-check_regression/csv-results-vs-first-0/sve.csv | 30738 +- .../csv-results-vs-first-0/vect.csv | 1028 +- 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| 2 +- git/linux_rev | 2 +- mail/jira-body.txt | 48 +- mail/mail-body.txt | 48 +- mail/mail-subject.txt | 2 +- manifest.sh | 36 +- results_id | 2 +- save-temps/400.perlbench.tar.xz | Bin 401664 -> 1281720 bytes save-temps/401.bzip2.tar.xz | Bin 42728 -> 94476 bytes save-temps/403.gcc.tar.xz | Bin 1214176 -> 3567072 bytes save-temps/410.bwaves.tar.xz | Bin 0 -> 15100 bytes save-temps/416.gamess.tar.xz | Bin 0 -> 4210492 bytes save-temps/429.mcf.tar.xz | Bin 22308 -> 36580 bytes save-temps/433.milc.tar.xz | Bin 58720 -> 167760 bytes save-temps/434.zeusmp.tar.xz | Bin 0 -> 126512 bytes save-temps/435.gromacs.tar.xz | Bin 0 -> 979240 bytes save-temps/436.cactusADM.tar.xz | Bin 0 -> 725464 bytes save-temps/437.leslie3d.tar.xz | Bin 0 -> 46336 bytes save-temps/444.namd.tar.xz | Bin 44912 -> 168352 bytes save-temps/445.gobmk.tar.xz | Bin 620148 -> 1833032 bytes save-temps/447.dealII.tar.xz | Bin 878220 -> 6165516 bytes save-temps/450.soplex.tar.xz | Bin 207588 -> 709924 bytes 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save-temps/434.zeusmp.tar.xz create mode 100644 save-temps/435.gromacs.tar.xz create mode 100644 save-temps/436.cactusADM.tar.xz create mode 100644 save-temps/437.leslie3d.tar.xz create mode 100644 save-temps/454.calculix.tar.xz create mode 100644 save-temps/459.GemsFDTD.tar.xz create mode 100644 save-temps/465.tonto.tar.xz create mode 100644 save-temps/481.wrf.tar.xz -- To stop receiving notification emails like this one, please contact the administrator of this repository.

1 year, 9 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_bmk-vect_speed-cpu2017/llvm-aarch64-master-O3_VECT updated (153fdd4357 -> e6f65af51b)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_bmk-vect_speed-cpu2017/llvm-aarch64-master-O3_VECT in repository toolchain/ci/base-artifacts. from 153fdd4357 17: onsuccess: #9: 1: [TCWG CI] No change after binutils/gcc [...] new e6f65af51b 18: onsuccess: #10: 1: [TCWG CI] No change after binutils/gc [...] The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log.xz | Bin 1836 -> 1824 bytes 02-prepare_abe/console.log.xz | Bin 2776 -> 2776 bytes 03-build_abe-binutils/console.log.xz | Bin 31764 -> 32376 bytes 04-build_abe-stage1/console.log.xz | Bin 75292 -> 74572 bytes 06-build_abe-linux/console.log.xz | Bin 8692 -> 8672 bytes 07-build_abe-glibc/console.log.xz | Bin 247056 -> 247060 bytes 08-build_abe-stage2/console.log.xz | Bin 184128 -> 183120 bytes 09-build_llvm-true-false-cflags-/console.log.xz | Bin 62132 -> 61880 bytes 10-benchmark/benchmark-build.log | 100 +- 10-benchmark/benchmark.log | 98 +- 10-benchmark/console.log.xz | Bin 3796 -> 3824 bytes 11-check_regression/console.log.xz | Bin 8780 -> 8980 bytes .../csv-results-vs-first-1/md5sum.csv | 1118 +- .../csv-results-vs-first-1/perf.csv | 1452 +- .../csv-results-vs-first-1/results.csv | 16939 +++- .../csv-results-vs-first-1/size.csv | 15425 ++- 11-check_regression/csv-results-vs-first-1/sve.csv | 1 + .../csv-results-vs-prev-0/md5sum.csv | 1206 +- 11-check_regression/csv-results-vs-prev-0/perf.csv | 1446 +- .../csv-results-vs-prev-0/results.csv | 1891 +- 11-check_regression/csv-results-vs-prev-0/size.csv | 92827 ++++++++++--------- 11-check_regression/csv-results-vs-prev-0/sve.csv | 10 +- .../csv-results-vs-prev-1/md5sum.csv | 1118 +- 11-check_regression/csv-results-vs-prev-1/perf.csv | 1452 +- .../csv-results-vs-prev-1/results.csv | 16939 +++- 11-check_regression/csv-results-vs-prev-1/size.csv | 15425 ++- 11-check_regression/csv-results-vs-prev-1/sve.csv | 1 + 11-check_regression/results-vs-first-brief.csv | 33 +- 11-check_regression/results-vs-first-full.csv | 1498 +- 11-check_regression/results-vs-first-internal.csv | 85 +- 11-check_regression/results-vs-first.csv | 85 +- 11-check_regression/results-vs-first.log | 495 +- 11-check_regression/results-vs-prev-brief.csv | 33 +- 11-check_regression/results-vs-prev-full.csv | 1534 +- 11-check_regression/results-vs-prev-internal.csv | 85 +- 11-check_regression/results-vs-prev.csv | 85 +- 11-check_regression/results-vs-prev.log | 597 +- dashboard/dashboard-generate.sh | 2 +- .../600.perlbench_s/results-metadata.json | 18 +- .../600.perlbench_s/results-metrics.json | 4 +- .../squad-vs-first/602.gcc_s/results-metadata.json | 18 +- .../squad-vs-first/602.gcc_s/results-metrics.json | 2 +- .../squad-vs-first/605.mcf_s/results-metadata.json | 18 +- .../squad-vs-first/619.lbm_s/results-metadata.json | 18 +- .../620.omnetpp_s/results-metadata.json | 18 +- .../620.omnetpp_s/results-metrics.json | 2 +- .../623.xalancbmk_s/results-metadata.json | 18 +- .../623.xalancbmk_s/results-metrics.json | 2 +- .../625.x264_s/results-metadata.json | 18 +- .../squad-vs-first/625.x264_s/results-metrics.json | 2 +- .../631.deepsjeng_s/results-metadata.json | 18 +- .../638.imagick_s/results-metadata.json | 18 +- .../638.imagick_s/results-metrics.json | 2 +- .../641.leela_s/results-metadata.json | 18 +- .../641.leela_s/results-metrics.json | 2 +- .../squad-vs-first/644.nab_s/results-metadata.json | 18 +- .../squad-vs-first/644.nab_s/results-metrics.json | 2 +- .../results-functional.json | 0 .../{619.lbm_s => 657.xz_s}/results-metadata.json | 18 +- .../squad-vs-first/657.xz_s/results-metrics.json | 2 + .../squad-vs-first/Mean/results-metadata.json | 18 +- dashboard/squad-vs-first/Mean/results-metrics.json | 4 +- dashboard/squad-vs-first/dashboard-push-squad.sh | 57 +- git/binutils_rev | 2 +- git/gcc_rev | 2 +- git/glibc_rev | 2 +- git/linux_rev | 2 +- git/llvm_rev | 2 +- mail/jira-body.txt | 60 +- mail/mail-body.txt | 60 +- mail/mail-subject.txt | 2 +- manifest.sh | 42 +- results_id | 2 +- 73 files changed, 113901 insertions(+), 58570 deletions(-) copy dashboard/squad-vs-first/{600.perlbench_s => 657.xz_s}/results-functional.jso [...] copy dashboard/squad-vs-first/{619.lbm_s => 657.xz_s}/results-metadata.json (53%) create mode 100644 dashboard/squad-vs-first/657.xz_s/results-metrics.json -- To stop receiving notification emails like this one, please contact the administrator of this repository.

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